On Fri, Feb 20, 2009 at 02:03:08PM -0600, Douglas Geiger wrote:
> It looks like usrp2_impl.cc never passes on the argument when you call
> config_mimo - I've attached a quick patch that I believe does the job
> correctly.
> When I run my host code now the clocks on my USRP2's remain
> synchroniz
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Douglas Geiger wrote:
> Matt Ettus wrote:
>> Sync_to_pps is all about timestamps and the pps input, so it is not
>> related to whether or not the clock is locked.
>
> Right, got it.
>
>> Just to clarify the clocking architecture on the USRP2, there a
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Matt Ettus wrote:
> Sync_to_pps is all about timestamps and the pps input, so it is not
> related to whether or not the clock is locked.
Right, got it.
>
> Just to clarify the clocking architecture on the USRP2, there are
> basically 3 modes:
>
>
Douglas Geiger wrote:
Ok - now that I've discovered I had some bad cabling - specifically a
bad T-splitter: the side going to my O-scope worked, the side going to
my USRP2's did *not* - which I suppose can be chalked up to user error.
I am now able to synchronize the clocks - both with the firmw
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Matt Ettus wrote:
> Douglas Geiger wrote:
>> I'm at svn revision 10441 - with both the firmware and fpga code built
>> from that (using Xilinx ISE 10.1 to make the fpga). I've just modified
>> the txrx.c code - adding:
>> clocks_enable_test_clk(true, 2
Douglas Geiger wrote:
I'm at svn revision 10441 - with both the firmware and fpga code built
from that (using Xilinx ISE 10.1 to make the fpga). I've just modified
the txrx.c code - adding:
clocks_enable_test_clk(true, 2);
clocks_mimo_config(MC_WE_LOCK_TO_SMA);
just before the while(1) loop
My r
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Matt Ettus wrote:
>>
>> Ah - that's was the problem. Unfortunately my scope can only handle a
>> single channel at 100MHz, so setting the divisor >2 helps.
>> Unfortunately it appears the clock is not synchronized with my external
>> 10MHz clock - an
Ah - that's was the problem. Unfortunately my scope can only handle a
single channel at 100MHz, so setting the divisor >2 helps.
Unfortunately it appears the clock is not synchronized with my external
10MHz clock - any suggestions on further steps to debug why I'm having
trouble?
I don't und
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Matt Ettus wrote:
> Douglas Geiger wrote:
>>
>> Is the test clock supposed to be running at 5kHz? I've just tested this
>> on one of my USRP2 - it does appear to be locked with my external clock
>> - - i.e. the 5kHz signal on the pin doesn't drift w.r.
Douglas Geiger wrote:
Is the test clock supposed to be running at 5kHz? I've just tested this
on one of my USRP2 - it does appear to be locked with my external clock
- - i.e. the 5kHz signal on the pin doesn't drift w.r.t my 10Mhz external
No, the test clock runs as 100MHz/div where div is th
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Matt Ettus wrote:
> Changkyu Seol wrote:
>> Hi!
>>
>> I am planning to implement multiple synchronized transmitters using
>> USRP2 and GPS receiver. Before that I checked whether the USRP2 is
>> locked to external clock through following experiment.
>
Changkyu Seol wrote:
Hi!
I am planning to implement multiple synchronized transmitters using
USRP2 and GPS receiver. Before that I checked whether the USRP2 is
locked to external clock through following experiment.
The easiest way to check for lock is to put the following line in your
firmwa
On Wed, Feb 18, 2009 at 02:20:38AM +0100, Changkyu Seol wrote:
> Hi!
>
> I am planning to implement multiple synchronized transmitters using
> USRP2 and GPS receiver. Before that I checked whether the USRP2 is
> locked to external clock through following experiment.
>
> 1) Connect the 10MHz and 1
Hi!
I am planning to implement multiple synchronized transmitters using
USRP2 and GPS receiver. Before that I checked whether the USRP2 is
locked to external clock through following experiment.
1) Connect the 10MHz and 1PPS from GPS receiver (EP1S, Spectracom) to
USRP2's REF and PPS in port, resp
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