Hello, I'm starting this thread to discuss ideas about
support for many-core floating-points accelerators.
As it was said in wiki it could be for example:
-further development of Performance Counters
and Block Core Affinity
-implementing message passing using on-chip
Hi,
Hello, I'm starting this thread to discuss ideas about
support for many-core floating-points accelerators.
As it was said in wiki it could be for example:
-further development of Performance Counters
and Block Core Affinity
Shouldn't we work on actually _running_ any of
On Thu, Apr 18, 2013 at 4:16 AM, Andrew Back and...@carrierdetect.com wrote:
Hi Sylvain,
On 18 April 2013 08:56, Sylvain Munaut 246...@gmail.com wrote:
Hi,
Hello, I'm starting this thread to discuss ideas about
support for many-core floating-points accelerators.
As it was said in wiki it
Ideally, an architecture-aware scheduler could capitalize on all available
accelerators / heterogenous processors, and could maximize performance for that
system.
Unfortunately right now we're limited to porting a subset of blocks to these
accelerators.
Tommy James Tracy II
Ph.D Student
High
