Re: [Freedreno] [PATCH] drm/msm/a6xx: Fix build with !CONFIG_DEBUG_FS

2019-04-10 Thread Jordan Crouse
On Thu, Apr 04, 2019 at 10:02:07AM +0800, YueHaibing wrote: > On 2019/4/3 23:36, Jordan Crouse wrote: > > On Wed, Apr 03, 2019 at 02:48:11PM +0800, Yue Haibing wrote: > >> From: YueHaibing > >> > >> When building CONFIG_DEBUG_FS is not set > >> gcc wa

[PATCH] drm/msm/a6xx: Don't enable GPU state code if dependencies are missing

2019-04-10 Thread Jordan Crouse
Add CONFIG_DRM_MSM_GPU_STATE to conditionally compile Adreno GPU state code depending on the availability of the dependencies. Reported-by: Hulk Robot Reported-by: YueHaibing Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state") Signed-off-by: Jordan Crouse --- drivers/gpu/drm/m

Re: [PATCH 3/7] drm/msm: a5xx: fix possible object reference leak

2019-04-10 Thread Jordan Crouse
remented on line 51, but without a > corresponding object release within this function. > > Signed-off-by: Wen Yang > Cc: Rob Clark > Cc: Sean Paul > Cc: David Airlie > Cc: Daniel Vetter > Cc: Jordan Crouse > Cc: Mamta Shukla > Cc: Thomas Zimmermann >

Re: [PATCH] drm/msm/a6xx: Fix build with !CONFIG_DEBUG_FS

2019-04-03 Thread Jordan Crouse
On Wed, Apr 03, 2019 at 02:48:11PM +0800, Yue Haibing wrote: > From: YueHaibing > > When building CONFIG_DEBUG_FS is not set > gcc warn this: > > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c: In function a6xx_show: > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:1124:2: error: implicit >

Re: [PATCH v1 3/4] dt-bindings: drm/msm/gpu: Document a5xx / a6xx zap shader region

2019-04-01 Thread Jordan Crouse
On Thu, Mar 28, 2019 at 08:32:15AM -0500, Rob Herring wrote: > On Tue, Mar 12, 2019 at 12:13:41PM -0600, Jordan Crouse wrote: > > Describe the zap-shader node that defines a reserved memory region > > to store the zap shader. > > > > Signed-off-by: Jordan Crouse >

[PATCH v2] drm/msm/gpu: Add submit queue queries

2019-03-22 Thread Jordan Crouse
if it is responsible for any and if so it can invalidate itself. This is also helpful for testing by confirming to the user driver if a particular command stream caused a fault (or not as the case may be). Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 9 +++- drivers

[PATCH v1 0/4] drm/msm/a6xx: Add support for zap shader

2019-03-12 Thread Jordan Crouse
he final two patches add the DT bindings and DT settings for setting up the reserved memory that the shader requires. Jordan Crouse (4): drm/msm/gpu: Move zap shader loading to adreno drm/msm/a6xx: Add zap shader load dt-bindings: drm/msm/gpu: Document a5xx / a6xx zap shader region arm64:

[PATCH v1 1/4] drm/msm/gpu: Move zap shader loading to adreno

2019-03-12 Thread Jordan Crouse
a5xx and a6xx both share (mostly) the same code to load the zap shader and bring the GPU out of secure mode. Move the formerly 5xx specific code to adreno to make it available for a6xx too. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 109

[PATCH v1 2/4] drm/msm/a6xx: Add zap shader load

2019-03-12 Thread Jordan Crouse
M sequence this should fail and we would fall back to writing the register. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + 2 files changed, 38 insertions(+), 1 deletion(-)

[PATCH v1 3/4] dt-bindings: drm/msm/gpu: Document a5xx / a6xx zap shader region

2019-03-12 Thread Jordan Crouse
Describe the zap-shader node that defines a reserved memory region to store the zap shader. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b

[RFC PATCH v1 12/15] drm/msm: Add support to create target specific address spaces

2019-03-01 Thread Jordan Crouse
Add support to create a GPU target specific address space for a context. For those targets that support per-instance pagetables they will return a new address space set up for the instance if possible otherwise just use the global device pagetable. Signed-off-by: Jordan Crouse --- drivers/gpu

[RFC PATCH v1 13/15] drm/msm/gpu: Add ttbr0 to the memptrs

2019-03-01 Thread Jordan Crouse
Targets that support per-instance pagetable switching will have to keep track of which pagetable belongs to each instance to be able to recover for preemption. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu

[RFC PATCH v1 14/15] drm/msm/a6xx: Support per-instance pagetables

2019-03-01 Thread Jordan Crouse
Add support for per-instance pagetables for a6xx targets. Add support to handle split pagetables and create a new instance if the needed IOMMU support exists and insert the necessary PM4 commands to trigger a pagetable switch at the beginning of a user command. Signed-off-by: Jordan Crouse

[RFC PATCH v1 11/15] drm/msm: Add a helper function for a per-instance address space

2019-03-01 Thread Jordan Crouse
Add a helper function to create a GEM address space attached to an iommu auxiliary domain for a per-instance pagetable. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.h | 4 +++ drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++ 2 files changed

[RFC PATCH v1 15/15] drm/msm/a5xx: Support per-instance pagetables

2019-03-01 Thread Jordan Crouse
. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 120 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 19 + drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 70 + 3 files changed, 192 insertions(+), 17 deletions(-) diff

[RFC PATCH v1 07/15] drm/msm: Print all 64 bits of the faulting IOMMU address

2019-03-01 Thread Jordan Crouse
When we move to 64 bit addressing for a5xx and a6xx targets we will start seeing pagefaults at larger addresses so format them appropriately in the log message for easier debugging. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1

[RFC PATCH v1 10/15] drm/msm: Add support for IOMMU auxiliary domains

2019-03-01 Thread Jordan Crouse
Add support for creating a auxiliary domain from the IOMMU device to implement per-instance pagetables. Also add a helper function to return the pagetable base address (ttbr) and asid to the caller so that the GPU target code can set up the pagetable switch. Signed-off-by: Jordan Crouse

[RFC PATCH v1 09/15] drm/msm/gpu: Move address space setup to the GPU targets

2019-03-01 Thread Jordan Crouse
in some of the target files but I think it pays for itself in improved code flow and flexibility. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 37 -- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 50 ++ drivers/gpu/drm/msm

[RFC PATCH v1 08/15] drm/msm: Pass the MMU domain index in struct msm_file_private

2019-03-01 Thread Jordan Crouse
Pass the index of the MMU domain in struct msm_file_private instead of assuming gpu->id throughout the submit path. This clears the way to change ctx->aspace to a per-instance pagetable. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c| 2 ++ drivers/gpu/d

[RFC PATCH v1 06/15] drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets

2019-03-01 Thread Jordan Crouse
generating 32 bit addresses so switch over now to prepare for using addresses above 4G for targets that support them. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++ 2 files changed, 28 insertions

[RFC PATCH v1 00/15] drm/msm: Per-instance pagetable support

2019-03-01 Thread Jordan Crouse
, I want to make sure that this fits with the current thinking about how aux domains should look and feel. [1] https://patchwork.freedesktop.org/series/43447/ [2] https://patchwork.kernel.org/patch/10825061/ Jordan Crouse (15): iommu: Add DOMAIN_ATTR_SPLIT_TABLES iommu/arm-smmu: Add split

[PATCH] drm/msm: Fix incorrect struct size for memory allocation

2019-02-21 Thread Jordan Crouse
The allocation for the clock bulk data does a classic sizeof(pointer) instead of sizeof(struct) so the array ends up incorrectly sized for the clock data. Cc: sta...@vger.kernel.org Fixes: 8e54eea ("drm/msm: Add a helper function to parse clock names") Signed-off-by: Jordan Crouse ---

[PATCH] drm/msm: Remove pm_runtime calls from msm_iommu.c

2019-02-19 Thread Jordan Crouse
and egg problem. Luckily this is easily fixed by removing the pm_runtime calls from the functions and letting the device link to the IOMMU device handle the magic. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_iommu.c | 13 + 1 file changed, 1 insertion(+), 12 deletions

[PATCH RESEND] drm/msm: Truncate the buffer object name if the copy from user failed

2019-02-19 Thread Jordan Crouse
and fixed by Dan Carpenter. [1] https://patchwork.freedesktop.org/series/56656/ Fixes: f05c83e77460 ("drm/msm: add uapi to get/set debug name") Reported-by: Dan Carpenter Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 5 - 1 file changed, 4 insertions(+),

[PATCH] drm/msm: Truncate the buffer object name if the copy from user failed

2019-02-19 Thread Jordan Crouse
/ Fixes: f05c83e77460 ("drm/msm: add uapi to get/set debug name") Reported-by: Dan Carpenter Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_d

Re: [PATCH v1 2/6] dt-bindings: drm/msm/a6xx: Add GX power-domain for GMU bindings

2019-02-19 Thread Jordan Crouse
On Sun, Feb 17, 2019 at 05:43:16PM -0500, Rob Clark wrote: > On Sun, Feb 17, 2019 at 4:08 PM Rob Herring wrote: > > > > On Mon, Feb 4, 2019 at 10:15 AM Jordan Crouse > > wrote: > > > > > > The GMU should have two power domains defined: "cx"

Re: [Freedreno] [PATCH] drm/msm: fix an error code in the ioctl

2019-02-15 Thread Jordan Crouse
On Thu, Feb 14, 2019 at 06:16:01PM -0500, Rob Clark wrote: > On Thu, Feb 14, 2019 at 2:19 AM Dan Carpenter > wrote: > > > > The copy_to/from_user() functions return the number of bytes remaining > > to be copied but we should return -EFAULT to the user. > > > > Fixes: f05c83e77460 ("drm/msm: add

[PATCH v1 3/6] drm/msm/gpu: Attach to the GPU GX power domain

2019-02-04 Thread Jordan Crouse
power domain and does the magic to "enable" and disable it at the right points. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 41 ++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ 2 files changed, 42 insertions(+), 1 deletio

[PATCH v1 6/6] drm/msm/a6xx: Remove an unused struct member

2019-02-04 Thread Jordan Crouse
The HFI tasklet was removed in df0dff1 ("drm/msm/a6xx: Poll for HFI responses") but the tasklet_struct was accidentally left behind. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/

[PATCH v1 2/6] dt-bindings: drm/msm/a6xx: Add GX power-domain for GMU bindings

2019-02-04 Thread Jordan Crouse
The GMU should have two power domains defined: "cx" and "gx". "cx" is the actual power domain for the device and "gx" will be attached at runtime to manage reference counting on the GPU device in case of a GMU crash. Signed-off-by: Jordan Crouse --- D

[PATCH v1 1/6] drm/msm/a6xx: Remove unwanted regulator code

2019-02-04 Thread Jordan Crouse
The GMU code currently has some misguided code to try to work around a hardware quirk that requires the power domains on the GPU be collapsed in a certain order. Upcoming patches will do this the right way so get rid of the unused and unwanted regulator code. Signed-off-by: Jordan Crouse

[PATCH v1 0/6] drm/msm: Improved a6xx GMU reset

2019-02-04 Thread Jordan Crouse
. Jordan Crouse (6): drm/msm/a6xx: Remove unwanted regulator code dt-bindings: drm/msm/a6xx: Add GX power-domain for GMU bindings drm/msm/gpu: Attach to the GPU GX power domain drm/msm/a6xx: Make GMU reset useful msm/drm/a6xx: Turn off the GMU if resume fails drm/msm/a6xx: Remove an unused

[PATCH v1 4/6] drm/msm/a6xx: Make GMU reset useful

2019-02-04 Thread Jordan Crouse
Now that the GX domain is sorted we can wire up a working GMU reset. IF a GMU hang was detected then try to forcefully shut down the GMU in the power down sequence which should ensure that it can recover normally on the next power up. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno

[PATCH v1 5/6] msm/drm/a6xx: Turn off the GMU if resume fails

2019-02-04 Thread Jordan Crouse
-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 82 +++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 20 ++-- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + 3 files changed, 58 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/msm

Re: [PATCH v6] drm/msm/a6xx: Add support for an interconnect path

2019-01-18 Thread Jordan Crouse
On Fri, Jan 18, 2019 at 03:04:34PM -0800, Evan Green wrote: > On Fri, Jan 18, 2019 at 12:24 PM Jordan Crouse wrote: > > > > Try to get the interconnect path for the GPU and vote for the maximum > > bandwidth to support all frequencies. This is needed for performance. &

Re: [Freedreno] [PATCH v6] drm/msm/a6xx: Add support for an interconnect path

2019-01-18 Thread Jordan Crouse
On Fri, Jan 18, 2019 at 01:52:20PM -0800, Doug Anderson wrote: > Hi, > > On Fri, Jan 18, 2019 at 12:24 PM Jordan Crouse wrote: > > > > Try to get the interconnect path for the GPU and vote for the maximum > > bandwidth to support all frequencies. This is needed fo

Re: [Freedreno] [PATCH v6] drm/msm/a6xx: Add support for an interconnect path

2019-01-18 Thread Jordan Crouse
On Fri, Jan 18, 2019 at 01:24:18PM -0700, Jordan Crouse wrote: > Try to get the interconnect path for the GPU and vote for the maximum > bandwidth to support all frequencies. This is needed for performance. > Later we will want to scale the bandwidth based on the frequency to > a

[PATCH v6] drm/msm/a6xx: Add support for an interconnect path

2019-01-18 Thread Jordan Crouse
not yet exist. v6: use icc_set_bw() instead of icc_set() v5: Remove hardcoded interconnect name and just use the default v4: Don't use a port string at all to skip the need for names in the DT v3: Use macros and change port string per Georgi Djakov Signed-off-by: Jordan Crouse --- drivers/gpu/drm

[PATCH] dt-bindings: drm/msm/a6xx: Document GMU bindings

2019-01-16 Thread Jordan Crouse
Commit 24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings") mistakenly omitted the GMU bindings as seen in [1]. Return them to their rightful place. [1] https://patchwork.freedesktop.org/patch/268679/ Signed-off-by: Jordan Crouse Reviewed-by: R

Re: [PATCH v2 1/2] drm/msm: Fix A6XX support for opp-level

2019-01-16 Thread Jordan Crouse
f a tree contains the device tree > patch but not this one you'll get a crash at bootup. > > Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support") > Signed-off-by: Douglas Anderson I agree that splitting these out make sense for the workflow. Reviewed-by: Jordan Crouse &g

[PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes

2019-01-16 Thread Jordan Crouse
Add the nodes to describe the Adreno GPU and GMU devices for sdm845. Signed-off-by: Jordan Crouse Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson --- This has the following dependencies: [v11,1/9] dt-bindings: opp: Introduce opp-level bindings https://patchwork.kernel.org/patch

Re: [PATCH] drm/msm: Fix A6XX support for opp-level

2019-01-11 Thread Jordan Crouse
gt; land in a tree that contains that patch. > > This patch needs to land before the patch ("arm64: dts: sdm845: Add > gpu and gmu device nodes") since if a tree contains the device tree > patch but not this one you'll get a crash at bootup. > > Signed-off-by: Douglas Anderso

Re: [PATCH] drm/msm/gpu: fix bo size for msm_rbmemptrs

2018-12-20 Thread Jordan Crouse
On Thu, Dec 20, 2018 at 10:47:02AM -0800, Chia-I Wu wrote: > memptrs_bo is used to store msm_rbmemptrs. Size it correctly. > > Signed-off-by: Chia-I Wu Thanks for your patch. I'm really glad somebody is looking seriously at this code. We have this in msm-next:

Re: [Freedreno] [PATCH] drm/msm/a6xx: add a6xx_gpu_state_get

2018-12-20 Thread Jordan Crouse
On Thu, Dec 20, 2018 at 10:46:45AM -0800, Chia-I Wu wrote: > It gets the generic states from the adreno core. > > This also adds a missing NULL check in msm_gpu_open. > > Signed-off-by: Chia-I Wu Thanks for the patch. We have an expanded version of the 6xx gpu state in msm-next [1]. You can

[PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

2018-12-20 Thread Jordan Crouse
not yet exist. v5: Remove hardcoded interconnect name and just use the default v4: Don't use a port string at all to skip the need for names in the DT v3: Use macros and change port string per Georgi Djakov Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Kconfig | 1 + drivers

[PATCH v3 2/3] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

2018-12-20 Thread Jordan Crouse
Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gpu.txt | 4 1 file changed, 4 insertions(+) diff --git

[PATCH v3 0/3] arm64: dts: sdm845: Add sdm845 GPU interconnect

2018-12-20 Thread Jordan Crouse
interconnect name from driver and bindings Jordan Crouse (3): drm/msm/a6xx: Add support for an interconnect path dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU arm64: dts: sdm845: Add interconnect for GPU .../devicetree/bindings/display/msm/gpu.txt | 4 arch/arm64

Re: [PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

2018-12-18 Thread Jordan Crouse
On Tue, Dec 18, 2018 at 02:29:25PM -0800, Doug Anderson wrote: > Hi, > > On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse wrote: > > > > 'interrupt-names' shouldn't be used in cases when there is only > > one interrupt and it is not otherwise used in the driver. &g

[PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

2018-12-18 Thread Jordan Crouse
Update the GPU bindings and document the new bindings for the GMU device found with Adreno a6xx targets. Signed-off-by: Jordan Crouse --- v7: Updated the GMU compatible string and clarified details about when clocks can be optional on the GPU .../devicetree/bindings/display/msm/gmu.txt | 59

[PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

2018-12-18 Thread Jordan Crouse
Add the nodes to describe the Adreno GPU and GMU devices. Signed-off-by: Jordan Crouse --- v7: Updated the GMU compatible string and removed interrupt-names arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot

[PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

2018-12-18 Thread Jordan Crouse
indentation, really use qcom,gmu for the phandle name v2: changed qcom,arc-level to qcom,level following discussion with Viresh; change gmu phandle to qcom,gmu per Rob Jordan Crouse (6): drm/msm/gpu: Remove hardcoded interrupt name drm/msm: drop interrupt-names ARM: dts: qcom: Removed unused

[PATCH v7 1/6] drm/msm/gpu: Remove hardcoded interrupt name

2018-12-18 Thread Jordan Crouse
Every GPU core only has one interrupt so there isn't any value in looking up the interrupt by name. Remove the name (which is legacy anyway) and use platform_get_irq() instead. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - drivers/gpu/drm/msm/msm_gpu.c

[PATCH v7 4/6] arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU

2018-12-18 Thread Jordan Crouse
'interrupt-names' shouldn't be used in cases when there is only one interrupt and it is not otherwise used in the driver. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64

[PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

2018-12-18 Thread Jordan Crouse
'interrupt-names' shouldn't be used in cases when there is only one interrupt and it is not otherwise used in the driver. Signed-off-by: Jordan Crouse --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot

[PATCH v7 2/6] drm/msm: drop interrupt-names

2018-12-18 Thread Jordan Crouse
Each GPU core only uses one interrupt so we don't to look up an interrupt by name and thereby we don't need interrupt-names. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gpu.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree

Re: [PATCH v2 1/2] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

2018-12-18 Thread Jordan Crouse
On Tue, Dec 18, 2018 at 11:22:01AM -0600, Rob Herring wrote: > On Fri, Dec 14, 2018 at 03:16:39PM -0700, Jordan Crouse wrote: > > Add documentation for the interconnect and interconnect-names bindings > > for the GPU node as detailed by bindings/interconnect/interconnect.txt. >

Re: [Freedreno] [v1] drm/msm/dpu: Cleanup dpu plane interface

2018-12-18 Thread Jordan Crouse
On Tue, Dec 18, 2018 at 06:50:38PM +0530, Jayant Shekhar wrote: > Remove unused functions from dpu plane interface > and unused variables from dpu plane state structure. > > Signed-off-by: Jayant Shekhar Reviewed-by: Jordan Crouse > --- > drivers/gpu/drm/msm/disp/dpu

Re: [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

2018-12-17 Thread Jordan Crouse
On Mon, Dec 17, 2018 at 03:20:10PM -0600, Rob Herring wrote: > On Wed, Dec 12, 2018 at 02:18:47PM -0700, Jordan Crouse wrote: > > Update the GPU bindings and document the new bindings for the GMU > > device found with Adreno a6xx targets. > > > > S

[PATCH v2 1/2] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

2018-12-14 Thread Jordan Crouse
Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gpu.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCH v2 2/2] arm64: dts: sdm845: Add interconnect for GPU

2018-12-14 Thread Jordan Crouse
Define an interconnect port for the GPU to set bus capabilities. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a5ddfc4c59b

[PATCH v2 0/2] arm64: dts: sdm845: Add sdm845 GPU interconnect

2018-12-14 Thread Jordan Crouse
to match latest per Doug Anderson *** BLURB HERE *** Jordan Crouse (2): dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU arm64: dts: sdm845: Add interconnect for GPU Documentation/devicetree/bindings/display/msm/gpu.txt | 6 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi

Re: [PATCH v3 2/3] drm/msm/dpu: handle failures while initializing displays

2018-12-14 Thread Jordan Crouse
On Thu, Dec 13, 2018 at 10:51:03AM -0800, Jeykumar Sankaran wrote: > Bail out KMS hw init on display initialization failures with > proper error logging. > > changes in v3: > - introduced in the series > > Signed-off-by: Jeykumar Sankaran > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |

Re: [Freedreno] [DPU PATCH] drm/msm/dpu: Clean up dpu hw interrupts

2018-12-14 Thread Jordan Crouse
On Fri, Dec 14, 2018 at 02:19:12PM +0530, Jayant Shekhar wrote: > Remove unused functions and macros from dpu hw interrupts > file. > > Signed-off-by: Jayant Shekhar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 30 >

Re: [PATCH v3 3/3] drm/msm/dpu: add display port support in DPU

2018-12-14 Thread Jordan Crouse
in v2: > - rebase on [2] (Sean Paul) > - remove unwanted error checks and > switch cases (Jordan Crouse) > changes in v3: > - add dp support after fixing > the current code base for error logging (Sean Paul) > > [1] https://lwn.net/Articles/7

[PATCH 2/2] arm64: dts: sdm845: Add interconnect for GPU

2018-12-13 Thread Jordan Crouse
Define an interconnect port for the GPU to set bus capabilities. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a5ddfc4c59b

[PATCH 0/2] arm64: dts: sdm845: Add sdm845 GPU interconnect

2018-12-13 Thread Jordan Crouse
Two quick patches to document and add an interconnect port definition for the sdm845 GPU. This is based on the base GPU DT changes: https://patchwork.freedesktop.org/series/39308/ As well as the DT nodes from Georgi: https://patchwork.kernel.org/patch/10719483/ Jordan Crouse (2): dt-bindings

[PATCH 1/2] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

2018-12-13 Thread Jordan Crouse
Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gpu.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCH v6 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU

2018-12-12 Thread Jordan Crouse
device. v4: Rebase v3: Split GMU PDC region into two GPU specific sections, fix indentation, really use qcom,gmu for the phandle name v2: changed qcom,arc-level to qcom,level following discussion with Viresh; change gmu phandle to qcom,gmu per Rob *** BLURB HERE *** Jordan Crouse (2): dt

[PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

2018-12-12 Thread Jordan Crouse
Update the GPU bindings and document the new bindings for the GMU device found with Adreno a6xx targets. Signed-off-by: Jordan Crouse --- .../devicetree/bindings/display/msm/gmu.txt | 56 +++ .../devicetree/bindings/display/msm/gpu.txt | 41 +- 2 files changed

[PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

2018-12-12 Thread Jordan Crouse
Add the nodes to describe the Adreno GPU and GMU devices. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index

Re: [PATCH v5 1/2] dt-bindings: Document,qcom,adreno-gmu

2018-12-12 Thread Jordan Crouse
On Wed, Dec 12, 2018 at 11:26:46AM -0800, Doug Anderson wrote: > Hi, > > On Wed, Dec 12, 2018 at 9:31 AM Jordan Crouse wrote: > > > > Document the device tree bindings for the Adreno GMU device > > available on Adreno a6xx targets. > > > > Reviewed-by:

[PATCH v5 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU

2018-12-12 Thread Jordan Crouse
of their respective nodes and rename the iommu device. v4: Rebase v3: Split GMU PDC region into two GPU specific sections, fix indentation, really use qcom,gmu for the phandle name v2: changed qcom,arc-level to qcom,level following discussion with Viresh; change gmu phandle to qcom,gmu per Rob Jordan

[PATCH v5 1/2] dt-bindings: Document,qcom,adreno-gmu

2018-12-12 Thread Jordan Crouse
Document the device tree bindings for the Adreno GMU device available on Adreno a6xx targets. Reviewed-by: Rob Herring Signed-off-by: Jordan Crouse --- .../devicetree/bindings/display/msm/gmu.txt | 54 +++ .../devicetree/bindings/display/msm/gpu.txt | 2 + 2 files changed

[PATCH v5 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

2018-12-12 Thread Jordan Crouse
Add the nodes to describe the Adreno GPU and GMU devices. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index

Re: [PATCH 2/2] drm/msm/a6xx: Fix NULL dereference during crashstate capture

2018-12-11 Thread Jordan Crouse
On Mon, Dec 10, 2018 at 05:34:22PM +0530, Sharat Masetty wrote: > The gpu crashstate's base objects registers pointer can be NULL if the > target implementation decides to capture the register dump on its own. > This patch simply checks for NULL before dereferencing. Hi Sharat - this doesn't

Re: [PATCH 1/2] drm/msm/adreno: Make adreno_gpu_state_get() return void

2018-12-10 Thread Jordan Crouse
On Mon, Dec 10, 2018 at 05:34:21PM +0530, Sharat Masetty wrote: > We are not really checking the state of the adreno_gpu_state_get() > function at the callers and in addition the state capture is mostly a > best effort service, so make the function return void. Reviewed-by: Jord

Re: [PATCH 2/2] drm/msm/a6xx: Fix NULL dereference during crashstate capture

2018-12-10 Thread Jordan Crouse
On Mon, Dec 10, 2018 at 05:34:22PM +0530, Sharat Masetty wrote: > The gpu crashstate's base objects registers pointer can be NULL if the > target implementation decides to capture the register dump on its own. > This patch simply checks for NULL before dereferencing. > > Signed-off-by: Sharat

Re: [Freedreno] [PATCH] drm/msm/a6xx: Add support for an interconnect path

2018-12-07 Thread Jordan Crouse
On Fri, Dec 07, 2018 at 10:06:56AM -0700, Jordan Crouse wrote: > Try to get the interconnect path for the GPU and vote for the maximum > bandwidth to support all frequencies. This is needed for performance. > Later we will want to scale the bandwidth based on the frequency to > a

[PATCH] drm/msm/a6xx: Add support for an interconnect path

2018-12-07 Thread Jordan Crouse
not yet exist. v3: Use macros and change port string per Georgi Djakov Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 + drivers/gpu/drm/msm

[PATCH v3 03/10] drm/msm/dpu: Remove dpu_crtc_is_enabled()

2018-12-03 Thread Jordan Crouse
The static inline function dpu_crtc_enabled() is only called once and the function that calls it in turn is only called once and the return value can be easily checked in the calling functions so collapse everything down. v3: No changes Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse

[PATCH v3 06/10] drm/msm: Make irq_postinstall optional

2018-12-03 Thread Jordan Crouse
Allow the KMS operation 'irq_postinstall' to be optional so that the target display drivers don't need to define a dummy function if they don't need one. v3: No changes Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 6 +- 1 file changed, 5

[PATCH v3 09/10] drm/msm/dpu: Further cleanups for static inline functions

2018-12-03 Thread Jordan Crouse
. Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 10 -- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11

[PATCH v3 08/10] drm/msm/dpu: Cleanup the debugfs functions

2018-12-03 Thread Jordan Crouse
away too. Also, use standard API functions where applicable instead of using hand written code. v3: No changes v2: Add more code; most of the dpu debugfs files should be addressed now. Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 30

[PATCH v3 00/10] drm/msm/dpu: cleanups

2018-12-03 Thread Jordan Crouse
that I dropped ("drm/msm/dpu: Use DEFINE_SHOW_ATTRIBUTE") in favor of https://patchwork.freedesktop.org/patch/265159/ Which does the same thing but is a little bit more tree-wide in its efforts. Jordan Crouse (10): drm/msm/dpu: Remove dpu_dbg drm/msm/dpu: Remove dpu_crtc_get_mixer_he

[PATCH v3 01/10] drm/msm/dpu: Remove dpu_dbg

2018-12-03 Thread Jordan Crouse
Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Makefile |3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 2393 - drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 103 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |4

[PATCH v3 04/10] drm/msm/dpu: Remove unused functions

2018-12-03 Thread Jordan Crouse
Remove some unused container_of() helper functions. v3: No changes v2: Retained still used helper functions in the name of readability Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 10 -- drivers/gpu/drm/msm/disp/dpu1

[PATCH v3 10/10] drm/msm/dpu: Clean up dpu_media_info.h static inline functions

2018-12-03 Thread Jordan Crouse
Do some cleanup in the static inline functions defined in dpu_media_info.h by cleaning up gotos and unneeded local variables. v3: Added spaces between operators per Seal Paul and Sam Ravnborg Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- .../gpu/drm/msm/disp/dpu1/msm_media_info.h

[PATCH v3 02/10] drm/msm/dpu: Remove dpu_crtc_get_mixer_height

2018-12-03 Thread Jordan Crouse
dpu_crtc_get_mixer_height() is only used once and the value it returns can be easily derived from the calling function. v3: No changes Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 13

[PATCH v3 07/10] drm/msm/dpu: Remove dpu_irq and unused functions

2018-12-03 Thread Jordan Crouse
path. v3: No changes Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 15 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 7 --- drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 66

[PATCH v3 05/10] drm/msm/dpu: Cleanup callers of dpu_hw_blk_init

2018-12-03 Thread Jordan Crouse
: No changes v2: Removed a cleanup intended for a different patch Reviewed-by: Sean Paul Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 17

[PATCH] drm/msm/a6xx: Remove unwanted regulator code

2018-12-03 Thread Jordan Crouse
The GMU code currently has some misguided code to try to work around a hardware quirk that requires the power domains on the GPU be collapsed in a certain order. Future changes will do this the right way so get rid of the unused and unwanted regulator code. Signed-off-by: Jordan Crouse

[PATCH] drm/msm/a6xx: Add a name for the crashdumper buffer

2018-12-03 Thread Jordan Crouse
Add a buffer object name for the a6xx crashdumper so it can be seen with the changes introduced by 7799a98edd ("drm/msm: Add a name field for gem objects"). Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 5 - 1 file changed, 4 insertions(+),

[PATCH] drm/msm/a6xx: Use new kernel API free function for gpu state

2018-12-03 Thread Jordan Crouse
dadb36b7ec42 ("drm/msm: Add a common function to free kernel buffer objects") missed freeing the crashdumper state for a6xx. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/d

Re: [PATCH v3 1/1] drm: msm: Replace dma_map_sg with dma_sync_sg*

2018-11-29 Thread Jordan Crouse
On Thu, Nov 29, 2018 at 01:48:15PM -0500, Rob Clark wrote: > On Thu, Nov 29, 2018 at 10:54 AM Christoph Hellwig wrote: > > > > On Thu, Nov 29, 2018 at 09:42:50AM -0500, Rob Clark wrote: > > > Maybe the thing we need to do is just implement a blacklist of > > > compatible strings for devices which

[PATCH 1/1] drm/msm/a6xx: Add support for an interconnect path

2018-11-29 Thread Jordan Crouse
not yet exist. v3: Absolute bandwidth values should be specified in KBps Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 + drivers/gpu/drm/msm/msm_gpu.h | 3 +++ 3 files changed, 32

[PATCH v3 0/1] drm/msm/a6xx: Add interconnect support

2018-11-29 Thread Jordan Crouse
and passed a value that overflowed the API. Correct bandwidth values are now passed. [1] https://lists.freedesktop.org/archives/freedreno/2018-November/004347.html v3: Actually send correct patch with correct units v2: Make sure to pass values in correct units Jordan Crouse (1): drm/msm/a6xx: Add

[PATCH v2 0/1] drm/msm/a6xx: Add interconnect support

2018-11-29 Thread Jordan Crouse
://lists.freedesktop.org/archives/freedreno/2018-November/004347.html v2: Make sure to pass values in correct units Jordan Crouse (1): drm/msm/a6xx: Add support for an interconnect path drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 + drivers

[PATCH 1/1] drm/msm/a6xx: Add support for an interconnect path

2018-11-29 Thread Jordan Crouse
not yet exist. v2: Absolute bandwidth values should be in KBps Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 + drivers/gpu/drm/msm/msm_gpu.h | 3 +++ 3 files changed, 32

Re: [Freedreno] [PATCH v3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

2018-11-28 Thread Jordan Crouse
On Thu, Nov 01, 2018 at 07:25:23PM -0700, Jeykumar Sankaran wrote: > DPU is short for the Display Processing Unit. It is the display > controller on Qualcomm SDM845 chips. > > This change adds MDSS and DSI nodes to enable display on the > target device. > > Changes in v2: >- Beefed up

[PATCH 0/1] drm/msm/a6xx: Add interconnect support

2018-11-28 Thread Jordan Crouse
/ Jordan Crouse (1): drm/msm/a6xx: Add support for an interconnect path drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 + drivers/gpu/drm/msm/msm_gpu.h | 3 +++ 3 files changed, 32 insertions(+) -- 2.18.0

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