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the bug.
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From: Gustavo Padovan
Change SYNC_IOC_FILE_INFO behaviour to avoid future API breaks and
optimize buffer allocation. In the new approach the ioctl needs to be called
twice to retrieve the array of fence_infos pointed by info->sync_fence_info.
The first call
Hi,
On 26 February 2016 at 16:54, Archit Taneja wrote:
> Hi,
>
> I had some minor comments. Sorry about sharing this late. Otherwise,
> the looks good to me.
Hi Archit, you are welcome :-)
Thanks for review again.
>
>
> On 02/26/2016 02:10 PM, Xinliang Liu wrote:
>>
>> Add kirin DRM master
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
v3: Refactor degamma/gamma LUTs load into a single function
v4: Remove unused variable
Signed-off-by: Shashank Sharma
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
Signed-off-by: Lionel Landwerlin
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by CTM
v4: Update contributors
v5: Refactor
Patch based on a previous series by Shashank Sharma.
This introduces optional properties to enable color correction at the
pipe level. It relies on 3 transformations applied to every pixels
displayed. First a lookup into a degamma table, then a multiplication
of the rgb components by a 3x3 matrix
Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.
v2: Read GAMMA_MODE register value at init (Matt Roper's comment)
v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along
with other registers (Matt Roper's comment).
v4: Mask
The moves a couple of functions programming the gamma LUT and CSC
units into their own file.
On generations prior to Haswell there is only a gamma LUT. From
haswell on there is also a new enhanced color correction unit that
isn't used yet. This is why we need to set the GAMMA_MODE register,
This series introduces pipe level color management through a set of properties
attached to the CRTC. It also provides an implementation for some Intel
platforms.
This series is based of a previous set of patches by Shashank Sharma.
Cheers,
Lionel
v9: Rebase on nightly
v10: Mask GAMMA_MODE
Add ade, dsi and adv7533 DT nodes for hikey board.
Signed-off-by: Xinliang Liu
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 40 +++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 55 ++
2 files changed, 95 insertions(+)
diff --git
Add maintainer and reviewer for hisilicon DRM driver.
v6: None.
v5: None.
v4:
- Add Chen Feng as Designated reviewer.
v3: First version.
Signed-off-by: Xinliang Liu
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Add support for external HDMI bridge.
v6: None.
v5: None.
v4: None.
v3:
- Fix a typo: s/exteranl/external.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 52
1 file changed, 52 insertions(+)
diff --git
Add DesignWare dsi host driver for hi6220 SoC.
v6: None.
v5: None.
v4: None.
v3: None.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 50
1 file changed, 50 insertions(+)
diff --git
Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
for hi6220 SoC.
v6:
- Change "pclk_dsi" to "pclk".
v5: None.
v4: None.
v3:
- Rename file name to dw_drm_dsi.c
- Make encoder type as DRM_MODE_ENCODER_DSI.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
Add cma Fbdev, Fbdev is legency and optional, you can enable/disable it by
configuring DRM_FBDEV_EMULATION.
Add hotplug.
v6: None.
v5: None.
v4: None.
v3: None.
v2:
- Use CONFIG_DRM_FBDEV_EMULATION instead of CONFIG_DRM_HISI_FBDEV.
Signed-off-by: Xinliang Liu
---
Add vblank irq handle.
v6: None.
v5: None.
v4: None.
v3:
- Remove hisi_get_crtc_from_index func.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 62 +
Add plane funcs and helper funcs for ADE.
v6: None.
v5: None.
v4: None.
v3:
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 535 +++-
1 file changed, 534 insertions(+), 1 deletion(-)
diff
Add crtc funcs and helper funcs for ADE.
v6:
- Cleanup reg-names dt parsing.
v5:
- Use syscon to access ADE media NOC QoS registers instread of directly
writing registers.
- Use reset controller to reset ADE instead of directly writing registers.
v4: None.
v3:
- Make ade as the master driver.
-
Add kirin DRM master driver for hi6220 SoC which used in HiKey board.
Add dumb buffer feature.
Add prime dmabuf feature.
v6: None.
v5: None.
v4: None.
v3:
- Move and rename all the files to kirin sub-directory.
So that we could separate different seires SoCs' driver.
- Replace
Add ADE display controller binding doc.
Add DesignWare DSI Host Controller v1.20a binding doc.
v6:
- Cleanup values part of reg and clocks properties.
- Change "pclk_dsi" clock name to "pclk".
v5:
- Remove endpoint unit address of dsi output port.
- Add "hisilicon,noc-syscon" property for ADE NOC
This patch set adds a new drm driver for HiSilicon Kirin hi6220 SoC.
Current testing and support board is Hikey board which is one of Linaro
96boards. It is an arm64 open source board. For more information about
this board, please access https://www.96boards.org.
Hardware Detail
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On pe, 2016-02-26 at 00:20 +0200, Imre Deak wrote:
> On Thu, 2016-02-25 at 21:10 +, Chris Wilson wrote:
> > commit 09731280028ce03e6a27e1998137f1775a2839f3
> > Author: Imre Deak
> > Date:Â Â Â Wed Feb 17 14:17:42 2016 +0200
> >
> > Â Â Â Â drm/i915: Add helper to get a display power ref if
On 26/02/16 00:36, Emil Velikov wrote:
> Hi Lionel,
>
> A bunch of suggestions - feel free to take or ignore them :-)
>
> On 25 February 2016 at 10:58, Lionel Landwerlin
> wrote:
>> Patch based on a previous series by Shashank Sharma.
>>
>> This introduces optional properties to enable color
From: Gustavo Padovan
Play safe and add flags member to all structs. So we don't need to
break API or create new IOCTL in the future if new features that requires
flags arises.
v2: check if flags are valid (zero, in this case)
Signed-off-by: Gustavo Padovan
From: Gustavo Padovan
Change SYNC_IOC_FILE_INFO behaviour to avoid future API breaks and
optimize buffer allocation. In the new approach the ioctl needs to be called
twice to retrieve the array of fence_infos pointed by info->sync_fence_info.
The first call
From: Gustavo Padovan
struct sync_merge_data already have documentation on top of the
struct definition. No need to duplicate it.
Signed-off-by: Gustavo Padovan
---
drivers/staging/android/uapi/sync.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
From: Gustavo Padovan
We don't use the 'fence' name to refer to sync_file anymore. So rename it
to SYNC_IOC_FILE_INFO.
Signed-off-by: Gustavo Padovan
---
drivers/staging/android/sync.c | 2 +-
drivers/staging/android/uapi/sync.h | 2 +-
2 files changed, 2
From: Gustavo Padovan
Inform userspace how many fences are in the sync_fence_info field.
Signed-off-by: Gustavo Padovan
---
drivers/staging/android/sync.c | 2 ++
drivers/staging/android/uapi/sync.h | 2 ++
2 files changed, 4 insertions(+)
diff --git
Hi
On Fri, Feb 12, 2016 at 8:50 PM, Haixia Shi wrote:
> v1: Remove the general drm_device_is_unplugged() checks, and move the
> unplugged
> flag handling logic into drm/udl. In general we want to keep driver-specific
> logic out of common drm code.
>
> v2: Based on discussion with Stephane and
During DRAM initialization on certain ASpeed devices, an incorrect
bit (bit 10) was checked in the "SDRAM Bus Width Status" register
to determine DRAM width.
Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05.
Signed-off-by: Timothy Pearson
---
are the assignee for the bug.
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Hi
On Thu, Feb 25, 2016 at 10:09 PM, Arnd Bergmann wrote:
> gcc warns about the timestamp in drm_wait_vblank being possibly
> used without an initialization:
>
> drivers/gpu/drm/drm_irq.c: In function 'drm_wait_vblank':
> drivers/gpu/drm/drm_irq.c:1755:28: warning: 'now.tv_usec' may be used
>
Dan,
On 02/26/2016 05:30 AM, Dan Carpenter wrote:
> We were accidentally returning PTR_ERR(NULL) which means success when we
> wanted to return a negative error code.
>
> Fixes: 412d4ae6b7a5 ('drm/rockchip: hdmi: add Innosilicon HDMI support')
> Signed-off-by: Dan Carpenter
Reviewed-by: Yakir
Hi,
I had some minor comments. Sorry about sharing this late. Otherwise,
the looks good to me.
On 02/26/2016 02:10 PM, Xinliang Liu wrote:
> Add kirin DRM master driver for hi6220 SoC which used in HiKey board.
> Add dumb buffer feature.
> Add prime dmabuf feature.
>
> v6: None.
> v5: None.
>
On 02/26/2016 04:34 AM, Laurent Pinchart wrote:
> Hi Archit,
>
> Thank you for the patch, I finally got around to testing it. Sorry for the
> delay.
>
> On Saturday 09 January 2016 22:22:26 Archit Taneja wrote:
>> The hdmi output in rcar-du uses the i2c slave encoder interface to link
>> to the
On 26 February 2016 at 13:04, Linus Torvalds
wrote:
> On Thu, Feb 25, 2016 at 6:20 PM, Dave Airlie wrote:
>>
>> This is a bit larger than Id like, but I asked the Intel guys to pull in
>> some Skylake fixes in the possibly vain hope that Skylake might be more
>> functional now that I'm seeing
The exynos drm driver implements power management functions that
are hidden inside of #ifdef, but when they are all disabled,
we get a warning about another unused function that is not
called from elsewhere:
drivers/gpu/drm/exynos/exynos_drm_gsc.c:1219:12: error: 'gsc_clk_ctrl' defined
but not
The VSP1 compositor code in DRM links against the respective V4L
driver, but the dependency is not expressed correctly in Kconfig,
which leads to a build error when the DRM driver is built-in
and the V4L driver is a module:
drivers/gpu/built-in.o: In function `rcar_du_vsp_plane_atomic_update':
On Thu, Feb 25, 2016 at 2:47 AM, Dan Carpenter
wrote:
> It's simpler to just use snprintf() to print this to one buffer instead
> of using strcpy() and strcat(). Also using snprintf() is slightly safer
> than using sprintf().
>
> Signed-off-by: Dan Carpenter
Applied. Thanks!
>
> diff --git
On 02/26/16 02:43, Russell King - ARM Linux wrote:
> On Thu, Feb 25, 2016 at 03:42:50PM +0200, Jyri Sarha wrote:
>> On 02/18/16 16:35, Rob Herring wrote:
>>> This should be implied from the port unit address. In other words,
>>> port at 0 is defined to be the rgb port. Now, if this is one of
Instead of forcing bridges to implement empty callbacks make them all
optional.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/drm_bridge.c | 12
include/drm/drm_crtc.h | 8
2 files changed, 16 insertions(+), 4
On 2/26/2016 12:11 AM, Joseph Salisbury wrote:
> On 02/24/2016 10:53 PM, Jindal, Sonika wrote:
>> Hi Joe,
>>
>> Yes, first thing to try is to increase the tries.
> We testing with 300 retries, but the second monitor still did not show
> up. However, it did show up in lspci.
>
>
>> Can you
omapdrm is missing a check on the validity of the rotation property.
This leads to omapdrm possibly trying to use rotation on non-rotateable
framebuffer, which causes the overlay setup to fail.
This patch adds the necessary check to omap_plane_atomic_check().
Signed-off-by: Tomi Valkeinen
Before universal planes we had to have plane specific properties for the
crtc too, as on the hardware level a crtc uses a plane. In other words,
e.g. 'zorder' property was added to both planes and crtcs, and
omap_crtc.c would delegate the property set/get to the primary plane.
However, the
From: Rob Clark
Subsequent threads returning EBUSY from vm_insert_pfn() was not
handled correctly. As a result concurrent access from new threads
to mmapped data caused SIGBUS.
See e79e0fe380847493266fba557217e2773c61bd1b ("drm/i915: EBUSY status
handling added to
The DSS hardware uses the same ROW_INC value for both Y and UV planes
for NV12 format. This means that the pitches of the Y and UV planes have
to match. omapdrm doesn't check this at the moment, and this can lead
into a broken NV12 fb on the screen.
This patch adds the check.
Signed-off-by: Tomi
DISPC requires the x resolution to be divisible by 8 when stall mode is
not used.
Add a check to the DPI driver to verify this.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dpi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c
Now that interlace support has been added, we can remove the check that
prevents interlace.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/hdmi5.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
Add the missing bits for interlace:
* Set VBLANK_OSC if the videomode's vblank is fractional
* Halve the vertical timings for interlace
* Double the horizontal timings for double-pixel mode
* Set FC_PRCONF properly for double-pixel mode
Signed-off-by: Tomi Valkeinen
---
The HDMI driver copies the timing values one by one. Instead we can just
copy the whole struct.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
For some reason the HDMI FC's HSW value is programmed to hsw-1. There's
no indication in the documentation that this would be correct, and no
other blanking value needs -1 either.
So remove the -1.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 4 ++--
1 file
Interlace field order is different between VENC and HDMI. The driver
currently sets the field order for VENC.
This patch adds the code to set the field order for HDMI.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 12
1 file changed, 12 insertions(+)
The HDMI WP timings are not programmed correctly for interlace.
We need to halve the vertical timings when interlace is used, and double
the horizontal timings when pixel doubling is used.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | 18 --
1 file
On OMAP4 and OMAP5 ES1.0 the HDMI_WP_VIDEO_TIMING_H:HSW field is
set directly to the HSW value. On later SoCs the field needs to be
programmed with the value of HSW-1.
Currently the driver always programs the field with the HSW value. Most
videomodes seem to work fine with that, but at least low
We need double-pixel mode (pixel repetition) for interlace modes. This
patch adds the necessary support to HDMI to double the pixel clock when
double-pixel mode is used.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/hdmi4.c | 7 ++-
drivers/gpu/drm/omapdrm/dss/hdmi5.c | 7
We need double-pixel mode (pixel repetition) for interlace modes. This
patch adds the necessary support to omapdrm to output double-pixel mode.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_connector.c | 4
1 file changed, 4 insertions(+)
diff --git
We need double-pixel mode (pixel repetition) for interlace modes. This
patch adds the necessary support to DISPC to output double-pixel mode.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 8
include/video/omapdss.h | 2 ++
2 files changed, 10
omap_crtc_wait_pending() waits until the config changes have been taken
into use, usually at next vblank. The wait-timeout used is 50ms, which
usually is enough, but in some rare cases not.
As time wait-timeout is just a safety measure for cases where something
is broken, we can just as well
We no longer have the omapdrm plugin system for SGX, and we can thus
remove the support for external memory and sync objects from omap_gem.c.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/omapdrm/omap_gem.c | 105 +++--
1 file
From: Laurent Pinchart
OMAP GEM objects backed by dma_buf reuse the current OMAP GEM object
support as much as possible. If the imported buffer is physically
contiguous its physical address will be used directly, reusing the
OMAP_BO_MEM_DMA_API code paths.
From: Laurent Pinchart
Split the individual steps of GEM object allocation and initialization
clearly. This improves readability and prepares for dma_buf import
support.
Signed-off-by: Laurent Pinchart
Signed-off-by: Tomi Valkeinen
---
From: Laurent Pinchart
The driver assumes that only objects backed by shmem need to be mapped
through DMM. While this is true with the current code, the assumption
won't hold with dma_buf import support.
Condition the mapping based on whether the buffer has
If the panel's enable fails, omap_encoder silently ignores the failure.
omapdrm should really handle the failure, but unfortunately the whole
encoder enable codepath is expected to always succeed.
So for now, catch the enable failure and print an error.
Signed-off-by: Tomi Valkeinen
---
omap_gem_dma_sync() calls dma_map_page() but does not check the possible
error with dma_mapping_error(). If DMA-API debugging is enabled, the
debug layer will give a warning if dma_mapping_error() has not been
used.
This patch adds proper error handling to omap_gem_dma_sync().
Signed-off-by:
omap_gem_attach_pages() calls dma_map_page() but does not check the
possible error with dma_mapping_error(). If DMA-API debugging is
enabled, the debug layer will give a warning if dma_mapping_error() has
not been used.
This patch adds proper error handling to omap_gem_attach_pages().
OMAP4+ DSS has WBUNCOMPLETEERROR irq, which was not defined in the irq
list. Add the define.
Signed-off-by: Tomi Valkeinen
Acked-by: Laurent Pinchart
---
include/video/omapdss.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index
From: Manisha Agrawal
tpd12s015 HW has LS_OE, CT_CP_HPD and HPD gpios. Out of these gpios,
driver only handled LS_OE as optional. The CT_CP_HPD gpio should also
be treated as optional gpio as it is just a power saving feature. Some
boards hardwire this gpio to be always
From: Manisha Agrawal
Migrated the gpio APIs to descriptor-interface based.
Signed-off-by: Manisha Agrawal
Acked-by: Tomi Valkeinen
Acked-by: Laurent Pinchart
---
.../gpu/drm/omapdrm/displays/encoder-tpd12s015.c | 79 --
1 file changed, 28
From: Manisha Agrawal
All devices using tpd12s015 driver are doing DT boot. No need of further
supporting the platform data. This patch removes support for platform
data.
Signed-off-by: Manisha Agrawal
[tomi.valkeinen at ti.com: minor adjustments]
Acked-by: Tomi
From: Jyri Sarha
drm_atomic_get_plane_state() may return ERR_PTR. Handle
drm_atomic_get_plane_state() return values right in
omap_crtc_atomic_set_property().
Signed-off-by: Jyri Sarha
Acked-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
This patch adds wrapper functions for readl() and writel(), dmm_read()
and dmm_write(), so that we can implement workaround for DRA7 errata
i878.
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 39
1
The current driver uses non-blocking DMM fill when releasing memory.
This gives us a small performance increase as we don't have to wait for
the fill operation to finish.
However, the driver does not have any error handling for non-blocking
fill. In case of an error, the fill operation may
We occasionally see DISPC sync-lost errors when enabling and disabling
HDMI. Sometimes we get only a few, which get handled (ignored) by the
driver, but sometimes there's a flood of the errors which doesn't seem
to stop.
The HW team has root caused this to the order in which HDMI and DISPC
are
Hi,
Here's a collection of patches for omapdrm. Some of them have been sent for
review at some point, most of them haven't.
There are two bigger features in the series: dmabuf import support and HDMI
interlace output support. Otherwise they are smaller improvements, fixes and
cleanups.
Changes
Hi,
Have you any comment for this proposal?
BR
Vincent
On 02/12/2016 10:26 AM, Vincent Abriou wrote:
> From: Fabien Dessenne
>
> If a buffer is interlaced, this "Bottom Field First" flag specifies
> which of the top or the bottom field shall be displayed first.
> When set, the bottom field
Hi Tomi,
On Friday 26 February 2016 11:12:21 Tomi Valkeinen wrote:
> On 26/02/16 10:55, Laurent Pinchart wrote:
> >> I don't quite understand what you mean. The checks apply to all planes.
> >
> > My point is that if you add a check to ensure that the pitch is identical
> > in all planes, the
On Fri, Feb 26, 2016 at 12:14:44PM +0200, Jyri Sarha wrote:
> On 02/26/16 02:43, Russell King - ARM Linux wrote:
> >On Thu, Feb 25, 2016 at 03:42:50PM +0200, Jyri Sarha wrote:
> >>On 02/18/16 16:35, Rob Herring wrote:
> >>>This should be implied from the port unit address. In other words,
>
are receiving this mail because:
You are the assignee for the bug.
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Hi Tomi,
On Thursday 25 February 2016 17:56:57 Tomi Valkeinen wrote:
> On 24/02/16 01:02, Laurent Pinchart wrote:
> > On Friday 19 February 2016 11:48:05 Tomi Valkeinen wrote:
> >> The DSS hardware uses the same ROW_INC value for both Y and UV planes
> >> for NV12 format. This means that the
Hi Tomi,
On Thursday 25 February 2016 17:45:48 Tomi Valkeinen wrote:
> On 24/02/16 00:14, Laurent Pinchart wrote:
> > On Friday 19 February 2016 11:47:47 Tomi Valkeinen wrote:
> >> omap_gem_dma_sync() calls dma_map_page() but does not check the possible
> >> error with dma_mapping_error(). If
Hi Tomi,
On Thursday 25 February 2016 17:39:35 Tomi Valkeinen wrote:
> On 24/02/16 00:10, Laurent Pinchart wrote:
> > On Friday 19 February 2016 11:47:46 Tomi Valkeinen wrote:
> >> omap_gem_attach_pages() calls dma_map_page() but does not check the
> >> possible error with dma_mapping_error(). If
llvm changes?
No, we can close this as fixed by the game developer. Thanks.
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On 25 February 2016 at 10:21, Xinliang Liu wrote:
> On 24 February 2016 at 02:37, Mark Rutland wrote:
> Hi Mark, thanks for review.
>
>> On Tue, Feb 23, 2016 at 11:00:21AM +0800, Xinliang Liu wrote:
>>> Add ADE display controller binding doc.
>>> Add DesignWare DSI Host Controller v1.20a binding
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Thanks to "drm: prime: Honour O_RDWR during prime-handle-to-fd"
commit we don't need to hack flags anymore.
Signed-off-by: Benjamin Gaignard
---
drivers/gpu/drm/sti/sti_drv.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/sti/sti_drv.c
Hello,
Hyungwon Hwang samsung.com> writes:
> Dear Theirry,
>
> Gentle ping. I modified as you reviewed before. Also I wrote the
> reason for using passing variable by reference for error checking. Can
> you share your opinion for that, and review this driver?
>
> Best regards,
> Hyungwon
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Hi Arnd,
Your patch will be part of the next pull request for the STI driver that
will be done by the end of next week.
Reviewed-by: Vincent Abriou
On 02/25/2016 10:11 PM, Arnd Bergmann wrote:
> The STi drm driver correctly warns about invalid format strings
> when built with 64-bit
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