[PATCH v7 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities

This defines all the DSC parameters as per the VESA DSC spec that will be required for DSC encoder/decoder v6: (From Manasi) * Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi) v5 (From Manasi) * Add the RC constants as per the spec v4 (From Manasi) * Add the DSC_MUX_WORD_SIZE constants

[PATCH v7 06/19] drm/i915/dp: Compute DSC pipe config in atomic check

DSC params like the enable, compressed bpp, slice count and dsc_split are added to the intel_crtc_state. These parameters are set based on the requested mode and available link parameters during the pipe configuration in atomic check phase. These values are then later used to populate the

[PATCH v7 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes

According to Display Stream compression spec 1.2, the picture parameter set metadata is sent from source to sink device using the DP Secondary data packet. An infoframe is formed for the PPS SDP header and PPS SDP payload bytes. This patch adds helpers to fill the PPS SDP header and PPS SDP

[PATCH v7 00/19] DSC enabling remaining patches

This patch series addresses review comments on previous DSC series: https://patchwork.freedesktop.org/series/47514/ Gaurav K Singh (3): drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink Manasi

[PATCH v7 05/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state

Basic DSC parameters and DSC configuration data needs to be computed for each of the requested mode during atomic check. This is required since for certain modes, valid DSC parameters and config data might not be computed in which case compression cannot be enabled for that mode. For that reason

[PATCH v7 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink

From: Gaurav K Singh This patch enables decompression support in sink device before link training and disables the same during the DDI disabling. v3 (From manasi): * Pass bool state to enable/disable (Ville) v2:(From Manasi) * Change the enable/disable function to take crtc_state instead of

[PATCH v7 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC

A separate power well 2 (PG2) is required for VDSC on eDP transcoder whereas all other transcoders use the power wells associated with the transcoders for VDSC. This patch adds a helper to obtain correct power domain depending on transcoder being used and enables/disables the power wells during

[PATCH v7 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling

After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the

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