Now that the driver is ready for it, let's bring in the HDMI controllers
variants for the BCM2711.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 278 +-
drivers/gpu/drm/vc4/vc4_hdmi.h | 36 ++-
drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 480
In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with
pixelvalves each being assigned to a given output, but each output can
then be muxed to feed from multiple FIFOs.
Since vc4 had that entirely static, both were probably equivalent, but
since that changes, let's rename hvs_channel to
The function vc4_hdmi_connector_detect access its vc4_hdmi struct by
dereferencing the pointer in the structure vc4_dev. This will cause some
issues when we will have multiple HDMI controllers, so let's just use the
local variable for now instead of dereferencing that pointer all the time,
and
It doesn't hurt to add the bridge in the global bridge list also for
platform specific dw-hdmi drivers which are based on the component
framework. This can be achieved by moving the drm_bridge_add() function
call from dw_hdmi_probe() to __dw_hdmi_probe(). A counterpart movement
for
The HDMI PHY in the BCM2711 HDMI controller is significantly more
complicated to setup than in the older BCM283x SoCs.
Let's add hooks to enable and disable the PHY.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/Makefile | 1 +
drivers/gpu/drm/vc4/vc4_hdmi.c | 14
The HDMI controllers found in the BCM2711 has a pretty different clock and
registers areas than found in the older BCM283x SoCs.
Let's create a variant structure to store the various adjustments we'll
need later on, and a function to get the resources needed for one
particular version.
We will need to share the vc4_hdmi and related structures with multiple
files, so let's create a header for it.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 76 +---
drivers/gpu/drm/vc4/vc4_hdmi.h | 86
From: Dave Stevenson
If the encoder is disabled and re-enabled (eg mode change) all infoframes
are reset, whilst the audio subsystem know nothing about this change.
The driver therefore needs to reinstate the audio infoframe for
itself.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime
From: Dave Stevenson
The audio configuration has changed for the BCM2711, with notably a
different parent clock and a different channel configuration.
Make that modular to be able to support the BCM2711.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
Hi Philipp,
thanks for the quick reply.
On Wed, 8 Jul 2020 at 10:31, Philipp Zabel wrote:
> Could this be just a panel getting confused because the pixel clock is
> disabled, or is there really an issue with the IPU? Have you tried just
> keeping clk_di_pixel enabled in ipu_di_disable(), but
Hi Boris,
Thank you to spend some time to review the patches.
On 1/7/20 13:41, Boris Brezillon wrote:
> On Mon, 18 May 2020 19:39:09 +0200
> Enric Balletbo i Serra wrote:
>
>> The mtk_dpi driver uses an empty implementation for its encoder. Replace
>> the code with the generic simple encoder.
Similarly to the audio support, CEC support is not there yet for the
BCM2711, so let's skip entirely the CEC initialization through a variant
flag.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 files changed, 7 insertions(+)
The driver isn't consistent with the name given to the vc4_hdmi
structure pointer in its functions. Make sure to use a consistent name.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 283 +-
1 file changed, 142
From: Dave Stevenson
The register range used for audio setup in the previous generations of
SoC were always the second range in the device tree. However, now that
the BCM2711 has way more register ranges, it makes sense to retrieve it
by names for it, while preserving the id-based lookup as a
During the transition from the firmware to the KMS driver, we need to pay
particular attention to how we deal with the pixelvalves that have already
been enabled, otherwise either timeouts or stuck pixels can occur. We'll
thus need to call the function to stop an HVS channel at boot.
Reviewed-by:
The HDMI driver was registering a single debugfs file so far with the name
hdmi_regs.
Obviously, this is not going to work anymore when will have multiple HDMI
controllers since we will end up trying to register two files with the same
name.
Let's use the variant to avoid that name conflict.
In order to make further refactoring easier, let's move the HVS channel
setup / teardown to their own function.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hvs.c | 104 +++
1 file changed, 58 insertions(+), 46 deletions(-)
diff --git
In order to avoid a stale pixel getting stuck on mode change or a disable
/ enable cycle, we need to make sure to flush the PV FIFO on disable.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
Let's continue the implementation of hooks for the parts that change in the
BCM2711 SoC with the PHY RNG setup.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 15 +--
drivers/gpu/drm/vc4/vc4_hdmi.h | 8
drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 15
The BCM2711 comes with other pixelvalves that have different requirements
and capabilities. Let's document their compatible.
Reviewed-by: Rob Herring
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 5
+
1
From: Dave Stevenson
ALSA's iec958 plugin by default sets the block start preamble
to 8, whilst this driver was programming the hardware to expect
0xF.
Amend the hardware config to match ALSA.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 3
In the BCM2711, the setup of the HVS, pixelvalve and HDMI controller
requires very precise ordering and timing that the regular atomic callbacks
don't provide. Let's add new callbacks on top of the regular ones to be
able to split the configuration as needed.
Signed-off-by: Maxime Ripard
---
The HDMI controllers found in the BCM2711 have most of the registers
reorganized in multiple registers areas and at different offsets than
previously found.
The logic however remains pretty much the same, so it doesn't really make
sense to create a whole new driver and we should share the code as
Now that we don't have any users anymore, we can kill that pointer.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 -
drivers/gpu/drm/vc4/vc4_hdmi.c | 7 ---
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h
It's unnecessary to cleanup the i2c adapter and the ddc pointer in
the bailout path of __dw_hdmi_probe(), since the adapter is not
added and the ddc pointer is not set.
Fixes: a23d6265f033 (drm: bridge: dw-hdmi: Extract PHY interrupt setup to a
function)
Cc: Andrzej Hajda
Cc: Neil Armstrong
The HSM clock needs to be setup at around 101% of the pixel rate. This
was done previously by setting the clock rate to 163.7MHz at probe time and
only check in mode_valid whether the mode pixel clock was under the pixel
clock +1% or not.
However, with 4k we need to change that frequency to a
From: Dave Stevenson
The current code is using the maximum of the source line size and the
destination line size to compute the size of the LBM to allocate.
While this is simpler, it starts to be an issue with modes such as 4k with
a quite long that will consume all the available memory, so we
The CEC_CLOCK_DIV define is not used anywhere in the driver, let's remove
it.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 86e21de6c578..a01562a49bf0
Now that we are passing the vc4_hdmi structure to the connector init
function, we can simply use the pointer in that structure instead of
having the pointer as an argument.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 7 +++
1 file changed, 3
The BCM2711 and BCM283x HDMI controllers use a slightly different reset
sequence, so let's add a callback to reset the controller.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 31 ++-
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 files changed, 21
In order to prevent some pixels getting stuck in an unflushable FIFO on
bcm2711, we need to enable the HVS, the pixelvalve (the CRTC) and the HDMI
controller (the encoder) in an intertwined way, and with tight delays.
However, the atomic callbacks don't really provide a way to work with
either
Let's now create more planes that can be affected to all the CRTCs.
vc4 has 3 CRTCs, 1 primary and 1 cursor each, and was having 24 (8
planes per CRTC) overlays.
However, vc5 has 5 CRTCs, so keeping the same logic would put us at 50
planes which is well above the 32 planes limit imposed by DRM.
The HSM clock needs to be running at 101% the pixel clock of the HDMI
controller, however it's shared between the two HDMI controllers, which
means that if the resolutions are different between the two HDMI
controllers, and the lowest resolution is on the second (in enable order)
controller, the
Hi everyone,
Here's a (pretty long) series to introduce support in the VC4 DRM driver
for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4).
The main differences are that there's two HDMI controllers and that there's
more pixelvalve now. Those pixelvalve come with a mux in
The HVS found in the BCM2711 has 6 outputs and 3 FIFOs, with each output
being connected to a pixelvalve, and some muxing between the FIFOs and
outputs.
Any output cannot feed from any FIFO though, and they all have a bunch of
constraints.
In order to support this, let's store the possible FIFOs
Whenever the code needs to access the vc4_hdmi structure from a DRM
connector or encoder, it first accesses the drm_device associated to the
connector, then retrieve the drm_dev private data which gives it a
pointer to our vc4_dev, and will finally follow the vc4_hdmi pointer in
that structure.
The vc4_crtc_handle_page_flip already has a local variable holding the
value of vc4_crtc->channel, so let's use it instead.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c
Now that all the drivers have been adjusted for it, let's bring in the
necessary device tree changes.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 46 +++-
arch/arm/boot/dts/bcm2711.dtsi| 115 ++-
2 files changed, 160
On 2020-07-07 20:04, Randy Dunlap wrote:
Drop the doubled word "the".
Signed-off-by: Randy Dunlap
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Cc: Tony Krowiak
Cc: Pierre Morel
Cc: Halil Pasic
Cc: linux-s...@vger.kernel.org
---
Documentation/s390/vfio-ap.rst |2 +-
1 file
the vc4_hdmi driver has some custom structures to hold the data it needs to
associate with the drm_encoder and drm_connector structures.
However, it allocates them separately from the vc4_hdmi structure which
makes it more complicated than it needs to be.
Move those structures to be contained by
The CEC init code was put directly into the bind function, which was quite
inconsistent with how the audio support was done, and would prevent us from
further changes to skip that initialisation entirely.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 108
In order to avoid a pixel getting stuck in an unflushable FIFO, we need to
recenter the FIFO every time we're doing a modeset and not only if we're
connected to an HDMI monitor.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 46 +++
1 file
The HDMI driver was registering a single ALSA card so far with the name
vc4-hdmi.
Obviously, this is not going to work anymore when will have multiple HDMI
controllers since we will end up trying to register two files with the same
name.
Let's use the variant to avoid that name conflict.
Our CEC code also retrieves the associated vc4_hdmi by setting the
vc4_dev pointer as its private data, and then dereferences its vc4_hdmi
pointer.
In order to eventually get rid of that pointer, we can simply pass the
vc4_hdmi pointer directly.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime
The HDMI controllers found in the BCM2711 SoC need some adjustments to the
bindings, especially since the registers have been shuffled around in more
register ranges.
Reviewed-by: Rob Herring
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml |
In order to avoid pixels getting stuck in an unflushable FIFO, we need when
we disable the HDMI controller to switch away from getting our pixels from
the pixelvalve and instead use blank pixels, and switch back to the
pixelvalve when we enable the HDMI controller.
Signed-off-by: Maxime Ripard
Now that we only configure the PixelValve in vc4_crtc_config_pv, it doesn't
really make much sense to dump its register content in its caller.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
diff
Similarly to the previous patches, the CSC setup is slightly different in
the BCM2711 than in the previous generations. Let's add a callback for it.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 142 +++---
drivers/gpu/drm/vc4/vc4_hdmi.h | 7 ++-
We'll need to reuse the part that disables the HVS and PixelValve during
boot too, so let's create a separate function.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 34 ++
1 file changed, 22 insertions(+), 12
The BCM2711 has a reworked display pipeline, and the load tracker needs
some adjustement to operate properly. Let's add a compatible for BCM2711
and disable the load tracker until properly supported.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.c | 1 +-
The current driver only supports a single HDMI controller, and part of
the issue is that the main vc4_dev structure holds a pointer to its
(only) HDMI controller, and the HDMI registers accessors will use it to
retrieve the mapped addresses.
Let's modify those accessors to use directly the
The BCM2711 sports a second HDMI controller, so let's add that second HDMI
encoder type.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
We're calling vc4_debugfs_add_file with our struct vc4_hdmi pointer set
in the private field, but we don't use that field and go through the
main struct vc4_dev to get it.
Let's use the private field directly, that will save us some trouble
later on.
Reviewed-by: Eric Anholt
Signed-off-by:
Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that
to our vc4_crtc_data structure to be able to compute the fill level
properly later on.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 20 +---
The vc4 atomic commit loop has an handrolled loop that is basically
identical to for_each_new_crtc_state, let's convert it to that helper.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_kms.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git
The BCM2711 comes with a new VideoCore. Add a compatible for it.
Reviewed-by: Rob Herring
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
In order to avoid stale pixels getting stuck in an intermediate FIFO
between the HVS and the pixelvalve on BCM2711, we need to configure the HVS
channel before the pixelvalve is reset and configured.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 8
1 file changed, 4
The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add
support for them.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 95 ++-
drivers/gpu/drm/vc4/vc4_regs.h | 7 +++-
2 files changed, 100
The mode_valid hook on the encoder uses a pointer to a drm_encoder called
crtc, which is pretty confusing. Let's rename it to encoder to make it
clear what it is.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The HVS5 uses different color matrices. Disable color management support
for now.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 17 +++--
drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
2 files changed, 12 insertions(+), 7 deletions(-)
diff
In order to clear our intermediate FIFOs that might end up with a stale
pixel, let's make sure our FIFO channel is reset everytime our channel is
setup.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hvs.c | 4
1 file changed, 4 insertions(+)
diff --git
The unbind function needs to retrieve a vc4_hdmi structure pointer through
the struct device that we're given since we want to support multiple HDMI
controllers.
However, our optional ASoC support doesn't make that trivial since it will
overwrite the device drvdata if we use it, but obviously
The current code has some logic, disabled by default, to dump the register
setup in the HDMI controller.
However, since we're going to split those functions in multiple, shorter,
functions that only make sense where they are called in sequence, keeping
the register dump makes little sense.
The previous generations were only supporting a single HDMI controller, but
that's about to change, so put an index as well to differentiate between
the two controllers.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
Some of the HDMI pixelvalves in vc5 output two pixels per clock cycle.
Let's put the number of pixel output per clock cycle in the CRTC data and
update the various calculations to reflect that.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 18
From: Dave Stevenson
The HVS5 needs an alignment of 64bytes for its LBM memory, so let's reflect
it.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
The longer FIFOs in vc5 pixelvalves means that the FIFO full level
doesn't fit in the original register field and that we also have a
secondary field. In order to prepare for this, let's move the registers
fill part to a helper function.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
Hi,
Is this patch good to go?
@dan...@ffwll.ch, @Philippe CORNU
Was already tested by @Yannick FERTRE
and @Adrian Pop
on https://lkml.org/lkml/2020/4/6/691 .
Thanks,
Angelo
From: Yannick
FERTRE
Date: Wed, Jun 24, 2020 at 16:35:04
> Hello Angelo,
> thanks for the patch.
> Tested-by:
On BCM2711 to avoid stale pixels getting stuck in intermediate FIFOs, the
pixelvalve needs to be setup each time there's a mode change or enable /
disable sequence.
Therefore, we can't really use mode_set_nofb anymore to configure it, but
we need to move it to atomic_enable.
Signed-off-by:
Hi Sandy,
Le mer. 8 juil. 2020 à 10:26, Sandy Huang a
écrit :
Hi paul,
After add this driver, the followinig usage scenarios can be
supported?
panel 1. crtc->encoder->connector[edp/hdmi/mipi dsi] -> panel
panel 2. Panel setup/control and framebuffer upload over SPI
the
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
Some pixelvalves in vc5 use the same interrupt line so let's register our
interrupt handler as a shared one.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
The COB allocation depends on the HVS channel used for a given
pixelvalve.
While the channel allocation was entirely static in vc4, vc5 changes
that and at bind time, a pixelvalve can be assigned to multiple
HVS channels.
Let's prepare that rework by allocating the COB when it's actually
needed.
The HVS found in the BCM2711 is slightly different from the previous
generations, let's add a compatible for it.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 18 ++-
1 file changed, 17 insertions(+), 1
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
From: Dave Stevenson
The HVS found in the BCM2711 is slightly different from the previous
generations.
Most notably, the display list layout changes a bit, the LBM doesn't have
the same size and the formats ordering for some formats is swapped.
Signed-off-by: Dave Stevenson
Reviewed-by: Eric
Hi Zenghui,
Thanks for fixing this.
Applied to drm-misc-fixes.
Best,
-Xinliang
On Mon, 6 Jul 2020 at 22:53, Zenghui Yu wrote:
>
> The HiSilicon hibmc driver triggers a splat at boot time as below
>
> [ 14.137806] [ cut here ]
> [ 14.142405] hibmc-drm :0a:00.0:
In order to prevent timeouts and stalls in the pipeline, the core clock
needs to be maxed at 500MHz during a modeset on the BCM2711.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 2 ++
drivers/gpu/drm/vc4/vc4_hvs.c | 9 +
RENOIR loads dmub fw not dmcu, check dmcu only will prevent loading iram,
it breaks backlight control.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=208277
Signed-off-by: Aaron Ma
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On Tue, Jul 07, 2020 at 03:01:25PM +0800, Nicolas Boichat wrote:
Hi Nicolas, thanks for the replay.
> On Tue, Jun 9, 2020 at 3:20 PM Xin Ji wrote:
> >
> > The ANX7625 is an ultra-low power 4K Mobile HD Transmitter designed
> > for portable device. It converts MIPI DSI/DPI to DisplayPort 1.3 4K.
Hi Daniel,
Le mer. 8 juil. 2020 à 9:23, Daniel Vetter a écrit :
On Tue, Jul 07, 2020 at 04:32:25PM +0200, Noralf Trønnes wrote:
(cc Dillon)
Den 03.07.2020 19.26, skrev Sam Ravnborg:
> Hi Noralf/Paul.
>
> Trying to stir up this discussion again.
>
> On Sun, Jun 14, 2020 at 06:36:22PM
The VID_CTL setup is done in several places in the driver even though it's
not really required. Let's simplify it a bit to do the configuration in one
go.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff
The vc4_hdmi_connector was only used to switch between drm_connector to
drm_encoder. However, we can now use vc4_hdmi to do the switch, so that
structure is redundant.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 19 ---
Hi Boris,
Thank you for review the patch.
On 1/7/20 13:51, Boris Brezillon wrote:
> On Mon, 18 May 2020 19:39:08 +0200
> Enric Balletbo i Serra wrote:
>
>> Convert mtk_dpi to a bridge driver with built-in encoder support for
>> compatibility with existing component drivers.
>>
>>
Even though it's not really clear why we need to flush the PV FIFO during
the configuration even though we started by flushing it, experience shows
that without it we get a stale pixel stuck in the FIFO between the HVS and
the PV.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c
The VIDEN bit in the pixelvalve currently being used to enable or disable
the pixelvalve seems to not be enough in some situations, which whill end
up with the pixelvalve stalling.
In such a case, even re-enabling VIDEN doesn't bring it back and we need to
clear the FIFO. This can only be done if
Since most of the HVS channel is setup in the init function, let's move the
gamma setup there too. As this makes the HVS mode_set function empty, let's
remove it in the process.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
drivers/gpu/drm/vc4/vc4_drv.h | 1 +-
In order to avoid pixels getting stuck in the (unflushable) FIFO between
the HVS and the PV, we need to add some delay after disabling the PV output
and before disabling the HDMI controller. 20ms seems to be good enough so
let's use that.
Signed-off-by: Maxime Ripard
---
Since we moved the pixelvalve configuration to atomic_enable, we're now
first calling the function that resets the pixelvalve and then the one that
configures it.
However, the first thing the latter is doing is calling the reset function,
meaning that we reset twice our pixelvalve. Let's remove
The driver resets the pixelvalve FIFO in a number of occurences without
always using the same sequence.
Since this will be critical for BCM2711, let's move that sequence to a
function so that we are consistent.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
At boot time, if we detect that a pixelvalve has been enabled, we need to
be able to retrieve the HVS channel it has been assigned to so that we can
disable that channel too. Let's create that function that returns the FIFO
or an error from a given output.
Reviewed-by: Eric Anholt
Signed-off-by:
In order to prevent issues during the firmware to KMS transition, we need
to make sure the pixelvalve are disabled at boot time so that the DRM state
matches the hardware state.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 25
On Wed, 1 Jul 2020 at 09:10, Sam Ravnborg wrote:
>
> Hi Guenter.
>
> On Tue, Jun 30, 2020 at 05:10:02PM -0700, Guenter Roeck wrote:
> > The following backtrace is seen when running aspeed G5 kernels.
> >
> > WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/drm_fb_helper.c:2233
> >
> Subject: [PATCH 05/20] Documentation: fpga: eliminate duplicated word
>
> Drop the doubled word "this".
>
> Signed-off-by: Randy Dunlap
> Cc: Jonathan Corbet
> Cc: linux-...@vger.kernel.org
> Cc: Wu Hao
> Cc: linux-f...@vger.kernel.org
Acked-by: Wu Hao
Thanks Randy.
Hao
On Wed, Jul 08, 2020 at 06:37:51PM -0500, Adam Ford wrote:
> On Mon, Jul 6, 2020 at 6:18 AM Adam Ford wrote:
> >
> > On Mon, Jul 6, 2020 at 1:02 AM Tomi Valkeinen wrote:
> > >
> > > Hi,
> > >
> > > On 03/07/2020 22:36, Sam Ravnborg wrote:
> > > > Hi Tomi.
> > > >
> > > > On Fri, Jul 03, 2020 at
On 2020-06-23 at 11:58:59 -0400, Sean Paul wrote:
> From: Sean Paul
>
> This patch is required for HDCP over MST. If a port is being used for
> multiple HDCP streams, we don't want to fully disable HDCP on a port if
> one of them is disabled. Instead, we just disable the HDCP signalling on
>
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