The LDB clock needs to be exactly 7-times the pixel clock used by the
display.
Signed-off-by: Alexander Stein
---
i.MX8MP has a dedicated LDB clock which defines the actual LVDS link frequency.
This has to be (exactly) the 7-time of the pixel clock.
Although the clock min/max range is available,
Hello Marek,
Am Mittwoch, 7. Dezember 2022, 16:59:50 CET schrieb Marek Vasut:
> On 12/7/22 16:13, Alexander Stein wrote:
> > i.MX8MP uses 3 clocks, so soften the restrictions for clocks &
> > clock-names.
> >
> > Fixes: f5419cb0743f ("dt-bindings: lcdif: Add compatible for i.MX8MP")
> >
Am Mittwoch, 7. Dezember 2022, 17:00:22 CET schrieb Marek Vasut:
> On 12/7/22 16:14, Alexander Stein wrote:
> > i.MX8MP requires a power-domain for this peripheral to use. Add it as
> > an optional property.
> >
> > Signed-off-by: Alexander Stein
> > ---
> >
> >
On Mon, 2022-12-05 at 17:19 -0800, Ceraolo Spurio, Daniele wrote:
> The current exectation from the FW side is that the driver will query
> the GSC FW version after the FW is loaded, similarly to what the mei
> driver does on DG2. However, we're discussing with the FW team if there
> is a way to
Starting with MTL, there will be two GT-tiles, a render and media
tile. PXP as a service for supporting workloads with protected
contexts and protected buffers can be subscribed by process
workloads on any tile. However, depending on the platform,
only one of the tiles is used for control events
On Wed, Nov 30, 2022 at 6:11 AM Daniel Vetter wrote:
>
> On Fri, Nov 25, 2022 at 02:52:01PM -0300, André Almeida wrote:
> > This patchset adds a udev event for DRM device's resets.
> >
> > Userspace apps can trigger GPU resets by misuse of graphical APIs or driver
> > bugs. Either way, the GPU
On Mon, 2022-12-05 at 17:19 -0800, Ceraolo Spurio, Daniele wrote:
> On MTL the GSC FW needs to be loaded on the media GT by the graphics
> driver. We're going to treat it like a new uc_fw, so add the initial
> defs and init/fini functions for it.
>
> Similarly to the other FWs, the GSC FW path
As kzalloc may fail and return NULL pointer, the "mw_state" can be NULL.
If the layout of struct malidp_mw_connector_state ever changes, it
will cause NULL poineter derefernce of "_state->base".
Therefore, the "mw_state" should be checked whether it is NULL in order
to improve the robust.
Fixes:
As kzalloc may fail and return NULL pointer, the "mw_state" can be NULL.
If the layout of struct malidp_mw_connector_state ever changes, it
will cause NULL poineter derefernce of "_state->base".
Therefore, the "mw_state" should be check whether it is NULL in order
to improve the robust.
Fixes:
On Wed, Dec 07, 2022 at 09:59:04PM +0800, Robin Murphy wrote:
>> As kzalloc may fail and return NULL pointer, it should be better to check
>> the return value in order to avoid the NULL pointer dereference in
>> __drm_atomic_helper_connector_reset.
>
> This commit message is nonsense; if
>
As kzalloc may fail and return NULL pointer, the "mw_state" can be NULL.
If the the layout of struct malidp_mw_connector_state ever changes, it
will cause NULL poineter derefernce of "_state->base".
Therefore, the "mw_state" should be check whether it is NULL in order
to improve the robust.
Add SoC-specific compat string to the MDP5 device nodes to ease
distinguishing between various platforms.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
Add platform-specific compatible entries to the qcom,mdp5.yaml to allow
distinguishing between various platforms.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/qcom,mdp5.yaml | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git
Add SoC-specific compat string to the MDP5 device node to ease
distinguishing between various platforms.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
Convert the mdp5.txt into the yaml format. Changes to the existing (txt) schema:
- MSM8996 has additional "iommu" clock, define it separately
- Add new properties used on some of platforms:
- interconnects, interconnect-names
- iommus
- power-domains
- operating-points-v2, opp-table
This patch concludes the conversion of display/msm schema from txt files
to YAML format.
The per-SoC compat (new addition) is required to ease migrating platform
support between mdp5 and dpu drivers.
Changes since v1:
- Renamed mdp@ to display-controller@ in the example (Krzysztof)
- Extended
Add platform data for sc8180xp based on sdmshrike-sde.dtsi.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
According to the vendor DT, sm6115 has UBWC 1.0, not 2.0.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 2219c1bd59a9..4401f945b966
To simplify adding new platforms and to make settings more obvious,
rewrite the UBWC setup to use the data structure to pass platform config
rather than just calling the functions direcly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 158 -
Add the platform data for sdm845 platform.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 5e19ec897670..b2c6e8b12469 100644
---
The commit 92bab9142456 ("drm/msm: less magic numbers in
msm_mdss_enable") reworked the static UBWC setup to replace magic
numbers with calulating written values from the SoC/device parameters.
This simplified adding new platforms.
However I did not estimate that the values would still be cryptic
On 05/12/2022 18:37, Robert Foss wrote:
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/msm_mdss.c | 4
1 file changed, 4 insertions(+)
diff --git
On 12/5/2022 8:37 AM, Robert Foss wrote:
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
1 file changed, 1
On 12/5/2022 8:37 AM, Robert Foss wrote:
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|
On 05/12/2022 18:37, Robert Foss wrote:
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Dmitry Baryshkov
On 05/12/2022 18:37, Robert Foss wrote:
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss
Reviewed-by: Dmitry Baryshkov
Minor nit below.
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
On 08/12/2022 00:00, Bjorn Andersson wrote:
From: Bjorn Andersson
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
necessary definitions and describe the DPU in the SC8280XP.
Signed-off-by: Bjorn Andersson
Hi Dave, Daniel,
Fixes for 6.2.
The following changes since commit 4670ac706ff9b3d0adb766ef9e93cc36d9dda474:
drm/amdgpu: expand on GPUVM documentation (2022-12-02 10:06:00 -0500)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
On Wed, 07 Dec 2022 08:57:55 -0800, Kuogee Hsieh wrote:
> Add both data-lanes and link-frequencies property into endpoint
>
> Changes in v7:
> -- split yaml out of dtsi patch
> -- link-frequencies from link rate to symbol rate
> -- deprecation of old data-lanes property
>
> Changes in v8:
> --
Hi Dave, Daniel,
A couple of small fixes for 6.1.
The following changes since commit 76dcd734eca23168cb008912c0f69ff408905235:
Linux 6.1-rc8 (2022-12-04 14:48:12 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
From: Bjorn Andersson
The DisplayPort controller's internal HPD interrupt handling is used for
cases where the HPD signal is connected to a GPIO which is pinmuxed into
the DisplayPort controller. In other configurations the HPD notification
might be delivered by the DRM framework from an
From: Bjorn Andersson
The SA8295P ADP has, among other interfaces, six MiniDP connectors which
are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3.
Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers,
DP PHYs and link them all together.
Signed-off-by: Bjorn
From: Bjorn Andersson
The DisplayPort controller's hot-plug mechanism is based on pinmuxing a
physical signal on a GPIO pin into the controller. This is not always
possible, either because there aren't dedicated GPIOs available or
because the hot-plug signal is a virtual notification, in cases
From: Bjorn Andersson
The Qualcomm SDM845 platform has a single DisplayPort controller, with
the same design as SC7180, so add support for this by reusing the SC7180
definition.
Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Bjorn Andersson
---
Changes since v4:
From: Bjorn Andersson
Add compatibles for the DisplayPort and Embedded DisplayPort blocks in
Qualcomm SDM845 and SC8280XP platforms.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
Acked-by: Krzysztof Kozlowski
---
Changes since v4:
- None
From: Bjorn Andersson
In the SC8280XP platform there are two identical MDSS instances, each
with the same set of DisplayPort instances, at different addresses.
By not relying on the index to define the instance id it's possible to
describe them both in the same table and hence have a single
From: Bjorn Andersson
The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
and link it together with the backlight control.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v4:
- None
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72
From: Bjorn Andersson
The SC8280XP platform has four DisplayPort controllers, per MDSS
instance, all with widebus support.
The first two are defined to be DisplayPort only, while the latter pair
(of each instance) can be either DisplayPort or Embedded DisplayPort.
The two sets are tied to the
From: Bjorn Andersson
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
necessary definitions and describe the DPU in the SC8280XP.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes
From: Bjorn Andersson
Add compatible for the SC8280XP Mobile Display Subsystem and
initialization for version 8.0.0.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
---
Changes since v4:
- None
drivers/gpu/drm/msm/msm_mdss.c | 4
1 file
From: Bjorn Andersson
Add binding for the display subsystem and display processing unit in the
Qualcomm SC8280XP platform.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
Reviewed-by: Rob Herring
---
Changes since v4:
- None
.../display/msm/qcom,sc8280xp-dpu.yaml|
From: Bjorn Andersson
Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v4:
- None
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
1 file
This introduces support for the SC8280XP platform in the MDSS, DPU and
DP driver. It reworks the HDP handling in the DP driver to support
external HPD sources - such as the dp-connector, or USB Type-C altmode.
It then introduces the display clock controllers, mdss, dpu and
displayport controllers
LGTM.
Reviewed-by: Maaz Mombasawala
On 12/7/22 09:29, Zack Rusin wrote:
> From: Zack Rusin
>
> User resource lookups used rcu to avoid two extra atomics. Unfortunately
> the rcu paths were buggy and it was easy to make the driver crash by
> submitting command buffers from two different
On 07/12/2022 18:57, Kuogee Hsieh wrote:
Add capability to parser and retrieve max DP link supported rate from
link-frequencies property of dp_out endpoint.
Changes in v6:
-- second patch after split parser patch into two patches
Changes in v7:
-- without checking cnt against
On 07/12/2022 18:57, Kuogee Hsieh wrote:
Add both data-lanes and link-frequencies property into endpoint
Changes in v7:
-- split yaml out of dtsi patch
-- link-frequencies from link rate to symbol rate
-- deprecation of old data-lanes property
Changes in v8:
-- correct Bjorn mail address to
On 07/12/2022 18:28, Bjorn Andersson wrote:
On Wed, Dec 07, 2022 at 04:49:07PM +0200, Dmitry Baryshkov wrote:
On 05/12/2022 19:44, Bjorn Andersson wrote:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
[..]
+static const struct
gud_pipe.c b/drivers/gpu/drm/gud/gud_pipe.c
index 62c43d3632d4..dc16a92625d4 100644
--- a/drivers/gpu/drm/gud/gud_pipe.c
+++ b/drivers/gpu/drm/gud/gud_pipe.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
---
base-commit: 5ad8e63ebba3d5a0730b43180b200e41eeb9409c
change-id
On 2022-12-07 15:29, Liviu Dudau wrote:
On Wed, Dec 07, 2022 at 01:59:04PM +, Robin Murphy wrote:
On 2022-12-07 09:21, Jiasheng Jiang wrote:
As kzalloc may fail and return NULL pointer, it should be better to check
the return value in order to avoid the NULL pointer dereference in
From: Martin Krastev
Looks good!
Reviewed-by: Martin Krastev
Regards,
Martin
On 7.12.22 г. 19:29 ч., Zack Rusin wrote:
From: Zack Rusin
User resource lookups used rcu to avoid two extra atomics. Unfortunately
the rcu paths were buggy and it was easy to make the driver crash by
On Wed, 07 Dec 2022 16:14:00 +0100, Alexander Stein wrote:
> i.MX8MP requires a power-domain for this peripheral to use. Add it as
> an optional property.
>
> Signed-off-by: Alexander Stein
> ---
> Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 3 +++
> 1 file changed, 3
On Wed, 07 Dec 2022 16:13:59 +0100, Alexander Stein wrote:
> i.MX8MP uses 3 clocks, so soften the restrictions for clocks & clock-names.
>
> Fixes: f5419cb0743f ("dt-bindings: lcdif: Add compatible for i.MX8MP")
> Signed-off-by: Alexander Stein
> ---
>
From: Zack Rusin
User resource lookups used rcu to avoid two extra atomics. Unfortunately
the rcu paths were buggy and it was easy to make the driver crash by
submitting command buffers from two different threads. Because the
lookups never show up in performance profiles replace them with a
Hi,
On 11/30/22 18:08, Allen Ballway wrote:
> Like the ASUS T100HAN for which there is already a quirk,
> the DynaBook K50 has a 800x1280 portrait screen mounted
> in the tablet part of a landscape oriented 2-in-1.
> Update the quirk to be more generic and apply to this device.
>
>
Hi,
On 11/30/22 08:43, Javier Martinez Canillas wrote:
> Hello Hans,
>
> On 11/27/22 19:15, Hans de Goede wrote:
>> The Lenovo Yoga Tab 3 X90F has a portrait 1600x2560 LCD used in
>> landscape mode, add a quirk for this.
>>
>> Signed-off-by: Hans de Goede
>> ---
>
> Looks good to me.
>
>
Add capability to parser data-lanes as property of dp_out endpoint.
Also retain the original capability to parser data-lanes as property
of mdss_dp node to handle legacy case.
Changes in v6:
-- first patch after split parser patch into two
Changes in v7:
-- check "data-lanes" from endpoint first
Add both data-lanes and link-frequencies property into endpoint
Changes in v7:
-- split yaml out of dtsi patch
-- link-frequencies from link rate to symbol rate
-- deprecation of old data-lanes property
Changes in v8:
-- correct Bjorn mail address to kernel.org
Changes in v10:
-- add menu item
By default, HBR2 (5.4G) is the max link link be supported. This patch uses the
actual limit specified by DT and removes the artificial limitation to 5.4 Gbps.
Supporting HBR3 is a consequence of that.
Changes in v2:
-- add max link rate from dtsi
Changes in v3:
-- parser max_data_lanes and
Add capability to parser and retrieve max DP link supported rate from
link-frequencies property of dp_out endpoint.
Changes in v6:
-- second patch after split parser patch into two patches
Changes in v7:
-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate
Changes in v9:
--
Move data-lanes property from mdss_dp node to dp_out endpoint. Also
add link-frequencies property into dp_out endpoint as well. The last
frequency specified at link-frequencies will be the max link rate
supported by DP.
Changes in v5:
-- revert changes at sc7180.dtsi and sc7280.dtsi
-- add _out
Add DP both data-lanes and link-frequencies property to dp_out endpoint and
support
functions to DP driver.
Kuogee Hsieh (5):
arm64: dts: qcom: add data-lanes and link-freuencies into dp_out
endpoint
dt-bindings: msm/dp: add data-lanes and link-frequencies property
drm/msm/dp: parser
On Wed, Dec 07, 2022 at 05:00:51PM +0100, Ulf Hansson wrote:
> On Thu, 1 Dec 2022 at 23:57, Bjorn Andersson wrote:
> >
> > On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote:
> > >
> >
> > @Ulf, Akhil has a power-domain for a piece of hardware which may be
> > voted active by multiple
On 12/7/2022 2:16 AM, Teres Alexis, Alan Previn wrote:
Diffed the patches and reviewed the changes -- i.e. the use of the worker for
the gsc fw loading cmd submission.
All looks good - just a few nits below.
Reviewed-by: Alan Previn
On Mon, 2022-12-05 at 21:15 -0800, Ceraolo Spurio,
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 591cd61541b9b95401e17dca24be486e32104cb8 Add linux-next specific
files for 20221207
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202211090634.ryfkk0ws-...@intel.com
https
On Wed, Dec 07, 2022 at 04:49:07PM +0200, Dmitry Baryshkov wrote:
> On 05/12/2022 19:44, Bjorn Andersson wrote:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
[..]
> > +static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
> > +
Hi Maíra,
Thanks for your review!
On Wed, Dec 07, 2022 at 11:26:13AM -0300, Maíra Canal wrote:
> On 12/1/22 12:11, Maxime Ripard wrote:
> > Accessing a register when running under kunit is a bad idea since our
> > device is completely mocked.
> >
> > Fail the current test if we ever access any
From: Dave Stevenson
Even though we report that we support the BT601 Colorspace, we were
always using the BT.709 conversion matrices. Let's add the BT601 ones.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 38
From: Dave Stevenson
Even though we report that we support the BT.2020 Colorspace, we were
always using the BT.709 conversion matrices. Let's add the BT.2020 ones.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 38
From: Dave Stevenson
The CSC matrix to use depends on the output format, its range and the
colorspace.
Since we're going to add more colorspaces, let's move the CSC matrix
retrieval to a function.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c
From: Dave Stevenson
The VC4 HDMI driver has a helper function to figure out whether full
range or limited range RGB is being used called
vc4_hdmi_is_full_range_rgb().
We'll need it to support other colorspaces, so let's rename it to
vc4_hdmi_is_full_range().
Signed-off-by: Dave Stevenson
From: Dave Stevenson
Copy Intel's "Broadcast RGB" property semantics to add manual override
of the HDMI pixel range for monitors that don't abide by the content
of the AVI Infoframe.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 87
From: Dave Stevenson
The CSC matrices were stored as separate matrix for each colorspace, and
if we wanted a limited or full RGB output.
This created some gaps in our support and we would not always pick the
relevant matrix.
Let's rework our data structure to store one per colorspace, and then
From: Dave Stevenson
YUV444 requires the matrix coefficients to be programmed in a different
way than the other formats. Let's add a function to program it properly.
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 17 -
1 file
None of our wrappers around container_of to access our objects from the
DRM object pointer actually modify the latter.
Let's make them const.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
: Constify container_of wrappers
drivers/gpu/drm/vc4/vc4_hdmi.c | 326 ++---
drivers/gpu/drm/vc4/vc4_hdmi.h | 21 ++-
2 files changed, 289 insertions(+), 58 deletions(-)
---
base-commit: 99e2d98adc738597abcc5d38b03d0e9858db5c00
change-id: 20221207-rpi-hdmi
On VC4, the TV margins on the HDMI connector are implemented by scaling
the planes.
However, if only the TV margins or the connector are changed by a new
state, the planes ending up on that connector won't be. Thus, they won't
be updated properly and we'll effectively ignore that change until the
On Thu, 1 Dec 2022 at 23:57, Bjorn Andersson wrote:
>
> On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote:
> >
>
> @Ulf, Akhil has a power-domain for a piece of hardware which may be
> voted active by multiple different subsystems (co-processors/execution
> contexts) in the system.
>
On Wed, Dec 07, 2022 at 03:29:09PM +0400, Miaoqian Lin wrote:
> intel_uncore_forcewake_put__locked() is used to release a reference.
>
> Fixes: a6111f7b6604 ("drm/i915: Reduce locking in execlist command
> submission")
> Signed-off-by: Miaoqian Lin
Reviewed-by: Rodrigo Vivi
and will push
On 12/7/22 16:14, Alexander Stein wrote:
i.MX8MP requires a power-domain for this peripheral to use. Add it as
an optional property.
Signed-off-by: Alexander Stein
---
Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
On 12/7/22 16:13, Alexander Stein wrote:
i.MX8MP uses 3 clocks, so soften the restrictions for clocks & clock-names.
Fixes: f5419cb0743f ("dt-bindings: lcdif: Add compatible for i.MX8MP")
Signed-off-by: Alexander Stein
---
Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 4 +++-
1
On Tue, Nov 29, 2022 at 07:19:42PM +, Paul Cercueil wrote:
> Instead of defining two versions of intel_sysfs_rc6_init(), one for each
> value of CONFIG_PM, add a check on !IS_ENABLED(CONFIG_PM) early in the
> function. This will allow the compiler to automatically drop the dead
> code when
On Wed, 5 Oct 2022 at 11:08, Akhil P Oommen wrote:
>
> Allow a consumer driver to poll for cx gdsc collapse through Reset
> framework.
Would you mind extending this commit message, to allow us to better
understand what part is really the consumer part.
I was expecting the consumer part to be
On Wed, 5 Oct 2022 at 11:08, Akhil P Oommen wrote:
>
> Add a reset op compatible function to poll for gdsc collapse. This is
> required because:
> 1. We don't wait for it to turn OFF at hardware for VOTABLE GDSCs.
> 2. There is no way for client drivers (eg. gpu driver) to do
>
Hi xurui,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on linus/master v6.1-rc8 next-20221207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
On Wed, Dec 07, 2022 at 01:59:04PM +, Robin Murphy wrote:
> On 2022-12-07 09:21, Jiasheng Jiang wrote:
> > As kzalloc may fail and return NULL pointer, it should be better to check
> > the return value in order to avoid the NULL pointer dereference in
> > __drm_atomic_helper_connector_reset.
>
i.MX8MP requires a power-domain for this peripheral to use. Add it as
an optional property.
Signed-off-by: Alexander Stein
---
Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
i.MX8MP uses 3 clocks, so soften the restrictions for clocks & clock-names.
Fixes: f5419cb0743f ("dt-bindings: lcdif: Add compatible for i.MX8MP")
Signed-off-by: Alexander Stein
---
Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
On 21/11/2022 11:08, Kalyan Thota wrote:
Since DRM encoder type for few encoders can be similar
(like eDP and DP), get the connector type for a given
encoder to differentiate between builtin and pluggable
displays.
Changes in v1:
- add connector type in the disp_info (Dmitry)
- add helper
Hi,
On Tue, Dec 6, 2022 at 10:59 PM Miaoqian Lin wrote:
>
> of_icc_get() alloc resources for path1, we should release it when not
> need anymore. Early return when IS_ERR_OR_NULL(path0) may leak path1.
> Defer getting path1 to fix this.
>
> Fixes: b9364eed9232 ("drm/msm/dpu: Move min BW request
On 05/12/2022 19:44, Bjorn Andersson wrote:
From: Bjorn Andersson
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
necessary definitions and describe the DPU in the SC8280XP.
Signed-off-by: Bjorn Andersson
On Wed, Dec 7, 2022 at 2:15 AM Lucas Stach wrote:
>
> Hi Rob,
>
> Am Dienstag, dem 06.12.2022 um 11:21 -0800 schrieb Rob Clark:
> > From: Rob Clark
> >
> > In cases where implicit sync is used, it is still useful (for things
> > like sub-allocation, etc) to allow userspace to opt-out of implicit
Use the values from the vendor DTs to set ubwc_swizzle in the catalog.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0.
Change the catalog entry accordingly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
Several small corrections for the UBWC setup and related data.
Dmitry Baryshkov (3):
drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
drm/msm/dpu: correct the UBWC version on sm6115
drm/msm/dpu: add missing ubwc_swizzle setting to catalog
On 12/1/22 12:11, Maxime Ripard wrote:
Accessing a register when running under kunit is a bad idea since our
device is completely mocked.
Fail the current test if we ever access any of our hardware registers.
Reviewed-by: Javier Martinez Canillas
Signed-off-by: Maxime Ripard
Reviewed-by:
On 12/1/22 12:11, Maxime Ripard wrote:
The HVS to PixelValve muxing code is fairly error prone and has a bunch
of arbitrary constraints due to the hardware setup.
Let's create a test suite that makes sure that the possible combinations
work and the invalid ones don't.
Reviewed-by: Javier
Hello dear drm/bridge maintainers,
On Fri, Nov 18, 2022 at 11:35:53PM +0100, Uwe Kleine-König wrote:
> From: Uwe Kleine-König
>
> The probe function doesn't make use of the i2c_device_id * parameter so it
> can be trivially converted.
>
> Signed-off-by: Uwe Kleine-König
Do you plan to pick
On 12/1/22 12:11, Maxime Ripard wrote:
In order to test the current atomic_check hooks we need to have a DRM
device that has roughly the same capabilities and layout that the actual
hardware. We'll also need a bunch of functions to create arbitrary
atomic states.
Let's create some helpers to
On 2022-12-07 04:59:23, Kalyan Thota wrote:
> Flush mechanism for DSPP blocks has changed in sc7280 family, it
> allows individual sub blocks to be flushed in coordination with
> master flush control.
>
> Representation: master_flush && (PCC_flush | IGC_flush .. etc )
>
> This change adds
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