Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing
Hi
Am 19.12.22 um 10:23 schrieb José Expósito:
Hi Thomas,
Thanks for CCing me.
There are some issues with this helpers on big endian architectures, you can
run the test on big endian with this command:
$ ./tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/tests \
The WA states that before doing a GSC engine reset we need to alert the
GSC FW and then wait for 200ms for the FW to get ready for it. The GuC
will take care of this for engine reset, but i915 is still responsible
for the full GT reset scenario.
Given that we do full GT resets in the resume paths
From: Tvrtko Ursulin
As the logic for selecting the register and corresponsing values grew, the
code become a bit unsightly. Consolidate by storing the required values at
engine init time in the engine itself, and by doing so minimise the amount
of invariant platform and engine checks during
From: Tvrtko Ursulin
Revert to the original explicit approach and document the reasoning
behind it.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
Cc: Balasubramani Vivekanandan
Cc: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt.c | 13 -
1 file changed, 12 insertions(+), 1
From: Tvrtko Ursulin
First patch to make the platform check not catch all due current lack of
automated testing.
Second patch to consolidate the code a bit and move invariant setup at engine
init time. Don't think I want to merge this one until some test coverage can be
had.
Tvrtko Ursulin
On Fr, 2022-12-16 at 18:50 +0100, Uwe Kleine-König wrote:
[...]
> +static int imx_lcdc_pipe_check(struct drm_simple_display_pipe *pipe,
> +struct drm_plane_state *plane_state,
> +struct drm_crtc_state *crtc_state)
> +{
> + const struct
On Fr, 2022-12-16 at 22:00 +0100, Uwe Kleine-König wrote:
> Hallo Philipp,
>
> On Fri, Dec 16, 2022 at 07:05:13PM +0100, Philipp Zabel wrote:
> > On Fr, 2022-12-16 at 18:50 +0100, Uwe Kleine-König wrote:
> > > From: Marian Cichy
> > >
> > > Add support for the LCD Controller found on i.MX21 and
Wang, Zhi A 于2022年12月19日周一 16:22写道：
>
> I think it is a case-by-case thing. For example:
>
> The current scenario in this function looks like below:
>
> caller pass spt a
> function
> alloc spt b
> something error
> free spt a
> return error
>
> The problem is:
Hi Thomas,
Thanks for CCing me.
There are some issues with this helpers on big endian architectures, you can
run the test on big endian with this command:
$ ./tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/tests \
--arch=powerpc --cross_compile=powerpc64-linux-gnu-
On 12/19/22 09:53, Uwe Kleine-König wrote:
> The listed address doesn't work any more:
>
> puck.c...@hisilicon.com
> host mx5.hisilicon.com [124.71.93.234]
> SMTP error from remote mail server after RCPT
> TO::
> 551 5.1.1 : Recipient address rejected:
> Failed recipient
The listed address doesn't work any more:
puck.c...@hisilicon.com
host mx5.hisilicon.com [124.71.93.234]
SMTP error from remote mail server after RCPT TO::
551 5.1.1 : Recipient address rejected:
Failed recipient validation check.: host 127.0.0.1[127.0.0.1] said:
554 5.7.1
On 12/19/22 09:40, Uwe Kleine-König wrote:
> The driver doesn't make use of any symbol provided by . So
> drop the include.
>
> Signed-off-by: Uwe Kleine-König
> ---
Reviewed-by: Javier Martinez Canillas
--
Best regards,
Javier Martinez Canillas
Core Platforms
Red Hat
Hello Uwe,
On 12/19/22 09:36, Uwe Kleine-König wrote:
> While working on a drm driver that doesn't need the i2c algobit stuff I
> noticed that DRM selects this code even though only 8 drivers actually use
> it. While also only some drivers use i2c, keep the select for I2C for the
> next cleanup
The driver doesn't make use of any symbol provided by . So
drop the include.
Signed-off-by: Uwe Kleine-König
---
drivers/gpu/drm/vc4/vc4_dsi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index 878e05d79e81..08e95c1d4a04 100644
While working on a drm driver that doesn't need the i2c algobit stuff I
noticed that DRM selects this code even though only 8 drivers actually use
it. While also only some drivers use i2c, keep the select for I2C for the
next cleanup patch. Still prepare this already by also selecting I2C for
the
Am 18.12.22 um 07:57 schrieb xinhui pan:
Optimise a little when continuous memory request fails.
There are memory holes and continuous memory request usually fails when
order is too big.
Currently buddy only look for exactly order memory for such request.
Now we can try again to look for
Hi Michel,
yeah that's a known issue. I'm already working on that, looks like I've
just forgotten to add a dma_fence_get() somewhere.
Going to send around a bug fix later today.
Thanks for the report,
Christian.
Am 17.12.22 um 13:12 schrieb Michel Dänzer:
With the drm-next-2022-12-13
On 12/19/2022 9:57 AM, Zheng Wang wrote:
> Hi Zhi,
>
> Thanks again for your reply and clear explaination about the function.
> I still have some doubt about the fix. Here is a invoke chain :
> ppgtt_populate_spt
>->ppgtt_populate_shadow_entry
> ->split_2MB_gtt_entry
> As far as I'm
Hi Zhi,
Thanks again for your reply and clear explaination about the function.
I still have some doubt about the fix. Here is a invoke chain :
ppgtt_populate_spt
->ppgtt_populate_shadow_entry
->split_2MB_gtt_entry
As far as I'm concerned, when something error happens in DMA mapping,
which
Hi,
On 18.12.2022 11:23, Oded Gabbay wrote:
> On Thu, Dec 8, 2022 at 1:08 PM Jacek Lawrynowicz
> wrote:
>> Adds four types of GEM-based BOs for the VPU:
>> - shmem
>> - userptr
>> - internal
>> - prime
>>
>> All types are implemented as struct ivpu_bo, based on
>> struct drm_gem_object.
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