Retrieve secure display's CRC data from the DC hardware in vline0 irq
handler, and store the values in secure display contexts.
Signed-off-by: Alan Liu
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 50 ---
1 file changed, 42 insertions(+), 8 deletions(-)
diff --git
Check if there is a new ROI update during the atomic commit and process
it. A new function amdgpu_dm_crtc_set_secure_display_crc_source() is
implemented to control the state of CRC engine in hardware.
Signed-off-by: Alan Liu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 38 +
When the user requests for secure display ROI or CRC data, the
request will be blocked until the CRC result of current frame is
calculated and updated to secure display ctx in vline0 irq handler.
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-
Implement set/get functions as the callback for userspace to get the CRC
result values of the corresponding ROI configuration of secure display.
Signed-off-by: Alan Liu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 38
Add a new blob properties and implement the property creation and
attachment functions for the CRC result values of secure display.
Signed-off-by: Alan Liu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 1 +
Implement set/get functions as the callback for userspace to update or
get the secure display ROI configuration.
Signed-off-by: Alan Liu
---
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 51 +++
1 file changed, 51 insertions(+)
diff --git
Add a new blob properties as well as the create and attach functions
for configuring region of interested (ROI) of secure display.
Signed-off-by: Alan Liu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 ++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 4 +++
Dear DRM development community,
We'd like to introduce the implementation of the new crtc properties.
First of all, please let me introduce the problem we try to address. With the
popularity of electric vehicles, the car vendors have increasing requirement
for ensuring the integrity of the
On Tue, May 16, 2023 at 7:57 AM Adam Ford wrote:
>
> The high-speed clock is hard-coded to the burst-clock
> frequency specified in the device tree. However, when
> using devices like certain bridge chips without burst mode
> and varying resolutions and refresh rates, it may be
> necessary to
On 10.04.2023 20:52, Dmitry Baryshkov wrote:
> If the Adreno SMMU is dma-coherent, allocation will fail unless we
> disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
> coherent SMMUs (like we have on sm8350 platform).
>
> Fixes: 54af0ceb7595 ("arm64: dts: qcom: sm8350:
On 7.05.2023 10:20, Krzysztof Kozlowski wrote:
> On 05/05/2023 23:40, Konrad Dybcio wrote:
>> Document the SM6375 MDSS.
>>
>> Signed-off-by: Konrad Dybcio
>> ---
>> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216
>> +
>> 1 file changed, 216 insertions(+)
>>
>
>
On 11.05.2023 16:59, Rob Clark wrote:
> From: Rob Clark
>
> When the special handling of qcom,adreno-smmu was moved into
> qcom_smmu_create(), it was overlooked that we didn't have all the
> required entries in qcom_smmu_impl_of_match. So we stopped getting
> adreno_smmu_priv on sc7180,
On 5/15/2023 3:07 PM, Dmitry Baryshkov wrote:
On 16/05/2023 01:01, Marijn Suijten wrote:
On 2023-05-15 13:29:21, Jessica Zhang wrote:
Const, as requested elsewhere. But this function is not used anywhere
in any of the series (because we replaced the usages with more sensible
member
On 5/15/2023 3:01 PM, Marijn Suijten wrote:
On 2023-05-15 13:29:21, Jessica Zhang wrote:
Const, as requested elsewhere. But this function is not used anywhere
in any of the series (because we replaced the usages with more sensible
member accesses like slice_chunk_size).
Acked.
I would
On Mon, 15 May 2023 15:58:26 -0700, Dixit, Ashutosh wrote:
>
> On Mon, 15 May 2023 15:23:58 -0700, Belgaumkar, Vinay wrote:
> >
> >
> > On 5/12/2023 5:39 PM, Dixit, Ashutosh wrote:
> > > On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
> > > Hi Vinay,
> > >
> > >> rps_boost debugfs
On 5/15/2023 3:23 PM, Marijn Suijten wrote:
On 2023-05-15 15:03:46, Abhinav Kumar wrote:
On 5/15/2023 2:21 PM, Marijn Suijten wrote:
On 2023-05-12 11:00:22, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag
The DPHY timings are currently hard coded. Since the input
clock can be variable, the phy timings need to be variable
too. To facilitate this, we need to cache the hs_clock
based on what is generated from the PLL.
The phy_mipi_dphy_get_default_config_for_hsclk function
configures the DPHY
The high-speed clock is hard-coded to the burst-clock
frequency specified in the device tree. However, when
using devices like certain bridge chips without burst mode
and varying resolutions and refresh rates, it may be
necessary to set the high-speed clock dynamically based
on the desired pixel
In order to support variable DPHY timings, it's necessary
to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config
can be used to determine the nominal values for a given resolution
and refresh rate.
Signed-off-by: Adam Ford
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
Make the pll-clock-frequency optional. If it's present, use it
to maintain backwards compatibility with existing hardware. If it
is absent, read clock rate of "sclk_mipi" to determine the rate.
Since it can be optional, change the message from an error to
dev_info.
Signed-off-by: Adam Ford
According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
and max values for M and the frequency range for the VCO_out
calculator were incorrect. This information was contradicted in other
parts of the mini, nano and plus manuals. After reaching out to my
NXP Rep, when confronting
From: Lucas Stach
Scale the blanking packet sizes to match the ratio between HS clock
and DPI interface clock. The controller seems to do internal scaling
to the number of active lanes, so we don't take those into account.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
Tested-by: Chen-Yu
This series fixes the blanking pack size and the PMS calculation. It then
adds support to allows the DSIM to dynamically DPHY clocks, and support
non-burst mode while allowing the removal of the hard-coded clock values
for the PLL for imx8m mini/nano/plus, and it allows the removal of the
Tear down DSC datapath* on encoder cleanup*
On 2023-05-15 14:25:28, Kuogee Hsieh wrote:
>
> Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
> dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
> to tear down DSC data path if DSC data path was setup previous.
>
>
On Mon, 15 May 2023 15:23:58 -0700, Belgaumkar, Vinay wrote:
>
>
> On 5/12/2023 5:39 PM, Dixit, Ashutosh wrote:
> > On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
> > Hi Vinay,
> >
> >> rps_boost debugfs shows host turbo related info. This is not valid
> >> when SLPC is enabled.
> > A
On 2023-05-15 14:25:26, Kuogee Hsieh wrote:
>
> Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
> This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
> adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
> DSC engine and DSC flush bits at
On 2023-05-15 14:25:27, Kuogee Hsieh wrote:
>
> From: Abhinav Kumar
>
> Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
> feature flag information. Each display compression engine (DCE) contains
> dual hard slice DSC encoders so both share same base address but with
>
On 2023-05-15 14:25:25, Kuogee Hsieh wrote:
>
> Add support for DSC 1.2 by providing the necessary hooks to program
> the DPU DSC 1.2 encoder.
>
> Changes in v3:
> -- fixed kernel test rebot report that "__iomem *off" is declared but not
>used at dpu_hw_dsc_config_1_2()
> -- unrolling thresh
You forgot to address the title suggestion "before assign" isn't proper
English.
Copying from v8 review:
"Guard PINGPONG DSC ops behind DPU_PINGPONG_DSC bit"
On 2023-05-15 14:25:23, Kuogee Hsieh wrote:
>
> DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
> both
On 5/3/23 16:15, Sukrut Bellary wrote:
> smatch warning -
> 1) drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3615 gfx_v9_0_kiq_resume()
> warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.
>
> 2) drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:6901 gfx_v10_0_kiq_resume()
> warn: inconsistent returns
On 5/12/2023 5:39 PM, Dixit, Ashutosh wrote:
On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
Hi Vinay,
rps_boost debugfs shows host turbo related info. This is not valid
when SLPC is enabled.
A couple of thoughts about this. It appears people are know only about
rps_boost_info
On 2023-05-15 15:03:46, Abhinav Kumar wrote:
> On 5/15/2023 2:21 PM, Marijn Suijten wrote:
> > On 2023-05-12 11:00:22, Kuogee Hsieh wrote:
> >>
> >> From: Abhinav Kumar
> >>
> >> Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
> >> feature flag information. Each display
On 2023-05-15 14:25:22, Kuogee Hsieh wrote:
>
> DPU < 7.0.0 requires the PINGPONG block to be involved during
> DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
> encoder engine was moved to INTF with the help of the flush mechanism.
> Add a DPU_PINGPONG_DSC feature bit to
Once again, capitalize DSC in the title.
On 2023-05-15 14:25:21, Kuogee Hsieh wrote:
>
> From: Abhinav Kumar
>
> There are some platforms has DSC blocks which have not been declared in
There are some platforms has?
How about (as suggested in earlier review): Some platforms have...
> the
On 5/15/2023 3:03 PM, Abhinav Kumar wrote:
On 5/15/2023 2:21 PM, Marijn Suijten wrote:
On 2023-05-12 11:00:22, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine
On 16/05/2023 01:01, Marijn Suijten wrote:
On 2023-05-15 13:29:21, Jessica Zhang wrote:
Const, as requested elsewhere. But this function is not used anywhere
in any of the series (because we replaced the usages with more sensible
member accesses like slice_chunk_size).
Acked.
I would
On 5/15/2023 2:21 PM, Marijn Suijten wrote:
On 2023-05-12 11:00:22, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so
On 2023-05-15 13:29:21, Jessica Zhang wrote:
> > Const, as requested elsewhere. But this function is not used anywhere
> > in any of the series (because we replaced the usages with more sensible
> > member accesses like slice_chunk_size).
>
> Acked.
>
> I would prefer to keep this helper so
On Tue, 16 May 2023 at 00:26, Kuogee Hsieh wrote:
>
> From: Abhinav Kumar
>
> Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
> feature flag information. Each display compression engine (DCE) contains
> dual hard slice DSC encoders so both share same base address but
On Tue, 16 May 2023 at 00:26, Kuogee Hsieh wrote:
>
> Add support for DSC 1.2 by providing the necessary hooks to program
> the DPU DSC 1.2 encoder.
>
> Changes in v3:
> -- fixed kernel test rebot report that "__iomem *off" is declared but not
>used at dpu_hw_dsc_config_1_2()
> -- unrolling
On Tue, 16 May 2023 at 00:25, Kuogee Hsieh wrote:
>
> DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
> both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
> executed to complete DSC configuration if DSC hardware block is present.
> Hence test
On Tue, 16 May 2023 at 00:25, Kuogee Hsieh wrote:
>
> DPU < 7.0.0 requires the PINGPONG block to be involved during
> DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
> encoder engine was moved to INTF with the help of the flush mechanism.
> Add a DPU_PINGPONG_DSC feature bit to
On 2023-05-12 11:00:21, Kuogee Hsieh wrote:
>
> Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
Can you rewrite "is piggyback"? Something like "Currently DSC flushing
happens during interface configuration". And it's intf configuration
**on the CTL**, which makes this
Applied. Thanks!
Alex
On Mon, May 15, 2023 at 3:18 AM Su Hui wrote:
>
> No need cast (void*) to (struct amdgpu_device *).
>
> Signed-off-by: Su Hui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
>
On 5/15/2023 2:23 PM, Marijn Suijten wrote:
On 2023-05-15 13:58:35, Abhinav Kumar wrote:
On 5/15/2023 1:07 PM, Marijn Suijten wrote:
On 2023-05-15 11:20:02, Abhinav Kumar wrote:
On 5/14/2023 2:39 PM, Marijn Suijten wrote:
DSC*, and mention 1.1 explicitly (since this skips the 1.2
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both share same base address but with
its own different sub block address.
changes in v4:
--
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to make it consistent with
the location of flush
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and
From: Abhinav Kumar
There are some platforms has DSC blocks which have not been declared in
the catalog. Complete DSC 1.1 support for all platforms by adding the
missing blocks to MSM8998 and SC8180X.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]:
By the way, can we replace "relevant chipsets" in the title with
"DPU >= 7.0" like the other titles?
- Marijn
On 2023-05-12 11:00:22, Kuogee Hsieh wrote:
On 2023-05-15 13:58:35, Abhinav Kumar wrote:
>
>
>
> On 5/15/2023 1:07 PM, Marijn Suijten wrote:
> > On 2023-05-15 11:20:02, Abhinav Kumar wrote:
> >>
> >>
> >>
> >> On 5/14/2023 2:39 PM, Marijn Suijten wrote:
> >>> DSC*, and mention 1.1 explicitly (since this skips the 1.2 blocks, while
> >>>
On 2023-05-12 11:00:22, Kuogee Hsieh wrote:
>
> From: Abhinav Kumar
>
> Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
> feature flag information. Each display compression engine (DCE) contains
> dual hard slice DSC encoders so both share same base address but with
>
On 5/15/2023 1:07 PM, Marijn Suijten wrote:
On 2023-05-15 11:20:02, Abhinav Kumar wrote:
On 5/14/2023 2:39 PM, Marijn Suijten wrote:
DSC*, and mention 1.1 explicitly (since this skips the 1.2 blocks, while
the series is clearly aimed at 1.1...). This was done for the DSC 1.2
HW block
On 5/14/2023 2:25 PM, Marijn Suijten wrote:
On 2023-05-12 14:32:14, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_dsc_helper.h | 65
> Hi Fei,
>
> On Fri, May 12, 2023 at 04:28:25PM -0700, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> To comply with the design that buffer objects shall have immutable
>> cache setting through out their life cycle, {set, get}_caching ioctl's
>> are no longer supported from MTL onward. With
On 2023-05-15 10:06:33, Kuogee Hsieh wrote:
> >> +static inline int _dsc_calc_ob_max_addr(struct dpu_hw_dsc *hw_dsc, int
> >> num_ss)
> > Can you write out "ob" fully?
> >
> > These don't need to be marked "inline", same below.
Please add newlines around your reply, like I did here, to make it
On 2023-05-15 10:46:48, Kuogee Hsieh wrote:
> > Friendly request to strip/snip unneeded context (as done in this reply)
> > to make it easier to spot the conversation, and replies to it.
> >
> > - Marijn
>
> Thanks for suggestion.
>
> How can I do that?
>
> just manually delete unneeded
On 2023-05-15 11:20:02, Abhinav Kumar wrote:
>
>
>
> On 5/14/2023 2:39 PM, Marijn Suijten wrote:
> > DSC*, and mention 1.1 explicitly (since this skips the 1.2 blocks, while
> > the series is clearly aimed at 1.1...). This was done for the DSC 1.2
> > HW block patch after all.
> >
> > in
From: Petr Tesarik Sent: Tuesday, May 9, 2023
2:18 AM
>
> The software IO TLB was designed with the assumption that it is not
> used much, especially on 64-bit systems, so a small fixed memory
> area (currently 64 MiB) is sufficient to handle the few cases which
> still require a bounce buffer.
On 5/15/2023 12:12 PM, Dmitry Baryshkov wrote:
On Mon, 15 May 2023 at 21:45, Abhinav Kumar wrote:
On 5/14/2023 10:01 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:12, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation
On Mon, 15 May 2023 at 21:45, Abhinav Kumar wrote:
>
>
>
> On 5/14/2023 10:01 AM, Dmitry Baryshkov wrote:
> > On Sat, 13 May 2023 at 01:12, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
> >>> Take into account the plane rotation and flipping when
On Sun, May 14, 2023, Lorenzo Stoakes wrote:
> No invocation of get_user_pages() use the vmas parameter, so remove it.
>
> The GUP API is confusing and caveated. Recent changes have done much to
> improve that, however there is more we can do. Exporting vmas is a prime
> target as the caller has
It turned out that Aya Neo Air Plus had a different board name than
expected.
This patch changes Aya Neo Air's quirk to account for that, as both
devices share "Air" in DMI product name.
Tested on Air claiming to be an Air Pro, and on Air Plus.
Signed-off-by: Maya Matuszczyk
---
On 5/14/2023 10:01 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:12, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation and flipping when calculating src
positions for the wide plane parts.
Signed-off-by: Dmitry Baryshkov
From: Francesco Dolcini
Remove unneeded stray semicolon.
Reported-by: kernel test robot
Link: https://lore.kernel.org/oe-kbuild-all/202305152341.oisjrpv6-...@intel.com/
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/bridge/tc358768.c | 2 +-
1 file changed, 1 insertion(+), 1
On 5/14/2023 2:39 PM, Marijn Suijten wrote:
DSC*, and mention 1.1 explicitly (since this skips the 1.2 blocks, while
the series is clearly aimed at 1.1...). This was done for the DSC 1.2
HW block patch after all.
in catalog -> to catalog
But it's just two platforms, you can fit MSM8998 and
On Mon, May 15, 2023 at 07:55:44PM +0200, Sam Ravnborg wrote:
> Hi Thomas,
>
> On Mon, May 15, 2023 at 11:40:23AM +0200, Thomas Zimmermann wrote:
> > Use the regular fbdev helpers for framebuffer I/O instead of DRM's
> > helpers. Armada does not use damage handling, so DRM's fbdev helpers
> > are
On Mon, 15 May 2023 at 20:47, Kuogee Hsieh wrote:
>
>
> On 5/14/2023 2:46 PM, Marijn Suijten wrote:
> > On 2023-05-12 21:19:19, Dmitry Baryshkov wrote:
> > >>> +static inline void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc
> >>> *hw_dsc,
> >>> +
From: Randy Dunlap
[ Upstream commit 2b76ffe81e32afd6d318dc4547e2ba8c46207b77 ]
Fix build errors on ARCH=alpha when CONFIG_MDA_CONSOLE=m.
This allows the ARCH macros to be the only ones defined.
In file included from ../drivers/video/console/mdacon.c:37:
../arch/alpha/include/asm/vga.h:17:40:
Hi Thomas,
On Mon, May 15, 2023 at 11:40:23AM +0200, Thomas Zimmermann wrote:
> Use the regular fbdev helpers for framebuffer I/O instead of DRM's
> helpers. Armada does not use damage handling, so DRM's fbdev helpers
> are mere wrappers around the fbdev code.
>
> By using fbdev helpers directly
On 5/14/2023 2:46 PM, Marijn Suijten wrote:
On 2023-05-12 21:19:19, Dmitry Baryshkov wrote:
+static inline void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc *hw_dsc,
+ const enum dpu_pingpong pp)
+{
+ struct dpu_hw_blk_reg_map *hw;
Hi Thomas,
On Mon, May 15, 2023 at 11:40:24AM +0200, Thomas Zimmermann wrote:
> Use the regular fbdev helpers for framebuffer I/O instead of DRM's
> helpers. Exynos does not use damage handling, so DRM's fbdev helpers
> are mere wrappers around the fbdev code.
>
> By using fbdev helpers directly
From: Randy Dunlap
[ Upstream commit 2b76ffe81e32afd6d318dc4547e2ba8c46207b77 ]
Fix build errors on ARCH=alpha when CONFIG_MDA_CONSOLE=m.
This allows the ARCH macros to be the only ones defined.
In file included from ../drivers/video/console/mdacon.c:37:
../arch/alpha/include/asm/vga.h:17:40:
On 5/14/2023 3:18 PM, Marijn Suijten wrote:
On 2023-05-12 11:00:20, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at
On 5/14/2023 3:18 PM, Marijn Suijten wrote:
On 2023-05-12 11:00:20, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at
On 5/13/2023 1:28 PM, Marijn Suijten wrote:
On 2023-05-12 14:32:11, Jessica Zhang wrote:
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
From: Randy Dunlap
[ Upstream commit 2b76ffe81e32afd6d318dc4547e2ba8c46207b77 ]
Fix build errors on ARCH=alpha when CONFIG_MDA_CONSOLE=m.
This allows the ARCH macros to be the only ones defined.
In file included from ../drivers/video/console/mdacon.c:37:
../arch/alpha/include/asm/vga.h:17:40:
On 15/05/2023 18:28, neil.armstr...@linaro.org wrote:
>> It's just a link stored in automated responses, what's here childish?
>> It's still valid in current cycle! Look:
>>
>> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
>>
>> What's the
From: Randy Dunlap
[ Upstream commit 2b76ffe81e32afd6d318dc4547e2ba8c46207b77 ]
Fix build errors on ARCH=alpha when CONFIG_MDA_CONSOLE=m.
This allows the ARCH macros to be the only ones defined.
In file included from ../drivers/video/console/mdacon.c:37:
../arch/alpha/include/asm/vga.h:17:40:
On 15/05/2023 18:22, neil.armstr...@linaro.org wrote:
>>> Meson is the only or almost the only platform making such changes. I
>>> don't get why, because the conflict could be easily avoided with using
>>> different names for defines in bindings and local clock. Approach of
>>> having bindings
On 15/05/2023 18:22, Krzysztof Kozlowski wrote:
On 15/05/2023 18:15, Neil Armstrong wrote:
On 13/05/2023 20:32, Krzysztof Kozlowski wrote:
On 12/05/2023 15:11, Neil Armstrong wrote:
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
(ver 1.21a),
with a custom glue
On 15/05/2023 18:15, Krzysztof Kozlowski wrote:
On 15/05/2023 18:13, Krzysztof Kozlowski wrote:
On 15/05/2023 18:06, Neil Armstrong wrote:
On 13/05/2023 20:28, Krzysztof Kozlowski wrote:
On 12/05/2023 15:11, Neil Armstrong wrote:
Expose VCLK2_SEL clock id and add new ids for the CTS_ENCL and
On 15/05/2023 18:15, Neil Armstrong wrote:
> On 13/05/2023 20:32, Krzysztof Kozlowski wrote:
>> On 12/05/2023 15:11, Neil Armstrong wrote:
>>> The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
>>> (ver 1.21a),
>>> with a custom glue managing the IP resets, clock and data
The TC358867/TC9595 devices are compatible with the predecessor TC358767.
Document compatible strings for the new devices, so they can be discerned
in board DTs. Update the title to match description in the process.
Signed-off-by: Marek Vasut
---
Cc: Andrey Gusakov
Cc: Andrzej Hajda
Cc: Conor
On 13/05/2023 20:32, Krzysztof Kozlowski wrote:
On 12/05/2023 15:11, Neil Armstrong wrote:
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
(ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the
DW-HDMI Glue
on the same Amlogic
On 15/05/2023 18:13, Krzysztof Kozlowski wrote:
> On 15/05/2023 18:06, Neil Armstrong wrote:
>> On 13/05/2023 20:28, Krzysztof Kozlowski wrote:
>>> On 12/05/2023 15:11, Neil Armstrong wrote:
Expose VCLK2_SEL clock id and add new ids for the CTS_ENCL and CTS_ENCL_SEL
clocks on G12A
On 15/05/2023 18:06, Neil Armstrong wrote:
> On 13/05/2023 20:28, Krzysztof Kozlowski wrote:
>> On 12/05/2023 15:11, Neil Armstrong wrote:
>>> Expose VCLK2_SEL clock id and add new ids for the CTS_ENCL and CTS_ENCL_SEL
>>> clocks on G12A compatible SoCs.
>>>
>>> Signed-off-by: Neil Armstrong
>>>
On 13/05/2023 20:28, Krzysztof Kozlowski wrote:
On 12/05/2023 15:11, Neil Armstrong wrote:
Expose VCLK2_SEL clock id and add new ids for the CTS_ENCL and CTS_ENCL_SEL
clocks on G12A compatible SoCs.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.h | 1 -
Hi Tomi,
On 12-May-23 14:45, Tomi Valkeinen wrote:
> On 09/05/2023 12:30, Aradhya Bhatia wrote:
>> From: Nikhil Devshatwar
>>
>> With new connector model, mhdp bridge will not create the connector and
>> SoC driver will rely on format negotiation to setup the encoder format.
>>
>> Support
This patch add Li Yi and Sui Jingfeng as maintainer to drm/loongson driver
Signed-off-by: Sui Jingfeng
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 402e26d0cdbc..8cdb75f653bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6945,6
Loongson display controller IP has been integrated in both Loongson north
bridge chipset(ls7a1000/ls7a2000) and Loongson SoCs(ls2k1000/ls2k2000), it
has been even included in Loongson self-made BMC products.
This display controller is a PCI device. It has two display pipes and each
display pipe
On Mon, May 15, 2023 at 04:22:38PM +0200, AngeloGioacchino Del Regno wrote:
> Il 15/05/23 15:36, Julien Stephan ha scritto:
> > On Mon, May 15, 2023 at 02:22:52PM +0200, AngeloGioacchino Del Regno wrote:
> > > Il 15/05/23 11:05, Julien Stephan ha scritto:
> > ..snip..
> > > > +
On Fri, May 12, 2023 at 11:54:09AM +0530, Ankit Nautiyal wrote:
> As per Bsepc:49259, Bigjoiner BW check puts restriction on the
> compressed bpp for a given CDCLK, pixelclock in cases where
> Bigjoiner + DSC are used.
>
> Currently compressed bpp is computed first, and it is ensured that
> the
On Mon, May 15, 2023 at 10:11:39AM -0400, Alex Deucher wrote:
> On Mon, May 15, 2023 at 3:17 AM Dan Carpenter
> wrote:
> >
> > On Mon, May 15, 2023 at 09:34:28AM +0800, Su Hui wrote:
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > >
Il 15/05/23 16:07, Julien Stephan ha scritto:
On Mon, May 15, 2023 at 02:22:52PM +0200, AngeloGioacchino Del Regno wrote:
+#define CSIxB_OFFSET 0x1000
What if we grab two (or three?) iospaces from devicetree?
- base (global)
- csi_a
- csi_b
That would make it possible to maybe
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