Hello,
syzbot found the following issue on:
HEAD commit:a4422ff22142 usb: typec: qcom: Add Qualcomm PMIC Type-C dr..
git tree: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
usb-testing
console output: https://syzkaller.appspot.com/x/log.txt?x=1524556628
kernel
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5
From: Dmitry Baryshkov
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica
Currently, hdisplay is being divided by 3 for DSC. However, this
calculation only works for cases where BPP = 8.
Update hdisplay calculation to be bytes_per_line / 3, so that it
accounts for cases where BPP != 8.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica
Use MSM and DRM DSC helper methods to configure DSC for DSI.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_dsc_helper.h | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h
Add helper to get the integer value of drm_dsc_config.bits_per_pixel
Reviewed-by: Marijn Suijten
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/display/drm_dsc_helper.h
From: Dmitry Baryshkov
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
The current dpu_hw_dsc calculation for det_thresh_flatness does not
match the downstream calculation or the DSC spec.
Use the DRM DSC helper for det_thresh_flatness to match downstream
implementation and the DSC spec.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by:
There are some overlap in calculations for MSM-specific DSC variables
between DP and DSI. In addition, the calculations for initial_scale_value
and det_thresh_flatness that are defined within the DSC 1.2 specifications,
but aren't yet included in drm_dsc_helper.c.
This series moves these
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Reviewed-by: Marijn Suijten
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 10 ++
1 file changed, 10
On 18/05/2023 01:58, Marijn Suijten wrote:
On 2023-05-17 14:32:42, Jessica Zhang wrote:
On 5/17/2023 2:13 PM, Marijn Suijten wrote:
On 2023-05-17 11:51:10, Jessica Zhang wrote:
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the
On 18/05/2023 01:27, Jessica Zhang wrote:
Add helper to get the integer value of drm_dsc_config.bits_per_pixel
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 7 +++
1 file changed, 7 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
On 18/05/2023 01:27, Jessica Zhang wrote:
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 10 ++
1 file
On 18/05/2023 01:01, Kuogee Hsieh wrote:
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same
On 18/05/2023 01:22, Marijn Suijten wrote:
On 2023-05-17 15:01:56, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at
On 18/05/2023 01:01, Kuogee Hsieh wrote:
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit
On 5/17/2023 4:01 PM, Marijn Suijten wrote:
On 2023-05-17 15:27:18, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_dsc_helper.h | 38
On 16/05/2023 23:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350 display expansion pack.
The panel enables display compression (DSC v1.2) by default.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/panel/Kconfig
On 5/17/23 12:33, Hamza Mahfooz wrote:
Since, we are only interested in having
drm_edid_override_connector_update(), update the value of
connector->edid_blob_ptr. We don't care about the return value of
drm_edid_override_connector_update() here. So, drop count.
Fixes: 068553e14f86
On 5/17/23 12:33, Hamza Mahfooz wrote:
set_abm_event() is never actually used. So, drop it.
Fixes: b46c01aa0329 ("drm/amd/display: Refactor ABM feature")
Reported-by: kernel test robot
Reported-by: Tom Rix
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c |
On 5/17/23 12:33, Hamza Mahfooz wrote:
get_available_dsc_slices() returns the number of indices set, and all of
the users of get_available_dsc_slices() don't cross the returned bound
when iterating over available_slices[]. So, the memset() in
get_available_dsc_slices() is redundant and can be
On 5/14/2023 10:06 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:39, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF indices. As of commit ef58e0ad3436
Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
queued to the underlying hardware.
This distinction is important to make, since the wake conditional in the GPU
scheduler thread wakes up when
Rename drm_sched_ready() to drm_sched_can_queue(). "ready" can mean many
things and is thus meaningless in this context. Instead, rename to a name
which precisely conveys what is being checked.
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
---
Ignore this series--I'll repost without the duplication.
Regards,
Luben
On 2023-05-17 19:08, Luben Tuikov wrote:
> Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
> is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
> queued to the underlying
On 5/17/23 19:04, Raphael Gallais-Pou wrote:
Hi Marek
Hi,
On 5/17/23 17:41, Marek Vasut wrote:
On 5/17/23 16:35, Raphael Gallais-Pou wrote:
Hi,
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 0f1110e42c93..a6e2e20f12fa 100644
---
On 5/17/2023 3:47 PM, Marijn Suijten wrote:
Title: "DPU >= 7.0" instead of "relevant chipsets" to match the others.
On 2023-05-17 15:01:58, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each
Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
queued to the underlying hardware.
This distinction is important to make, since the wake conditional in the GPU
scheduler thread wakes up when
Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
queued to the underlying hardware.
This distinction is important to make, since the wake conditional in the GPU
scheduler thread wakes up when
Rename drm_sched_ready() to drm_sched_can_queue(). "ready" can mean many
things and is thus meaningless in this context. Instead, rename to a name
which precisely conveys what is being checked.
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
---
On 2023-05-17 16:43, Alex Deucher wrote:
> On Wed, May 17, 2023 at 3:04 PM Luben Tuikov wrote:
>>
>> Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
>
> I think drm_sched_wakeup_if_can_queue() looks cleaner.
Yeah, I can change it to this--I was concerned of too many
On 2023-05-17 15:27:18, Jessica Zhang wrote:
> Introduce MSM-specific DSC helper methods, as some calculations are
> common between DP and DSC.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/msm_dsc_helper.h | 38
>
> 1 file changed, 38
On 2023-05-17 14:32:42, Jessica Zhang wrote:
>
>
> On 5/17/2023 2:13 PM, Marijn Suijten wrote:
> > On 2023-05-17 11:51:10, Jessica Zhang wrote:
> >> Add helpers to calculate det_thresh_flatness and initial_scale_value as
> >> these calculations are defined within the DSC spec.
> >>
> >>
Title: Tear down DSC datapath* on encoder cleanup*
On 2023-05-17 15:01:59, Kuogee Hsieh wrote:
> Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
> dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
> to tear down DSC data path if DSC data path was setup previous.
>
>
Title: "DPU >= 7.0" instead of "relevant chipsets" to match the others.
On 2023-05-17 15:01:58, Kuogee Hsieh wrote:
> From: Abhinav Kumar
>
> Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
> feature flag information. Each display compression engine (DCE) contains
>
On 2023-05-17 15:01:57, Kuogee Hsieh wrote:
> Currently DSC flushing happens during interface configuration at
> dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
> dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
> to handle both per-DSC engine and DSC flush bits
The current dpu_hw_dsc calculation for det_thresh_flatness does not
match the downstream calculation or the DSC spec.
Use the DRM DSC helper for det_thresh_flatness to match downstream
implementation and the DSC spec.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by:
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_dsc_helper.h | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h
Add helper to get the integer value of drm_dsc_config.bits_per_pixel
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/display/drm_dsc_helper.h
From: Dmitry Baryshkov
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
Currently, hdisplay is being divided by 3 for DSC. However, this
calculation only works for cases where BPP = 8.
Update hdisplay calculation to be bytes_per_line / 3, so that it
accounts for cases where BPP != 8.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica
From: Dmitry Baryshkov
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica
Use MSM and DRM DSC helper methods to configure DSC for DSI.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
There are some overlap in calculations for MSM-specific DSC variables
between DP and DSI. In addition, the calculations for initial_scale_value
and det_thresh_flatness that are defined within the DSC 1.2 specifications,
but aren't yet included in drm_dsc_helper.c.
This series moves these
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 10 ++
1 file changed, 10 insertions(+)
diff --git
On 2023-05-17 15:01:56, Kuogee Hsieh wrote:
> Add support for DSC 1.2 by providing the necessary hooks to program
> the DPU DSC 1.2 encoder.
>
> Changes in v3:
> -- fixed kernel test rebot report that "__iomem *off" is declared but not
>used at dpu_hw_dsc_config_1_2()
> -- unrolling thresh
DSC* in the title.
On 2023-05-17 15:01:52, Kuogee Hsieh wrote:
> From: Abhinav Kumar
>
> Some platforms have DSC blocks which have not been declared in the catalog.
> Complete DSC 1.1 support for all platforms by adding the missing blocks to
> MSM8998 and SC8180X.
>
> Changes in v9:
> -- add
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with
its own different sub block address.
changes in v4:
-- delete
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc()
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter
From: Abhinav Kumar
Some platforms have DSC blocks which have not been declared in the catalog.
Complete DSC 1.1 support for all platforms by adding the missing blocks to
MSM8998 and SC8180X.
Changes in v9:
-- add MSM8998 and SC8180x to commit titil
Changes in v10:
-- fix grammar at commit
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]:
On 5/17/2023 2:15 PM, Marijn Suijten wrote:
On 2023-05-17 11:51:11, Jessica Zhang wrote:
From: Dmitry Baryshkov
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
On Wed, May 17, 2023 at 10:30 PM Aaro Koskinen wrote:
> This one has some issue as mmci-omap is unable to find the GPIOs on 770.
>
> On Mon, May 08, 2023 at 11:20:07PM +0200, Linus Walleij wrote:
> > +static struct gpiod_lookup_table nokia770_mmc_gpio_table = {
> > + .dev_id = "mmci-omap",
>
Hi Adam,
On 17.05.2023 04:55, Adam Ford wrote:
> On Mon, May 15, 2023 at 6:57 PM Adam Ford wrote:
>> The DPHY timings are currently hard coded. Since the input
>> clock can be variable, the phy timings need to be variable
>> too. To facilitate this, we need to cache the hs_clock
>> based on
On 5/17/2023 2:13 PM, Marijn Suijten wrote:
On 2023-05-17 11:51:10, Jessica Zhang wrote:
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Signed-off-by: Jessica Zhang
Was this r-b dropped because of changing the
On 5/17/2023 2:26 PM, Marijn Suijten wrote:
On 2023-05-17 11:51:14, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_dsc_helper.h | 38
On Tue, May 9, 2023 at 11:33 AM Chia-I Wu wrote:
>
> Extend the address and size validations to AMDGPU_VA_OP_UNMAP and
> AMDGPU_VA_OP_CLEAR by moving the validations to amdgpu_gem_va_ioctl.
>
> Internal users of amdgpu_vm_bo_map are no longer validated but they
> should be fine.
>
> Userspace
On 2023-05-17 11:51:14, Jessica Zhang wrote:
> Introduce MSM-specific DSC helper methods, as some calculations are
> common between DP and DSC.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/msm_dsc_helper.h | 38
>
> 1 file changed, 38
On Wed, May 17, 2023 at 10:39 PM Aaro Koskinen wrote:
> When tested w/gpio-descriptors-omap branch, the touchscreen probe fails:
>
> [2.378540] SPI driver ads7846 has no spi_device_id for ti,tsc2046
> [2.391906] SPI driver ads7846 has no spi_device_id for ti,ads7843
> [2.405029] SPI
On 2023-05-17 11:51:13, Jessica Zhang wrote:
> From: Dmitry Baryshkov
>
> Use new DRM DSC helpers to setup DSI DSC configuration. The
> initial_scale_value needs to be adjusted according to the standard, but
> this is a separate change.
>
> Signed-off-by: Dmitry Baryshkov
> Reviewed-by:
On 2023-05-17 11:51:12, Jessica Zhang wrote:
> Add helper to get the integer value of drm_dsc_config.bits_per_pixel
>
> Signed-off-by: Jessica Zhang
Seems fine, but folks might request to make int->integer to make it more
clear that it returns the integer part, and/or add the commit body to a
On 2023-05-17 11:51:11, Jessica Zhang wrote:
> From: Dmitry Baryshkov
>
> Add a helper setting config values which are typically constant across
> operating modes (table E-4 of the standard) and mux_word_size (which is
> a const according to 3.5.2).
>
> Signed-off-by: Dmitry Baryshkov
>
On 2023-05-17 11:51:10, Jessica Zhang wrote:
> Add helpers to calculate det_thresh_flatness and initial_scale_value as
> these calculations are defined within the DSC spec.
>
> Signed-off-by: Jessica Zhang
Was this r-b dropped because of changing the return types in v10->v11?
Reviewed-by:
On 5/17/2023 1:59 PM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW
On Wed, May 17, 2023 at 9:59 PM Aaro Koskinen wrote:
> This does not compile as nokia770_ads7846_props is declared twice,
> and nokia770_cbus_props and nokia770_mpuio_gpiochip_swnode are missing.
H I think we should probably update omap1_defconfig to enable
all the OMAP1 drivers so we have
On 5/2/2023 08:27, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication have contain the
have contain?
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the meu
'meu manifest'
On Wed, May 17, 2023 at 3:08 AM Su Hui wrote:
>
> No need cast (void*) to (struct radeon_device *)
> or (struct radeon_ring *).
>
> Signed-off-by: Su Hui
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/radeon/r100.c | 8
> drivers/gpu/drm/radeon/r300.c | 2 +-
>
On Wed, May 17, 2023 at 11:02 AM Alex Deucher wrote:
>
> + dri-devel for scheduler
>
> On Tue, May 9, 2023 at 6:23 AM ZhenGuo Yin wrote:
> >
> > [Why]
> > drm_sched_entity_add_dependency_cb ignores the scheduled fence and return
> > false.
> > If entity's dependency is a schedulerd error fence
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW to be
pinned in GGTT after the xfer is
On Wed, May 17, 2023 at 3:04 PM Luben Tuikov wrote:
>
> Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
I think drm_sched_wakeup_if_can_queue() looks cleaner.
Alex
> is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
> queued to the
On Wed, May 17, 2023 at 3:04 PM Luben Tuikov wrote:
>
> Rename drm_sched_ready() to drm_sched_can_queue(). "ready" can mean many
> things and is thus meaningless in this context. Instead, rename to a name
> which precisely conveys what is being checked.
>
> Cc: Christian König
> Cc: Alex Deucher
Hi,
On Mon, May 08, 2023 at 11:20:06PM +0200, Linus Walleij wrote:
> The CBUS also has the ADS7846 touchscreen attached.
Not sure what this comment means. CBUS is for Retu/Tahvo, and touchscreen
is SPI.
When tested w/gpio-descriptors-omap branch, the touchscreen probe fails:
[2.378540] SPI
On 5/17/23 3:08 PM, Konrad Dybcio wrote:
On 17.05.2023 20:09, Jonathan Marek wrote:
AFAIK GMU_ALWAYS_ON_COUNTER does not have the same value as
CP_ALWAYS_ON_COUNTER (only the same frequency), so changing this would break
userspace expecting to be able to compare the value returned by
Hi,
This one has some issue as mmci-omap is unable to find the GPIOs on 770.
On Mon, May 08, 2023 at 11:20:07PM +0200, Linus Walleij wrote:
> +static struct gpiod_lookup_table nokia770_mmc_gpio_table = {
> + .dev_id = "mmci-omap",
Changing this to "mmci-omap.1" helped, not sure if that is a
On 5/17/2023 12:25 PM, Marijn Suijten wrote:
On 2023-05-17 21:13:36, Marijn Suijten wrote:
On 2023-05-17 11:51:17, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods to configure DSC for DSI.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
Hi,
This does not compile as nokia770_ads7846_props is declared twice,
and nokia770_cbus_props and nokia770_mpuio_gpiochip_swnode are missing.
On Mon, May 08, 2023 at 11:20:06PM +0200, Linus Walleij wrote:
> +static const struct software_node_ref_args nokia770_cbus_gpio_refs[] = {
> +
On 17/05/2023 16:52, Alexandre Bailon wrote:
> From: Julien Stephan
>
> By default we will call drm_gem_mmap() unless the apu driver has
> declared it's own mmap handler.
>
> Signed-off-by: Julien Stephan
> Reviewed-by: Julien Stephan
One does not have to review own code. We all assume that
On 17/05/2023 21:38, Krzysztof Kozlowski wrote:
> On 17/05/2023 16:52, Alexandre Bailon wrote:
>> This adds the device tree bindings for the APU DRM driver.
>>
>> Signed-off-by: Alexandre Bailon
>> Reviewed-by: Julien Stephan
>
> There are so many errors in this patch... that for sure it was
On 17/05/2023 16:52, Alexandre Bailon wrote:
> This adds the device tree bindings for the APU DRM driver.
>
> Signed-off-by: Alexandre Bailon
> Reviewed-by: Julien Stephan
There are so many errors in this patch... that for sure it was not
tested. Reduced review, except what was already said:
From: Pranjal Ramajor Asha Kanojiya
Validating user data does not need to be protected by any lock and it is
safe to move it out of critical region.
Fixes: ff13be830333 ("accel/qaic: Add datapath")
Fixes: 129776ac2e38 ("accel/qaic: Add control path")
Signed-off-by: Pranjal Ramajor Asha Kanojiya
From: Pranjal Ramajor Asha Kanojiya
QAIC_ATTACH_SLICE_BO attaches slicing configuration to a BO. Validate if
given BO is already sliced. An already sliced BO cannot be sliced again.
Fixes: ff13be830333 ("accel/qaic: Add datapath")
Signed-off-by: Pranjal Ramajor Asha Kanojiya
Reviewed-by: Carl
From: Pranjal Ramajor Asha Kanojiya
During QAIC_ATTACH_SLICE_BO, we associate a BO to its DBC. We need to
grab the dbc->ch_lock to make sure that DBC does not goes away while
QAIC_ATTACH_SLICE_BO is still running.
Fixes: ff13be830333 ("accel/qaic: Add datapath")
Signed-off-by: Pranjal Ramajor
From: Pranjal Ramajor Asha Kanojiya
Before calling synchronize_srcu() we clear the transfer list, this is to
allow all the QAIC_WAIT_BO callers to exit otherwise the system could
deadlock. There could be a corner case where more elements get added to
transfer list after we have flushed it.
If msg_xfer() is unable to queue part of a NNC message because the MHI ring
is full, it will attempt to give the QSM some time to drain the queue.
However, if QSM fails to make any room, msg_xfer() will fail and tell the
caller to try again. This is problematic because part of the message may
During development of new features, we noticed some spots in the code that
could be improved based on review feedback from the initial driver series.
Also two race condition fixes, one found during stress testing and another
via code inspection.
Jeffrey Hugo (1):
accel/qaic: Fix NNC message
On 2023-05-17 21:13:36, Marijn Suijten wrote:
>
> On 2023-05-17 11:51:17, Jessica Zhang wrote:
> >
> > Use MSM and DRM DSC helper methods to configure DSC for DSI.
> >
> > Reviewed-by: Dmitry Baryshkov
> > Reviewed-by: Marijn Suijten
> > Signed-off-by: Jessica Zhang
> > ---
> >
On 2023-05-17 11:51:17, Jessica Zhang wrote:
>
> Use MSM and DRM DSC helper methods to configure DSC for DSI.
>
> Reviewed-by: Dmitry Baryshkov
> Reviewed-by: Marijn Suijten
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ---
> 1 file changed, 4
On 17.05.2023 20:09, Jonathan Marek wrote:
> AFAIK GMU_ALWAYS_ON_COUNTER does not have the same value as
> CP_ALWAYS_ON_COUNTER (only the same frequency), so changing this would break
> userspace expecting to be able to compare the value returned by
> MSM_PARAM_TIMESTAMP with CP timestamp
> On 16/05/2023 19:11, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> To comply with the design that buffer objects shall have immutable
>> cache setting through out their life cycle, {set, get}_caching ioctl's
>> are no longer supported from MTL onward. With that change caching
>> policy can
Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
queued to the underlying hardware.
This distinction is important to make, since the wake conditional in the GPU
scheduler thread wakes up when
Rename drm_sched_ready() to drm_sched_can_queue(). "ready" can mean many
things and is thus meaningless in this context. Instead, rename to a name
which precisely conveys what is being checked.
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Luben Tuikov
---
Use MSM and DRM DSC helper methods to configure DSC for DSI.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5
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