On 2023-07-27 19:20:58, Dmitry Baryshkov wrote:
> The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
> Rather than checking for the flag, check for the presense of the
> corresponding interrupt line.
>
> Signed-off-by: Dmitry Baryshkov
> ---
>
On 2023-07-27 19:20:58, Dmitry Baryshkov wrote:
> The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
> Rather than checking for the flag, check for the presense of the
> corresponding interrupt line.
>
> Signed-off-by: Dmitry Baryshkov
That's a smart use of the interrupt
On 2023-07-27 22:51:32, Dmitry Baryshkov wrote:
> On 27/07/2023 22:41, Marijn Suijten wrote:
> > On 2023-07-27 22:34:59, Dmitry Baryshkov wrote:
> >> On 27/07/2023 22:29, Marijn Suijten wrote:
> >>> On 2023-07-27 18:04:54, Dmitry Baryshkov wrote:
> In preparation to reworking the IRQ indices,
Title nit: How about making this "UP by 1"?
On 2023-07-27 18:04:55, Dmitry Baryshkov wrote:
> In order to simplify IRQ declarations, shift IRQ indices by 1. This
Same here, UP by one.
> makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have
> to explicitly set the 'no
On 27/07/2023 22:41, Marijn Suijten wrote:
On 2023-07-27 22:34:59, Dmitry Baryshkov wrote:
On 27/07/2023 22:29, Marijn Suijten wrote:
On 2023-07-27 18:04:54, Dmitry Baryshkov wrote:
In preparation to reworking the IRQ indices, move irq_tbl access to
separate helper.
I am not seeing the
On Thu, Jul 20, 2023 at 8:27 AM Helen Koike wrote:
>
> From: Tomeu Vizoso
>
> Developers can easily execute several tests on different devices
> by just pushing their branch to their fork in a repository hosted
> on gitlab.freedesktop.org which has an infrastructure to run jobs
> in several
On 2023-07-27 22:34:59, Dmitry Baryshkov wrote:
> On 27/07/2023 22:29, Marijn Suijten wrote:
> > On 2023-07-27 18:04:54, Dmitry Baryshkov wrote:
> >> In preparation to reworking the IRQ indices, move irq_tbl access to
> >> separate helper.
> >
> > I am not seeing the advantage of the helper, but
On 27/07/2023 22:29, Marijn Suijten wrote:
On 2023-07-27 18:04:54, Dmitry Baryshkov wrote:
In preparation to reworking the IRQ indices, move irq_tbl access to
separate helper.
I am not seeing the advantage of the helper, but making every function
look up dpu_kms->hw_intr->irq_tbl[irq_idx]
On 2023-07-27 18:04:54, Dmitry Baryshkov wrote:
> In preparation to reworking the IRQ indices, move irq_tbl access to
> separate helper.
I am not seeing the advantage of the helper, but making every function
look up dpu_kms->hw_intr->irq_tbl[irq_idx] only once and storing that in
a local
On 2023-07-27 18:04:53, Dmitry Baryshkov wrote:
> In preparation of slighly changing IRQ numbering, move DPU_IRQ_REG()
> macro to the dpu_hw_interrupts.h header. Also split the DPU_IRQ_MASK()
> macro into local DPU_IRQ_MASK() and the global DPU_IRQ_OFFSET() macros.
>
> Signed-off-by: Dmitry
On 2023-07-27 18:04:52, Dmitry Baryshkov wrote:
> There is no point in passing the IRQ index to IRQ callbacks, no function
> uses that. Drop it at last.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 2 +-
>
The drm_exec tests where crashing[0] because of a null dereference. This
is caused by a new access of the `driver` attribute of `struct
drm_driver` on drm_gem_private_object_init(). Alloc the drm_device to
fix that.
[0]
[15:05:24] == drm_exec (6 subtests) ===
On 2023-07-27 17:45:38, Dmitry Baryshkov wrote:
> Please exuse me for the spam, I missed the triggered WARN_ON because of
> the dropped patch.
>
> Declaring the mask of supported interrupts proved to be error-prone. It
> is very easy to add a bit with no corresponding backing block or to miss
>
Because the gma_irq_install() is call after psb_gem_mm_init() function,
when psb_gem_mm_init() fails, the interrupt line haven't been allocated.
Yet the gma_irq_uninstall() is called in the psb_driver_unload() function
without checking if checking the irq is registered or not.
The calltrace is
> ...so that a per-plane logic in mtk_drm_plane can be easily added, because...
I think my concern is more that if we need to validate the format and
the modifier differently because of the plane data, then this method
would provide limited value. For example, on my MT8195, plane ID 38
supports
Le 27/07/2023 à 19:03, Yuanjun Gong a écrit :
in aspeed_gfx_load(), check the return value of clk_prepare_enable()
and return the error code if clk_prepare_enable() returns an
unexpected value.
Fixes: 4f2a8f5898ec ("drm: Add ASPEED GFX driver")
Signed-off-by: Yuanjun Gong
---
On Thu, Jul 27, 2023, at 18:45, Javier Martinez Canillas wrote:
> Arthur Grillo Queiroz Cabral writes:
>> On 27/07/23 13:07, Javier Martinez Canillas wrote:
>>> "Arnd Bergmann" writes:
Changing the local config should not be required after fixing
the Kconfig files.
>>>
>>>
Specify bpc value for the powertip_ph800480t013_idf02 panel to stop drm
code from complaining about unexpected bpc value (0).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
As talked about in the patch ("drm/panel: Add a way for other devices
to follow panel state"), we really want to keep the power states of a
touchscreen and the panel it's attached to in sync with each other. In
that spirit, add support to i2c-hid to be a panel follower. This will
let the i2c-hid
Turning on an i2c-hid device can be a slow process. This is why
i2c-hid devices use PROBE_PREFER_ASYNCHRONOUS. Unfortunately, when
we're a panel follower the i2c-hid power up sequence now blocks the
power on of the panel. Let's fix that by scheduling the work on the
system_wq.
Reviewed-by: Maxime
Let's provide the proper link from the touchscreen to the panel on
trogdor devices where the touchscreen support it. This allows the OS
to power sequence the touchscreen more properly.
For the most part, this is just expected to marginally improve power
consumption while the screen is off.
In a future patch we'd like to be able to call the current i2c-hid
suspend and resume functions from times other than system
suspend. Move the functions higher up in the file and have them take a
"struct i2c_hid" to make this simpler. We'll then add tiny wrappers of
the functions for use with
In the i2c-hid remove() function we currently try to power off,
depopulate our child device, and free our resources. That's OK, but...
* If the i2c-hid device is on a power rail that can't turn off (either
an always-on or a shared power rail) we won't try to put the device
in a low power
In a future patch, we want to change i2c-hid not to necessarily power
up the touchscreen during probe. In preparation for that, rearrange
the probe function so that we put as much stuff _before_ powering up
the device as possible.
This change is expected to have no functional effect.
As talked about in the patch ("drm/panel: Add a way for other devices
to follow panel state"), touchscreens that are connected to panels are
generally expected to be power sequenced together with the panel
they're attached to. Today, nothing provides information allowing you
to find out that a
The SYSTEM_SLEEP_PM_OPS() allows us to get rid of '#ifdef
CONFIG_PM_SLEEP', as talked about in commit 1a3c7bb08826 ("PM: core:
Add new *_PM_OPS macros, deprecate old ones").
This change is expected to have no functional effect.
Reviewed-by: Maxime Ripard
Signed-off-by: Douglas Anderson
---
Inform fw_devlink of the fact that a panel follower (like a
touchscreen) is effectively a consumer of the panel from the purposes
of fw_devlink.
NOTE: this patch isn't required for correctness but instead optimizes
probe order / helps avoid deferrals.
Acked-by: Rob Herring
Reviewed-by: Maxime
These days, it's fairly common to see panels that have touchscreens
attached to them. The panel and the touchscreen can somewhat be
thought of as totally separate devices and, historically, this is how
Linux has treated them. However, treating them as separate isn't
necessarily the best way to
The big motivation for this patch series is mostly described in the patch
("drm/panel: Add a way for other devices to follow panel state"), but to
quickly summarize here: for touchscreens that are connected to a panel we
need the ability to power sequence the two device together. This is not a
In a whole pile of panel drivers, we have code to make the
prepare/unprepare/enable/disable callbacks behave as no-ops if they've
already been called. It's silly to have this code duplicated
everywhere. Add it to the core instead so that we can eventually
delete it from all the drivers. Note: to
On 27/07/2023 12:54, Maarten Lankhorst wrote:
Hey,
On 2023-07-26 13:41, Tvrtko Ursulin wrote:
On 26/07/2023 11:14, Maarten Lankhorst wrote:
Hey,
On 2023-07-22 00:21, Tejun Heo wrote:
On Wed, Jul 12, 2023 at 12:46:04PM +0100, Tvrtko Ursulin wrote:
$ cat drm.memory.stat
card0
27 липня 2023 р. 19:50:35 GMT+03:00, Thierry Reding
написав(-ла):
>On Thu, Jul 27, 2023 at 07:26:28PM +0300, Svyatoslav Ryhel wrote:
>>
>>
>> 27 липня 2023 р. 18:11:15 GMT+03:00, Thierry Reding
>> написав(-ла):
>> >On Sun, Jun 18, 2023 at 11:50:46AM +0300, Svyatoslav Ryhel wrote:
>> >>
On Thu, Jul 27, 2023 at 07:24:56PM +0300, Svyatoslav Ryhel wrote:
>
>
> 27 липня 2023 р. 18:09:22 GMT+03:00, Thierry Reding
> написав(-ла):
> >On Sun, Jun 18, 2023 at 11:50:44AM +0300, Svyatoslav Ryhel wrote:
> >> This patch adds support for the bridge/connector attached to the
> >> HDMI
On Thu, Jul 27, 2023 at 07:26:28PM +0300, Svyatoslav Ryhel wrote:
>
>
> 27 липня 2023 р. 18:11:15 GMT+03:00, Thierry Reding
> написав(-ла):
> >On Sun, Jun 18, 2023 at 11:50:46AM +0300, Svyatoslav Ryhel wrote:
> >> All ASUS Transformers have micro-HDMI connector directly available.
> >> After
Arthur Grillo Queiroz Cabral writes:
Hello Arthur,
> On 27/07/23 13:07, Javier Martinez Canillas wrote:
>> "Arnd Bergmann" writes:
>>
[...]
>>> Changing the local config should not be required after fixing
>>> the Kconfig files.
>>>
>>
>> CONFIG_VT can only be disabled if CONFIG_EXPERT=y
On 27/07/23 05:33, Arnd Bergmann wrote:
> On Thu, Jul 27, 2023, at 00:03, Arthur Grillo wrote:
>> Using the `kunit_tool` with the command:
>>
>> tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/tests/
>>
>> Lead to this error[0]. Fix it by expliciting removing the
>>
On 27/07/2023 14:42, Maarten Lankhorst wrote:
On 2023-07-26 21:44, Tejun Heo wrote:
Hello,
On Wed, Jul 26, 2023 at 12:14:24PM +0200, Maarten Lankhorst wrote:
So, yeah, if you want to add memory controls, we better think
through how
the fd ownership migration should work.
I've taken a
Add checking the length of each data path before assigning drm private
data into all_drm_priv array.
Fixes: 1ef7ed48356c ("drm/mediatek: Modify mediatek-drm for mt8195 multi mmsys
support")
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 16 +---
1 file
To support DSI and eDP as main display connector without modifying
mtk-drm driver, we add the dynamic connector selection mechanism.
Change in v7:
1. separate 2 fixes patch from v6.
2. remove unnecessary null checking and variable.
3. move ddp_comp checking to crtc create.
Change in v6:
1.
1. Move output drm connector from each ddp_path array to connector array.
2. Add dynamic select available connector flow in crtc create and enable.
Signed-off-by: Nancy Lin
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
Add DSI as main display output for mt8188 vdosys0.
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
Add missing mmsys_dev_num to mt8188 vdosys0 driver data.
Fixes: 54b48080278a ("drm/mediatek: Add mediatek-drm of vdosys0 support for
mt8188")
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On 27/07/23 13:07, Javier Martinez Canillas wrote:
> "Arnd Bergmann" writes:
>
>> On Thu, Jul 27, 2023, at 00:03, Arthur Grillo wrote:
>>> Using the `kunit_tool` with the command:
>>>
>>> tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/tests/
>>>
>>> Lead to this error[0]. Fix
27 липня 2023 р. 18:11:15 GMT+03:00, Thierry Reding
написав(-ла):
>On Sun, Jun 18, 2023 at 11:50:46AM +0300, Svyatoslav Ryhel wrote:
>> All ASUS Transformers have micro-HDMI connector directly available.
>> After Tegra HDMI got bridge/connector support, we should use connector
>> framework
27 липня 2023 р. 18:09:22 GMT+03:00, Thierry Reding
написав(-ла):
>On Sun, Jun 18, 2023 at 11:50:44AM +0300, Svyatoslav Ryhel wrote:
>> This patch adds support for the bridge/connector attached to the
>> HDMI output, allowing to model the hardware properly. It keeps
>> backwards compatibility
As the INTF is fixed at the encoder creation time, we can move the
check whether INTF supports tearchck to dpu_encoder_phys_cmd_init().
This function can return an error if INTF doesn't have required feature.
Performing this check in dpu_encoder_phys_cmd_tearcheck_config() is less
useful, as this
Inline the _setup_intf_ops() function, it makes it easier to handle
different conditions involving INTF configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 47 +
1 file changed, 21 insertions(+), 26 deletions(-)
diff --git
The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however
only INTF_1 and INTF_2 actually support tearing control. Rather than
trying to fix the DPU_INTF_TE, check for the presense of the
corresponding interrupt line.
Signed-off-by: Dmitry Baryshkov
---
The dpu_encoder_phys_cmd_te_rd_ptr_irq() function uses neither hw_intf
nor hw_pp data, so we can drop the corresponding check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8
1 file changed, 8 deletions(-)
diff --git
Replace the only user of the DPU_INTF_TE feature flag with the direct
DPU version comparison.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 -
The DPU_PINGPONG_TE flag became unused, we can drop it now.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +---
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git
The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
Rather than checking for the flag, check for the presense of the
corresponding interrupt line.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +-
1 file changed, 1 insertion(+), 1
Drop two feature flags, DPU_INTF_TE and DPU_PINGPONG_TE, in favour of
performing the MDSS revision checks instead.
Dependencies: [1], [2]
[1] https://patchwork.freedesktop.org/series/118088/
[2] https://patchwork.freedesktop.org/series/118836/
Dmitry Baryshkov (7):
drm/msm/dpu: enable
On 7/18/23 18:44, Nathan Chancellor wrote:
Hi all,
A proposed update to clang's -Wconstant-logical-operand [1] to warn when
the left hand side is a constant as well now triggers with the modulo
expression in nsecs_to_jiffies_timeout() when NSEC_PER_SEC is not a
multiple of HZ, such as
"Arnd Bergmann" writes:
> On Thu, Jul 27, 2023, at 00:03, Arthur Grillo wrote:
>> Using the `kunit_tool` with the command:
>>
>> tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/tests/
>>
>> Lead to this error[0]. Fix it by expliciting removing the
>> CONFIG_DRM_FBDEV_EMULATION.
>>
Javier Martinez Canillas writes:
> Thomas Zimmermann writes:
>
> Hello Thomas,
>
>> Hi Javier
>>
>> Am 27.07.23 um 16:04 schrieb Javier Martinez Canillas:
>>> The commit 45b58669e532 ("drm/ssd130x: Allocate buffer in the plane's
>>> .atomic_check() callback") moved the buffers allocation to be
Am 27.07.23 um 17:16 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Hello Thomas,
Hi Javier
Am 27.07.23 um 16:04 schrieb Javier Martinez Canillas:
The commit 45b58669e532 ("drm/ssd130x: Allocate buffer in the plane's
.atomic_check() callback") moved the buffers allocation to
On 27/07/2023 18:24, Abhinav Kumar wrote:
On 7/27/2023 1:39 AM, Dmitry Baryshkov wrote:
On Thu, 27 Jul 2023 at 02:20, Abhinav Kumar
wrote:
On 5/21/2023 10:10 AM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and
UBWC
configuration.
On 7/27/2023 1:39 AM, Dmitry Baryshkov wrote:
On Thu, 27 Jul 2023 at 02:20, Abhinav Kumar wrote:
On 5/21/2023 10:10 AM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration.
Signed-off-by: Dmitry Baryshkov
---
From: Thierry Reding
On Wed, 26 Jul 2023 20:48:55 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> The HannStar HSD101PWW2 is an LVDS panel, so move it to the correct
> bindings file.
>
>
Applied, thanks!
[3/3] ARM: tegra: Use Hannstar HSD101PWW2 on Pegatron Chagall
commit:
From: Thierry Reding
On Wed, 26 Jul 2023 20:50:08 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> The Chunghwa CLAA070WP03XG is an LVDS panel, so move it to the correct
> bindings file.
>
>
Applied, thanks!
[3/3] ARM: tegra: Provide specific compatible string for Nexus 7 panel
Thomas Zimmermann writes:
Hello Thomas,
> Hi Javier
>
> Am 27.07.23 um 16:04 schrieb Javier Martinez Canillas:
>> The commit 45b58669e532 ("drm/ssd130x: Allocate buffer in the plane's
>> .atomic_check() callback") moved the buffers allocation to be done in
>> the primary plane's .atomic_check()
On Sun, Jun 18, 2023 at 11:50:46AM +0300, Svyatoslav Ryhel wrote:
> All ASUS Transformers have micro-HDMI connector directly available.
> After Tegra HDMI got bridge/connector support, we should use connector
> framework for proper HW description.
>
> Tested-by: Andreas Westman Dorcsak # ASUS TF
Thomas Zimmermann writes:
> Hi Maxime
>
> Am 27.07.23 um 16:33 schrieb Maxime Ripard:
>> Hi Thomas,
>>
>> On Wed, Jul 26, 2023 at 05:36:15PM +0200, Thomas Zimmermann wrote:
I've already sent a patch to use internally 24bit colors, when userspace
can use 32bit that would solve this
On Sun, Jun 18, 2023 at 11:50:44AM +0300, Svyatoslav Ryhel wrote:
> This patch adds support for the bridge/connector attached to the
> HDMI output, allowing to model the hardware properly. It keeps
> backwards compatibility with existing bindings and is required
> by devices which have a simple or
In order to simplify IRQ declarations, shift IRQ indices by 1. This
makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have
to explicitly set the 'no interrupt' fields in catalog structures.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4
In preparation to reworking the IRQ indices, move irq_tbl access to
separate helper.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 48 +--
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 12 +++--
2 files changed, 41 insertions(+), 19
In preparation of slighly changing IRQ numbering, move DPU_IRQ_REG()
macro to the dpu_hw_interrupts.h header. Also split the DPU_IRQ_MASK()
macro into local DPU_IRQ_MASK() and the global DPU_IRQ_OFFSET() macros.
Signed-off-by: Dmitry Baryshkov
---
There is no point in passing the IRQ index to IRQ callbacks, no function
uses that. Drop it at last.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
Having an explicit init of interrupt fields to -1 for not existing IRQs
makes it easier to forget and/or miss such initialisation, resulting in
a wrong interrupt definition.
Instead shift all IRQ indices to turn '0' to be the non-existing IRQ.
Dependencies: [1]
[1]
Hi Javier
Am 27.07.23 um 16:04 schrieb Javier Martinez Canillas:
The commit 45b58669e532 ("drm/ssd130x: Allocate buffer in the plane's
.atomic_check() callback") moved the buffers allocation to be done in
the primary plane's .atomic_check() callback.
But it missed that since the driver uses a
Hi Maxime
Am 27.07.23 um 16:33 schrieb Maxime Ripard:
Hi Thomas,
On Wed, Jul 26, 2023 at 05:36:15PM +0200, Thomas Zimmermann wrote:
I've already sent a patch to use internally 24bit colors, when userspace
can use 32bit that would solve this issue as well. In the end, on the
VGA link, 24 or 32
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, we can
refine the check in i915_gem_object_can_bypass_llc() to stop assuming any
user PAT can bypass the shared cache (if there is any).
Instead we can use the absence of I915_BO_CACHE_COHERENT_FOR_WRITE as the
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, we can
refine the check in use_cpu_reloc() to not reject the uncached PAT if it
was set by userspace.
Instead it can decide based on the presence of full coherency which
should be functionally equivalent on
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, and having
also special cased the Meteorlake snooping fully coherent mode, we can
remove the user PAT check from gpu_write_needs_clflush().
Signed-off-by: Tvrtko Ursulin
Cc: Fei Yang
Cc: Matt Roper
---
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, we can
refine the check in vm_fault_gtt() to not reject the uncached PAT if it
was set by userspace on a snoopable platform.
Signed-off-by: Tvrtko Ursulin
Cc: Fei Yang
Cc: Matt Roper
---
From: Tvrtko Ursulin
Commit 9275277d5324 ("drm/i915: use pat_index instead of cache_level") has
introduced PAT indices to i915 internal APIs, partially replacing the
usage of driver internal cache_level, but has also added a few sub-
optimal design decisions which this patch tries to improve
From: Tvrtko Ursulin
On Meteorlake CPU cache will not contain stale data after GPU access since
write-invalidate protocol is used, which means there is no need to flush
before potentially transitioning the buffer to a non-coherent domain.
Use the opportunity to documet the situation on discrete
From: Tvrtko Ursulin
No need to run extra instructions which will never trigger on platforms
before Meteorlake.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++
1 file changed, 26 insertions(+)
diff --git
From: Tvrtko Ursulin
Eliminate a bunch of runtime calls to i915_gem_get_pat_index() by caching
the interesting PAT indices in struct drm_i915_private. They are static
per platfrom so no need to consult a function every time.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
Cc: Fei Yang
---
From: Tvrtko Ursulin
Good news is that I realized series can be split after all. Bad news is that it
is still a lot to go through.
drm/i915: Skip clflush after GPU writes on Meteorlake
This is based on what Fei found out from hardware architects. If we agree the
the function this helper
On Thu, Jul 27, 2023 at 12:51 AM Konrad Dybcio wrote:
>
> On 27.07.2023 00:53, Rob Clark wrote:
> > On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> > wrote:
> >>
> >> On Thu, 27 Jul 2023 at 01:04, Rob Clark wrote:
> >>>
> >>> On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> >>> wrote:
>
The following changes since commit cd036d542afb82adfbbd43c5dbeb7010e8e91ee7:
drm/msm/a6xx: Add A610 speedbin support (2023-06-18 11:35:27 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/drm/msm.git tags/drm-msm-fixes-2023-07-27
for you to fetch changes up to
On Thu, Jul 27, 2023, at 16:07, Javier Martinez Canillas wrote:
> Arnd Bergmann writes:
>
> Hello Arnd,
>
> Thanks a lot for your patch.
>
>> From: Arnd Bergmann
>>
>> It is not possible for ssd130x_primary_plane_funcs to use both
>> its own reset/duplicate/destroy callbacks and the ones from
>>
Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this with looping over the enabled INTF blocks
to setup the irq mask.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry
Inline __intr_offset(), there is no point in having a separate oneline
function for setting base block address.
Reviewed-by: Neil Armstrong
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +---
1 file changed, 1
Now as the list of the interrupts is constructed from the catalog
data, drop the mdss_irqs field from catalog.
Reviewed-by: Neil Armstrong
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Reviewed-by: Neil Armstrong
Reviewed-by: Marijn Suijten
Fixes: c7314613226a0 ("drm/msm: Add missing struct identifier")
While reworking interrupts masks, it was easier to keep old
MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
to drop them and use unified symbol names.
Reviewed-by: Neil Armstrong
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
Please exuse me for the spam, I missed the triggered WARN_ON because of
the dropped patch.
Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this static configuration with the
Hi Maira,
On Thu, Jul 27, 2023 at 11:01:27AM -0300, Maira Canal wrote:
> Hi Nathan,
>
> On 7/18/23 18:44, Nathan Chancellor wrote:
> > A proposed update to clang's -Wconstant-logical-operand to warn when the
> > left hand side is a constant shows the following instance in
> >
Hi Thomas,
On Wed, Jul 26, 2023 at 05:36:15PM +0200, Thomas Zimmermann wrote:
> > I've already sent a patch to use internally 24bit colors, when userspace
> > can use 32bit that would solve this issue as well. In the end, on the
> > VGA link, 24 or 32 bit colors are the same. That would allow
The previous patch exposed the accumulated amount of active time per
client for each V3D queue. But this doesn't provide a global notion of
the GPU usage.
Therefore, provide the accumulated amount of active time for each V3D
queue (BIN, RENDER, CSD, TFU and CACHE_CLEAN), considering all the jobs
This patch exposes the accumulated amount of active time per client
through the fdinfo infrastructure. The amount of active time is exposed
for each V3D queue: BIN, RENDER, CSD, TFU and CACHE_CLEAN.
In order to calculate the amount of active time per client, a CPU clock
is used through the
This patchset exposes GPU usages stats both globally and per-file
descriptor.
The first patch exposes the accumulated amount of active time per client
through the fdinfo infrastructure. The amount of active time is exposed
for each V3D queue. Moreover, it exposes the number of jobs submitted to
On 2023-07-27 16:34:49, Dmitry Baryshkov wrote:
> On 27/07/2023 15:22, Dmitry Baryshkov wrote:
> >
> > On Sun, 23 Jul 2023 18:08:38 +0200, Marijn Suijten wrote:
> >> Bring up the SM6125 DPU now that all preliminary series (such as INTF
> >> TE) have been merged (for me to test the hardware
Arnd Bergmann writes:
Hello Arnd,
Thanks a lot for your patch.
> From: Arnd Bergmann
>
> It is not possible for ssd130x_primary_plane_funcs to use both
> its own reset/duplicate/destroy callbacks and the ones from
> DRM_GEM_SHADOW_PLANE_FUNCS:
>
> In file included from
The commit 45b58669e532 ("drm/ssd130x: Allocate buffer in the plane's
.atomic_check() callback") moved the buffers allocation to be done in
the primary plane's .atomic_check() callback.
But it missed that since the driver uses a shadow-buffered plane, the
Hi Nathan,
On 7/18/23 18:44, Nathan Chancellor wrote:
A proposed update to clang's -Wconstant-logical-operand to warn when the
left hand side is a constant shows the following instance in
nsecs_to_jiffies_timeout() when NSEC_PER_SEC is not a multiple of HZ,
such as CONFIG_HZ=300:
In file
Thomas Zimmermann writes:
Hello Thomas,
Thanks a lot for the feedback!
> Hi Javier,
>
> this patch is completely broken. It's easy to fix though.
>
> Am 21.07.23 um 09:09 schrieb Javier Martinez Canillas:
[...]
>> +struct ssd130x_plane_state {
>> +struct drm_plane_state base;
>
> You
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