Hi Krzysztof,
On Tue, 2023-09-12 at 10:19 +0200, Krzysztof Kozlowski wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 12/09/2023 09:56, Moudy Ho wrote:
> > Introduce more MDP3 components present in MT8195.
The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
programmable switching frequency to optimize efficiency.
The brightness can be controlled either by I2C commands (called "analog"
mode) or by a PWM input signal (PWM mode).
This driver supports both modes.
For DT
On Tue, 2023-09-12 at 10:23 +0200, Krzysztof Kozlowski wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 12/09/2023 09:57, Moudy Ho wrote:
> > Add device nodes for Media Data Path 3 (MDP3) modules.
> >
> >
Some components act as bridges only and do not require full configuration.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 8 +++
.../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 1 +
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 58 ++-
3 files
Introduce more MDP3 components present in MT8195.
Signed-off-by: Moudy Ho
---
.../display/mediatek/mediatek,aal.yaml| 2 +-
.../display/mediatek/mediatek,color.yaml | 2 +-
.../display/mediatek/mediatek,merge.yaml | 1 +
.../display/mediatek/mediatek,ovl.yaml| 2 +-
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
to zero decimal places.
The vendor's FW GMU is called a618_gmu.bin. And also a618 on SM7150 uses
a615 zapfw.
Add this as machine = "qcom,sm7150", because
MT8195 has two MMSYS sets, VPPSYS0 and VPPSYS1.
These sets coordinate and control the clock, power, and
register settings needed for the components of MDP3.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 44 +--
Extend the component settings used in MT8195 MDP3.
Additionally, it is crucial to read all component settings in
a specific manner to ensure that shared memory data structure lengths
are aligned across different platforms.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c
Increasing the number of sets built by MMSYS and MUTEX in MT8195
will enable the creation of more pipelines in MDP3.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 80 ---
.../platform/mediatek/mdp3/mtk-mdp3-core.h| 7 ++
2 files changed, 60
In some chips, MDP3 has the ability to utilize two pipelines to
parallelly process a single frame.
To enable this feature, multiple CMDQ clients and packets need to
be configured at the same time.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 8 +
On Tue, Sep 12, 2023 at 08:55:31AM +0200, Krzysztof Kozlowski wrote:
> On 11/09/2023 18:47, John Watts wrote:
> > On Mon, Sep 11, 2023 at 01:49:39PM +0200, Krzysztof Kozlowski wrote:
> >> If the other panel has exactly the same case, then yes, you can do like
> >> this. But it depends on the
Hi Angelo,
On Tue, 2023-09-12 at 11:18 +0200, AngeloGioacchino Del Regno wrote:
> Il 12/09/23 09:57, Moudy Ho ha scritto:
> > MT8195 has two MMSYS sets, VPPSYS0 and VPPSYS1.
> > These sets coordinate and control the clock, power, and
> > register settings needed for the components of MDP3.
> >
>
Due to the same hardware design, MDP RDMA needs to
be integrated into the same binding.
Signed-off-by: Moudy Ho
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 88 ---
.../bindings/media/mediatek,mdp3-rdma.yaml| 5 +-
2 files changed, 3 insertions(+), 90 deletions(-)
Changes since v4:
- Rebase on v6.6-rc1
- Organize identical hardware components into their respective files.
Hi,
The purpose of this patch is to separate the MDP3-related bindings from
the original mailing list mentioned below:
Add configuration of more components in MT8195 MDP3.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mdp_reg_aal.h | 25 ++
.../platform/mediatek/mdp3/mdp_reg_color.h| 31 +++
.../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 +
On Tue, 2023-09-12 at 10:16 +0200, Krzysztof Kozlowski wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 12/09/2023 09:56, Moudy Ho wrote:
> > Due to the same hardware design, MDP RDMA needs to
> > be
---
drivers/staging/fbtft/fb_ra8875.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/fbtft/fb_ra8875.c
b/drivers/staging/fbtft/fb_ra8875.c
index 398bdbf53c9a..658f915b8528 100644
--- a/drivers/staging/fbtft/fb_ra8875.c
+++
On 2023-09-14 15:00, Maxime Ripard wrote:
On Wed, Sep 13, 2023 at 07:35:57PM +0300, José Pekkarinen wrote:
On 2023-09-13 17:41, mrip...@kernel.org wrote:
> On Wed, Sep 13, 2023 at 05:01:40PM +0300, José Pekkarinen wrote:
> > On 2023-09-13 12:50, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On
Changes since v4:
- Rebase on v6.6-rc1
- Remove any unnecessary DTS settings.
- Adjust the usage of MOD and clock in blending components.
Changes since v3:
- Depend on :
[1] https://patchwork.kernel.org/project/linux-media/list/?series=719841
- Suggested by Krzysztof, integrating all newly
Hi
Am 12.09.23 um 22:22 schrieb Janne Grunau via B4 Relay:
From: Janne Grunau
Multiple power domains need to be handled explicitly in each driver. The
driver core can not handle it automatically since it is not aware of
power sequencing requirements the hardware might have. This is not a
On Sat, Sep 16, 2023 at 05:32:42PM +0300, Dan Carpenter wrote:
> On Fri, Sep 08, 2023 at 09:59:40PM +0200, Philipp Stanner wrote:
...
> > +static inline void *memdup_array_user(const void __user *src, size_t n,
> > size_t size)
> > +{
> > + size_t nbytes;
> > +
> > + if
Hi
Am 14.09.23 um 21:51 schrieb Javier Martinez Canillas:
The driver uses a naming convention where functions for struct drm_*_funcs
callbacks are named ssd130x_$object_$operation, while the callbacks for
struct drm_*_helper_funcs are named ssd130x_$object_helper_$operation.
The idea is that
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