On Thu, Apr 24, 2025 at 09:08:49AM GMT, Jianeng Ceng wrote:
> Ponyta is a custom label Chromebook based on MT8186. It is a
> self-developed project of Huaqin and has no fixed OEM.
>
> Signed-off-by: Jianeng Ceng
> ---
Acked-by: Krzysztof Kozlowski
---
This is an automated instruction, just i
MEI GSC interrupt comes from i915. It has top half and bottom half.
Top half is called from i915 interrupt handler. It should be in
irq disabled context.
With RT kernel, by default i915 IRQ handler is in threaded IRQ. MEI GSC
top half might be in threaded IRQ context. In this case, local IRQ
shoul
Marcus Folkesson writes:
> Hello Javier,
>
> On Tue, Apr 08, 2025 at 12:44:46PM +0200, Javier Martinez Canillas wrote:
>> Marcus Folkesson writes:
>>
>> Hello Marcus,
>>
>> > Sitronix ST7571 is a 4bit gray scale dot matrix LCD controller.
>> > The controller has a SPI, I2C and 8bit parallel in
Hello Javier,
On Tue, Apr 08, 2025 at 12:44:46PM +0200, Javier Martinez Canillas wrote:
> Marcus Folkesson writes:
>
> Hello Marcus,
>
> > Sitronix ST7571 is a 4bit gray scale dot matrix LCD controller.
> > The controller has a SPI, I2C and 8bit parallel interface, this
> > driver is for the I2
The anx7625_link_bridge() checks if a device is not a panel
bridge and add DRM_BRIDGE_OP_HPD and DRM_BRIDGE_OP_DETECT
flags to the drm_bridge->ops. However, on port 1 of the anx7625
bridge, any device added is always treated as a panel bridge,
preventing connector_detect() from being called. To res
Add device tree nodes for the DSI0 and DSI1 controllers
with their corresponding PHYs found on Qualcomm SA8775P SoC.
Signed-off-by: Ayushi Makhija
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 186 +-
1 file changed
Hi Maíra,
On Wed, Apr 23, 2025 at 4:22 PM Maíra Canal wrote:
>
> Hi Jagath,
>
> On 21/04/25 05:59, Jagath Jog J wrote:
> > This patch updates the MIPI DBI driver to use drm_device.debugfs_root
> > instead of drm_minor for creating debugfs files. The debugfs setup is now
> > done earlier in probe(
Document the DSI CTRL on the SA8775P Platform.
Signed-off-by: Ayushi Makhija
Reviewed-by: Krzysztof Kozlowski
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml| 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-m
Add DSI Controller v2.5.1 support for SA8775P SoC.
Signed-off-by: Ayushi Makhija
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 18 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg
This series enables the support for DSI to DP bridge ports
(labled as DSI0 and DSI1) of the Qualcomm's SA8775P Ride platform.
SA8775P SoC has DSI controller v2.5.1 and DSI PHY v4.2.
The Ride platform is having ANX7625 DSI to DP bridge chip from Analogix.
---
This patch depends on following series
Document the DSI PHY on the SA8775P Platform.
Signed-off-by: Ayushi Makhija
Acked-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
b/Docu
Document DSI controller and phy on SA8775P platform.
Signed-off-by: Ayushi Makhija
Reviewed-by: Krzysztof Kozlowski
---
.../display/msm/qcom,sa8775p-mdss.yaml| 181 +-
1 file changed, 180 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/displ
Use gpiod_set_value_cansleep() instead of gpiod_set_value()
to fix the below call trace in the boot log:
[5.690534] Call trace:
[5.690536] gpiod_set_value+0x40/0xa4
[5.690540] anx7625_runtime_pm_resume+0xa0/0x324 [anx7625]
[5.690545] __rpm_callback+0x48/0x1d8
[5.690549] rpm
The SA8775P SoC uses the 5nm (v4.2) DSI PHY driver with
different enable regulator load.
Signed-off-by: Ayushi Makhija
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
When the device enters the suspend state, it prevents
HPD interrupts from occurring. To address this, implement
.hpd_enable() and .hpd_disable() callbacks functions of
the drm_bridge.
Signed-off-by: Ayushi Makhija
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 18
Add anx7625 DSI to DP bridge device nodes.
Signed-off-by: Ayushi Makhija
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 181 +
1 file changed, 181 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
index 175f
In the anx7625_sink_detect(), the device is checked to see
if it is a panel bridge, and it always sends a "connected"
status to the connector. When adding the DP port on port 1 of the
anx7625, it incorrectly treats it as a panel bridge and sends an
always "connected" status. Instead of checking the
On Wed, Apr 23, 2025 at 03:12:27PM +0200, Christian König wrote:
> On 4/18/25 18:42, Tvrtko Ursulin wrote:
> > Hi all,
> >
> > Recently I mentioned to Danilo about some fence lifetime issues so here is a
> > rough series, more than anything intended to start the discussion.
> >
> > Most of the pr
Hello,
I'm new to DRM development and ran into something in the Panfrost (but also
Panthor) driver I'm curious about.
In drivers/gpu/drm/panfrost/panfrost_gem.c, there's this line: obj->base.map_wc
= !pfdev->coherent;
>From what I can tell, this means when the CPU isn't coherent, it uses
>writ
[Public]
Sorry for spamming.
Please ignore this patch set. I misread the code flow here a bit. Will refine
another version later if needed.
Thanks!
Regards,
Wayne
> -Original Message-
> From: Wayne Lin
> Sent: Thursday, April 24, 2025 11:08 AM
> To: dri-devel@lists.freedesktop.org
> C
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MIXER_COMBINED_ALPHA feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cat
Ponyta is a custom label Chromebook based on MT8186. It is a
self-developed project of Huaqin and has no fixed OEM.
Signed-off-by: Jianeng Ceng
---
Changes in v11:
- PATCH 1/2: Remove redundant items.
- Link to
v10:https://lore.kernel.org/all/20250423093647.4074135-2-cengjian...@huaqin.corp-part
Hi Helen,
On 24/04/25 00:26, Helen Koike wrote:
On 17/04/2025 00:04, Vignesh Raman wrote:
Add jobs to run dt_binding_check and dtbs_check. If warnings are seen,
exit with a non-zero error code while configuring them as warning in
the GitLab CI pipeline.
Signed-off-by: Vignesh Raman
Reviewed
On Wed, April 23, 2025 7:15 PM Brost, Matthew wrote:
> On Wed, Apr 23, 2025 at 07:57:10PM -0600, Lin, Shuicheng wrote:
> > On Wed, April 23, 2025 1:19 PM Cavitt, Jonathan wrote:
> > > Add initial declarations for the drm_xe_vm_get_property ioctl.
> > >
> > > v2:
> > > - Expand kernel docs for drm_x
On Wed, April 23, 2025 1:19 PM Cavitt, Jonathan wrote:
> Add support for userspace to request a list of observed faults from a
> specified
> VM.
>
> v2:
> - Only allow querying of failed pagefaults (Matt Brost)
>
> v3:
> - Remove unnecessary size parameter from helper function, as it
> is a pr
Hi Helen,
On 24/04/25 00:21, Helen Koike wrote:
Hi Vignesh,
Thanks for this version, please see my comments below.
On 17/04/2025 00:04, Vignesh Raman wrote:
Add jobs to validate devicetrees and run KUnit tests.
Pipeline link,
https://gitlab.freedesktop.org/vigneshraman/linux/-/pipelines/1407
On Wed, April 23, 2025 1:19 PM Cavitt, Jonathan wrote:
> Add additional information to each VM so they can report up to the first
> 50 seen faults. Only pagefaults are saved this way currently, though in the
> future, all faults should be tracked by the VM for future reporting.
>
> Additionally,
The memory allocated by msm_fence_alloc() actually is the
container of msm_fence_alloc()'s return value. Thus, just
free its return value is not enough.
Add a helper 'msm_fence_free()' in msm_fence.h/msm_fence.c
to do the complete job.
Fixes: f94e6a51e17c ("drm/msm: Pre-allocate hw_fence")
Cc: sta
Add check for the return value of alloc_ordered_workqueue()
in xe_gt_alloc() to catch potential exception.
Fixes: e2d84e5b2205 ("drm/xe: Mark GT work queue with WQ_MEM_RECLAIM")
Cc: sta...@vger.kernel.org
Signed-off-by: Haoxiang Li
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/xe/xe_gt.c | 2
[Why]
There is no handling for I2C-read-over-AUX when receive reply of
I2C_ACK|AUX_ACK followed by the total number of data bytes Fewer
than LEN + 1
[How]
Refer to DP v2.1: 2.11.7.1.6.3 & 2.11.7.1.6.4, repeat the identical
I2C-read-over-AUX transaction with the updated LEN value equal to
the origi
These two patches are trying to fix how we handle I2C-Over_AUX
transactions when sink side can only complte partial data at one time.
We encounter EDID reading error with specific monitor and cause mode
list can only be lower resolutions. After analysis, the monitor will
reply I2C_ACK|AUX_ACK foll
[Why]
Notice few problems under I2C-write-over-Aux with
Write_Status_Update_Request flag set cases:
- I2C-write-over-Aux request with
Write_Status_Update_Request flag set won't get sent
upon the reply of I2C_ACK|AUX_ACK followed by “M”
Value. Now just set the flag but won't send out
- The I
Continue migration to the MDSS-revision based checks and replace
DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/c
From: Dmitry Baryshkov
Inline the _setup_mixer_ops() function, it makes it easier to handle
different conditions involving LM configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 24 +---
1 file changed, 9 insertions(+), 15 deletion
From: Dmitry Baryshkov
Continue cleanup of the feature flags and replace the last remaining CTL
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 +++---
drivers/
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/cat
On April 24, 2025, 1:18 a.m. UTC
Alexandre Courbot wrote:
> Since this just renames fields, would you be ok if I squashed this one
> into the relevant patch of my series, alongside a
>
> [joelagn...@nvidia.com: give better names to FalconAppifHdrV1's fields]
>
> ?
Yes, sounds good to me. Thanks
Add check for the return value of alloc_ordered_workqueue()
and alloc_workqueue(). Furthermore, if some allocations fail,
cleanup works are added to avoid potential memory leak problem.
Fixes: 40053823baad ("drm/i915/display: move modeset probe/remove functions to
intel_display_driver.c")
Cc: sta
Add check for the return value of alloc_ordered_workqueue()
in xe_display_create() to catch potential exception.
Fixes: 44e694958b95 ("drm/xe/display: Implement display support")
Cc: sta...@vger.kernel.org
Signed-off-by: Haoxiang Li
---
drivers/gpu/drm/xe/display/xe_display.c | 2 ++
1 file chan
On Wed, Apr 23, 2025 at 07:57:10PM -0600, Lin, Shuicheng wrote:
> On Wed, April 23, 2025 1:19 PM Cavitt, Jonathan wrote:
> > Add initial declarations for the drm_xe_vm_get_property ioctl.
> >
> > v2:
> > - Expand kernel docs for drm_xe_vm_get_property (Jianxun)
> >
> > v3:
> > - Remove address ty
This change is essentially a Panfrost port of commit a3707f53eb3f
("drm/panthor: show device-wide list of DRM GEM objects over DebugFS").
The DebugFS file is almost the same as in Panthor, minus the GEM object
usage flags, since Panfrost has no kernel-only BO's.
Two additional GEM state flags whi
This patch series is a Panfrost port of the already merged patches
previously discussed at [1].
The differences are minimal. However, Panfrost doesn't have Kernel-only BO's,
so all the
functionality that dealt with them has been removed.
The under-discussion Mesa MR that would allow one to test
Allow UM to label a BO for which it possesses a DRM handle.
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 44 -
drivers/gpu/drm/panfrost/panfrost_gem.h | 2 ++
include/uapi/drm/panfrost_drm.h | 20 +++
3 files changed, 65 ins
Unlike in Panthor, from where this change is based on, there is no need
to support tagging of BO's other than UM-exposed ones, so all strings
can be freed with kfree().
This commit is done in preparation of a following one that will allow
UM to set BO labels through a new ioctl().
Signed-off-by:
On Wed, 23 Apr 2025 19:31:36 +0300, Andy Shevchenko wrote:
> On Wed, Apr 23, 2025 at 06:30:48PM +0900, Akira Yokosawa wrote:
>> On Tue, 22 Apr 2025 10:57:33 +0300, Andy Shevchenko wrote:
>>> On Mon, Apr 21, 2025 at 10:35:29AM -0600, Jonathan Corbet wrote:
Dmitry Baryshkov writes:
>
> [...]
>
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
LVDS support in MDP4 driver makes use of drm_connector directly. However
LCDC encoder and LVDS connector are wrappers around drm_panel. Switch
them to use drm_panel_bridge/drm_bridge_connector. This allows using
standard interface for the drm_panel
On Wed, April 23, 2025 1:19 PM Cavitt, Jonathan wrote:
> Add initial declarations for the drm_xe_vm_get_property ioctl.
>
> v2:
> - Expand kernel docs for drm_xe_vm_get_property (Jianxun)
>
> v3:
> - Remove address type external definitions (Jianxun)
> - Add fault type to xe_drm_fault struct (Jia
Thanks a lot for doing this, this was severely missing from the
WPR2 patchset.
Due to the strong focus on documentation, and in order to ease merging,
I think it makes sense to keep this separate from the WPR2 patchset and
merge it on top of it. Danilo, would that work for you?
On Thu Apr 24, 202
This is v11 of the MT8186 Chromebook device tree series.
---
Changes in v11:
- PATCH 1/2: Remove redundant items.
- Link to
v10:https://lore.kernel.org/all/20250423093647.4074135-2-cengjian...@huaqin.corp-partner.google.com/
Changes in v10:
- PATCH 1/2: Add enum for ponyta sku.
- Link to
v9:http
Since this just renames fields, would you be ok if I squashed this one
into the relevant patch of my series, alongside a
[joelagn...@nvidia.com: give better names to FalconAppifHdrV1's fields]
?
On Thu Apr 24, 2025 at 7:54 AM JST, Joel Fernandes wrote:
> Signed-off-by: Joel Fernandes
> ---
> d
MT8186 ponyta, known as huaqin custom label, is a
MT8186 based laptop. It is based on the "corsola" design.
It includes LTE, touchpad combinations.
Reviewed-by: Matthias Brugger
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Jianeng Ceng
---
Changes since v10:
- No change.
Changes in
Hi,
At 2025-04-24 01:18:45, "Dmitry Baryshkov"
wrote:
>On Wed, Apr 23, 2025 at 06:44:16PM +0200, Arnd Bergmann wrote:
>> From: Arnd Bergmann
>>
>> DRM_DISPLAY_DP_AUX_BUS cannot be selected when CONFIG_OF is disabled:
>>
>> WARNING: unmet direct dependencies detected for DRM_DISPLAY_DP_AUX_BU
Em Mon, 21 Apr 2025 10:35:29 -0600
Jonathan Corbet escreveu:
> Dmitry Baryshkov writes:
>
> > On Wed, Apr 16, 2025 at 03:51:03PM +0800, Mauro Carvalho Chehab wrote:
> >>
> >> As reported by Andy, the Kernel build system runs kernel-doc script for
> >> DRM,
> >> when W=1. Due to Python's nor
As reported by Andy, kernel-doc.py is creating a __pycache__
directory at build time.
Disable creation of __pycache__ for the libraries used by
kernel-doc.py, when excecuted via the build system or via
scripts/find-unused-docs.sh.
Reported-by: Andy Shevchenko
Closes: https://lore.kernel.org/linu
As reported by Andy, the Kernel build system runs kernel-doc script for DRM,
when W=1. Due to Python's normal behavior, its JIT compiler will create
a bytecode and store it under scripts/lib/*/__pycache__. As one may be using
O= and even having the sources on a read-only mount point, disable its
c
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
The LVDS/LCDC controller uses pixel clock coming from the multimedia
controller (mmcc) rather than using the PLL directly. Stop using LVDS
PLL directly and register it as a clock provider. Use lcdc_clk as a
pixel clock for the LCDC.
Reviewed-by: K
sysmembar is a critical operation that the GSP falcon needs to perform
in the reset sequence. Add some code comments to clarify.
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/gpu.rs | 11 ++-
drivers/gpu/nova-core/regs.rs | 2 ++
2 files changed, 12 insertions(+), 1 deletion(
From: Dmitry Baryshkov
Continue cleanup of the feature flags and replace the last remaining LM
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++--
dri
On 4/23/2025 7:12 PM, Timur Tabi wrote:
> On Wed, 2025-04-23 at 18:53 -0400, Joel Fernandes wrote:
>> +This document describes the layout of the VBIOS image which is a series of
>> concatenated
>> +images in the ROM of the GPU. The VBIOS is mirrored onto the BAR 0 space
>> and is read
>> +by b
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
We can check the LCDC clock directly from the LCDC encoder driver, so
remove it from the LVDS connector.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 1 -
drivers/gpu/drm
The page fault handler should reject write/atomic access to read only
VMAs. Add code to handle this in handle_pagefault after the VMA lookup.
Fixes: 3d420e9fa848 ("drm/xe: Rework GPU page fault handling")
Signed-off-by: Jonathan Cavitt
Suggested-by: Matthew Brost
Reviewed-by: Shuicheng Lin
---
On Wed, 2025-04-23 at 18:53 -0400, Joel Fernandes wrote:
> +This document describes the layout of the VBIOS image which is a series of
> concatenated
> +images in the ROM of the GPU. The VBIOS is mirrored onto the BAR 0 space and
> is read
> +by both Boot ROM firmware (also known as IFR or init-f
Hello,
Please find in this series, several clarifications, diagrams and code comments
for various things in the nova-core driver. These are essential to develop an
understanding how nova-core's boot initialization works and aid in development.
These patches are on top of Alex's last posting for GS
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/firmware/fwsec.rs | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs
b/drivers/gpu/nova-core/firmware/fwsec.rs
index 664319d1d31c..79c21db9d89d 100644
--- a/drivers
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
Instead of using .parent_names, use .parent_data, which binds parent
clocks by using relative names specified in DT in addition to using global
system clock names.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.
Add explanation of fwsec with diagrams. This helps clarify how the
nova-core falcon boot works.
Signed-off-by: Joel Fernandes
---
Documentation/gpu/nova/core/fwsec.rst | 173 ++
Documentation/gpu/nova/core/vbios.rst | 3 +-
Documentation/gpu/nova/index.rst | 1 +
devinit is mentioned in the code. This patch explains it so it is clear
what it does. devinit is not only essential at boot-time, but also at
runtime due to suspend-resume and things like re-clocking.
Signed-off-by: Joel Fernandes
---
Documentation/gpu/nova/core/devinit.rst | 54
Add detailed explanation and block diagrams of the layout of the vBIOS
on Nvidia GPUs. This is important to understand how nova-core boots an
Nvidia GPU.
Signed-off-by: Joel Fernandes
---
Documentation/gpu/nova/core/vbios.rst | 154 ++
1 file changed, 154 insertions(+)
c
Add several code comments to reduce acronym soup and explain how devinit magic
and bootflow works before driver loads. These are essential for debug and
development of the nova driver.
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/devinit.rs | 36
drive
On Mon, Apr 21, 2025 at 10:18:24PM +0200, Barnabás Czémán wrote:
> From: Daniil Titov
>
> Modify existing MSM8917 driver to support MSM8937 SoC. Override frequencies
> which are different in this chip. Register all the clocks to the framework
> for the clients to be able to request for them. Add
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
Drop the !COMMON_CLK stub for mpd4_lvds_pll_init(), the DRM_MSM driver
depends on COMMON_CLK.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 7 ---
1 file changed, 7 deletions(-)
On 2/26/2025 6:31 PM, Dmitry Baryshkov wrote:
Since SmartDMA planes provide two rectangles, it is possible to use them
to drive two different DRM planes, first plane getting the rect_0,
another one using rect_1 of the same SSPP. The sharing algorithm is
pretty simple, it requires that each of
From: Dave Airlie
This just adds the memcg init and account_op support.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 1 +
drivers/gpu/drm/nouveau/nouveau_gem.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/d
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++---
From: Dave Airlie
In order for modular GPU memory mgmt TTM to adjust the GPU
statistic we need to export the stat change functionality.
Signed-off-by: Dave Airlie
---
mm/memcontrol.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 25471a0fd0be..68b23
Hey,
I've been tasked to look into this, and I'm going start from hopeless
naivety and see how far I can get. This is an initial attempt to hook
TTM system memory allocations into memcg and account for them.
It does:
1. Adds memcg GPU statistic,
2. Adds TTM memcg pointer for drivers to set on the
From: Dave Airlie
This adds the memcg object for any user allocated object,
and adds account_op to necessary paths which might populate
a tt object.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 2 ++
drive
From: Dave Airlie
Doing proper integration of TTM system memory allocations with
memcg is a difficult ask, primarily due to difficulties around
accounting for evictions properly.
However there are systems where userspace will be allocating
objects in system memory and they won't be prone to migr
From: Dave Airlie
Discrete and Integrated GPUs can use system RAM instead of
VRAM for all or some allocations. These allocations happen
via drm/ttm subsystem and are currently not accounted for
in cgroups.
Add a gpu statistic to allow a place to visualise allocations
once they are supported.
Si
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalo
From: Dmitry Baryshkov
The DPU_PINGPONG_TE2 is unused by the current code (and can further be
replaced by the checking for the te2 sblk presense). Other feature bits
are completely unused. Drop them from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/ca
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu1
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cat
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/g
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++--
drivers/
From: Dmitry Baryshkov
Continue cleanup of the feature flags and replace the last remaining LM
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8
drivers
From: Dmitry Baryshkov
Inline the _setup_ctl_ops() function, it makes it easier to handle
different conditions involving CTL configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 98 ++
1 file changed, 47 insertions(+), 51 d
From: Dmitry Baryshkov
Drop unused MDP TOP features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/
From: Dmitry Baryshkov
Only SSPP, WB and VBIF still have feature bits remaining, all other
hardware blocks don't have feature bits anymore. Remove the 'features'
from the DPU_HW_BLK_INFO so that it doesn't get included into hw info
structures by default and only include it when necessary.
Signed
From: Dmitry Baryshkov
Drop unused LM features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DITHER feature bit with the core_major_ver >= 3 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 8 ||
core_major_ver == 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
drivers/gpu/drm
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and drop the
DPU_DIM_LAYER feature bit. It is currently unused, but can be replaed
with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4
drivers/gpu/drm/msm/disp/dpu1/cata
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DSC feature bit with the core_major_ver < 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dp
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/m
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++--
drive
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/d
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