On 19-06-2025 02:49, Daniele Ceraolo Spurio wrote:
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Introduce a debug filesystem node to disable late binding fw reload
during the system or runtime resume. This is intended for situations
where the late binding fw needs to be loaded from user mode.
Hi
Am 18.06.25 um 20:45 schrieb Mario Limonciello:
On 6/18/2025 9:12 AM, Simona Vetter wrote:
On Wed, Jun 18, 2025 at 11:11:26AM +0200, Thomas Zimmermann wrote:
Hi
Am 17.06.25 um 22:22 schrieb Mario Limonciello:
On 6/17/25 2:22 PM, Alex Williamson wrote:
On Tue, 17 Jun 2025 12:59:10 -0500
From: Andy Yan
Enable the Mini DisplayPort on this board.
Note that ROCKCHIP_VOP2_EP_DP0 is defined as 10 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address error,
expected "a"" if we use it directly after endpoint, so we use "a"
instead here.
Signed-off-by: An
From: Andy Yan
The DP1 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY1 with USB 3.1
HOST1 controller.
Signed-off-by: Andy Yan
---
(no changes since v1)
.../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 +++
1 file changed, 30 inser
From: Andy Yan
The RA620 is an active DP to HDMI converter chip, basically
no software is involved to drive it.
Add it to simple bridge to make it can be find by the drm bridge chain.
Signed-off-by: Andy Yan
Reviewed-by: Dmitry Baryshkov
---
(no changes since v3)
Changes in v3:
- First int
On 19/06/2025 08:37, Ryosuke Yasuoka wrote:
On Thu, Jun 19, 2025 at 3:12 PM Jocelyn Falempe wrote:
On 13/06/2025 15:20, Ryosuke Yasuoka wrote:
Add drm_panic moudle for bochs drm so that panic screen can be displayed
on panic.
Thanks for the patch, it's simple and looks good to me.
Reviewed
From: Andy Yan
Add driver extension for Synopsys DesignWare DPTX IP used
on Rockchip RK3588 SoC.
Signed-off-by: Andy Yan
Acked-by: Dmitry Baryshkov
Tested-by: Nicolas Frattaroli
---
Changes in v4:
- Drop unused function
- Add platform_set_drvdata
Changes in v2:
- no include uapi path
- swi
From: Andy Yan
The HDMI0(Port next to Headphone Jack) is drived by DP1 on rk3588
via RA620(a dp2hdmi converter).
Add related dt nodes to enable it.
Note: ROCKCHIP_VOP2_EP_DP1 is defined as 11 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address
error, expected "
From: Andy Yan
The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX
controller. And this DPTX controller need share a USBDP PHY with
the USB 3.0 OTG controller during operation.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(no changes since v2)
Changes in v2:
- Link
From: Andy Yan
RA620 is a DP to HDMI bridge converter from RADXA, which first
found be used on ROCK 5 ITX.
This chip can be used without involving software.
Signed-off-by: Andy Yan
Acked-by: Krzysztof Kozlowski
---
(no changes since v3)
Changes in v3:
- First introduced in this version.
From: Andy Yan
The DW DP TX Controller is compliant with the DisplayPort Specification
Version 1.4 with the following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
* Single Stream Transport(SST)
* Multistream
From: Andy Yan
The DP0 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY0 with USB 3.1
HOST0 controller.
Signed-off-by: Andy Yan
---
(no changes since v1)
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 +++
1 file changed, 30 inser
From: Andy Yan
There are two DW DPTX based DisplayPort Controller on rk3588 which
are compliant with the DisplayPort Specification Version 1.4 with
the following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
Hi,
Here's this week drm-misc-next PR.
Maxime
drm-misc-next-2025-06-19:
drm-misc-next for 6.17:
UAPI Changes:
- Add Task Information for the wedge API
Cross-subsystem Changes:
Core Changes:
- Fix warnings related to export.h
- fbdev: Make CONFIG_FIRMWARE_EDID available on all architectures
-
On Thu, Jun 19, 2025 at 3:12 PM Jocelyn Falempe wrote:
>
> On 13/06/2025 15:20, Ryosuke Yasuoka wrote:
> > Add drm_panic moudle for bochs drm so that panic screen can be displayed
> > on panic.
>
> Thanks for the patch, it's simple and looks good to me.
>
> Reviewed-by: Jocelyn Falempe
>
> If no
Hi Michal,
kernel test robot noticed the following build errors:
[auto build test ERROR on 4774cfe3543abb8ee98089f535e28ebfd45b975a]
url:
https://github.com/intel-lab-lkp/linux/commits/Michal-Wilczynski/power-sequencing-Add-T-HEAD-TH1520-GPU-power-sequencer-driver/20250618-182429
base
On 13/06/2025 15:20, Ryosuke Yasuoka wrote:
Add drm_panic moudle for bochs drm so that panic screen can be displayed
on panic.
Thanks for the patch, it's simple and looks good to me.
Reviewed-by: Jocelyn Falempe
If no objections, I will push it next Monday.
Best regards,
--
Jocelyn
Sig
On 19-06-2025 02:35, Daniele Ceraolo Spurio wrote:
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Reload late binding fw during runtime resume.
v2: Flush worker during runtime suspend
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 2 +-
drivers/gpu/drm/xe/xe_late_
On 18-06-25, 18:48, Miguel Ojeda wrote:
> On Sun, Jun 15, 2025 at 10:55 PM Tamir Duberstein wrote:
> >
> > Apply these changes and enable the lint -- no functional change
> > intended.
>
> We need one more for `opp` [1] -- Viresh: I can do it on apply, unless
> you disagree.
Please do. Thanks.
> -Original Message-
> From: Murthy, Arun R
> Sent: Thursday, June 19, 2025 10:47 AM
> To: Kandpal, Suraj ;
> nouv...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; intel-...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: RE: [PAT
On 19-06-2025 02:27, Daniele Ceraolo Spurio wrote:
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Load late binding firmware
v2:
- s/EAGAIN/EBUSY/
- Flush worker in suspend and driver unload (Daniele)
v3:
- Use retry interval of 6s, in steps of 200ms, to allow
other OS components rel
On Wed, Jun 18, 2025 at 03:29:26PM -0400, Zack Rusin wrote:
> From: Marko Kiiskila
>
> Commit 81256a50aa0f ("x86/mm: Make memremap(MEMREMAP_WB) map memory as
> encrypted by default") changed the default behavior of
> memremap(MEMREMAP_WB) and started mapping memory as encrypted.
> The driver requ
Hi,
On 19/06/2025 01:38, Marek Szyprowski wrote:
> On 18.06.2025 14:25, Tomi Valkeinen wrote:
>> On 18/06/2025 15:06, Marek Szyprowski wrote:
>>> Commit c9b1150a68d9 ("drm/atomic-helper: Re-order bridge chain pre-enable
>>> and post-disable") changed the call sequence to the CRTC enable/disable
>>
Hi Oscar,
> Subject: Re: [PATCH v4 2/3] mm/memfd: Reserve hugetlb folios before
> allocation
>
> On Tue, Jun 17, 2025 at 10:30:54PM -0700, Vivek Kasireddy wrote:
> > When we try to allocate a folio via alloc_hugetlb_folio_reserve(),
> > we need to ensure that there is an active reservation associ
Hi Andrew, Anshuman,
> Subject: Re: [PATCH] mm/hugetlb: Don't crash when allocating a folio if there
> are no resv
>
> On Wed, 18 Jun 2025 12:14:49 +0530 Anshuman Khandual
> wrote:
>
> > > Therefore, prevent the above crash by replacing the VM_BUG_ON()
> > > with WARN_ON_ONCE() as there is no n
> -Original Message-
> From: Kandpal, Suraj
> Sent: Monday, April 14, 2025 9:46 AM
> To: nouv...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; intel-...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Murthy, Arun R
> ; Kandpal, Suraj
> Subje
Hi Prabhakar,
> -Original Message-
> From: Biju Das
> Sent: 18 June 2025 14:26
> Subject: RE: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI
> clocks
>
> Hi Prabhakar,
>
> > -Original Message-
> > From: dri-devel On Behalf Of
> > Lad, Prabhakar
> > Sent: 16 June 20
> -Original Message-
> From: Kandpal, Suraj
> Sent: Monday, April 14, 2025 9:46 AM
> To: nouv...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; intel-...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Murthy, Arun R
> ; Kandpal, Suraj
> Subje
On Sun, 15 Jun 2025 16:55:09 -0400
Tamir Duberstein wrote:
> Before Rust 1.29.0, Clippy introduced the `cast_lossless` lint [1]:
>
>> Rust’s `as` keyword will perform many kinds of conversions, including
>> silently lossy conversions. Conversion functions such as `i32::from`
>> will only perform
> > -Original Message-
> > From: Murthy, Arun R
> > Sent: Thursday, June 12, 2025 4:43 PM
> > To: Kandpal, Suraj ;
> > nouv...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; intel-
> > x...@lists.freedesktop.org; intel-...@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K
> > Subje
Hi Thomas,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on v6.16-rc2 next-20250618]
[cannot apply to lee-backlight/for-backlight-next lee-leds/for-leds-next
drm-exynos/exynos-drm-next linus/master lee-backlight
During rpmsg_probe, fastrpc device nodes are created first, then
channel specific resources are initialized, followed by
of_platform_populate, which triggers context bank probing. This
sequence can cause issues as applications might open the device
node before channel resources are initialized or t
On 6/18/2025 7:38 PM, Christian König wrote:
On 6/18/25 15:47, Sunil Khatri wrote:
move the functions from drm_drv.c which uses the static
drm_debugfs_root as parent node in the debugfs by drm.
move this root node to the debugfs for easily handling
of future requirements to add more informati
On 19-06-2025 02:16, Daniele Ceraolo Spurio wrote:
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Search for late binding firmware binaries and populate the meta data of
firmware structures.
v2 (Daniele):
- drm_err if firmware size is more than max pay load size
- s/request_firmware/firmwa
On Wed, Jun 18, 2025 at 10:16:14PM +0200, Thomas Hellström wrote:
> This patchset modifies the migration part of drm_gpusvm to drm_pagemap and
> adds a populate_mm() op to drm_pagemap.
>
> The idea is that the device that receives a pagefault determines if it wants
> to
> migrate content and to w
On Wed, Jun 18, 2025 at 06:45:56PM +0200, Miguel Ojeda wrote:
> On Wed, Jun 18, 2025 at 3:54 PM Tamir Duberstein wrote:
> >
> > @Andreas Hindborg could you please have a look for configfs?
> >
> > @Rafael J. Wysocki @Viresh Kumar could you please have a look for cpufreq?
>
> Thanks Tamir.
>
> Ch
On Wed, Jun 18, 2025 at 07:29:25PM +0200, Miguel Ojeda wrote:
> On Sun, Jun 15, 2025 at 10:55 PM Tamir Duberstein wrote:
> >
> > rust/kernel/devres.rs | 2 +-
>
> Danilo, Greg: for completeness: if you don't want this, please shout. Thanks!
Acked-by: Greg Kroah-Hartman
On Wed, Jun 18, 2025 at 07:04:11PM +0200, Miguel Ojeda wrote:
> On Wed, Jun 18, 2025 at 3:51 PM Tamir Duberstein wrote:
> >
> > @Danilo Krummrich could you please have a look for nova?
>
> Alice, Christian, Danilo, Greg, Tejun: it would also be nice to get
> Acked-by's for your (other) bits.
Ack
On Wed, Jun 18, 2025 at 12:22:13PM +0200, Michal Wilczynski wrote:
> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD
> TH1520 SoC used by the Lichee Pi 4A board. This node enables support for
> the GPU using the drm/imagination driver.
>
> By adding this node, the kernel can
On Wed, Jun 18, 2025 at 12:22:12PM +0200, Michal Wilczynski wrote:
> Add the "gpu-clkgen" reset property to the AON device tree node. This
> allows the AON power domain driver to detect the capability to power
> sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary
> driver for managi
On Wed, Jun 18, 2025 at 12:22:08PM +0200, Michal Wilczynski wrote:
> Extend the TH1520 AON to describe the GPU clkgen reset line, required
> for proper GPU clock and reset sequencing.
>
> The T-HEAD TH1520 GPU requires coordinated management of two clocks
> (core and sys) and two resets (GPU core
On Wed, Jun 18, 2025 at 12:22:06PM +0200, Michal Wilczynski wrote:
> This patch series introduces support for the Imagination IMG BXM-4-64
> GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is
> managing the GPU's complex power-up and power-down sequence, which
> involves multiple c
On Thu, Jun 19, 2025 at 10:33 AM Shakeel Butt wrote:
>
> On Wed, Jun 18, 2025 at 02:06:17PM +1000, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > While discussing memcg intergration with gpu memory allocations,
> > it was pointed out that there was no numa/system counters for
> > GPU memory all
On Tue, Jun 17, 2025 at 11:30:20AM +0200, David Hildenbrand wrote:
> On 17.06.25 11:25, David Hildenbrand wrote:
> > On 16.06.25 13:58, Alistair Popple wrote:
> > > Previously dax pages were skipped by the pagewalk code as pud_special() or
> > > vm_normal_page{_pmd}() would be false for DAX pages.
On Wed, Jun 18, 2025 at 02:06:17PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> While discussing memcg intergration with gpu memory allocations,
> it was pointed out that there was no numa/system counters for
> GPU memory allocations.
>
> With more integrated memory GPU server systems turni
On Wed, 18 Jun 2025 14:06:17 +1000 Dave Airlie wrote:
> While discussing memcg intergration with gpu memory allocations,
> it was pointed out that there was no numa/system counters for
> GPU memory allocations.
>
> With more integrated memory GPU server systems turning up, and
> more requirement
On Wed, 18 Jun 2025 12:14:49 +0530 Anshuman Khandual
wrote:
> > Therefore, prevent the above crash by replacing the VM_BUG_ON()
> > with WARN_ON_ONCE() as there is no need to crash the system in
> > this situation and instead we could just warn and fail the
> > allocation.
>
> Why there are no
On Wed, Jun 18, 2025 at 12:22:07PM +0200, Michal Wilczynski wrote:
> Introduce the pwrseq-thead-gpu driver, a power sequencer provider for
> the Imagination BXM-4-64 GPU on the T-HEAD TH1520 SoC. This driver
> controls an auxiliary device instantiated by the AON power domain.
>
> The TH1520 GPU re
Hi André,
On Wed, 18 Jun 2025 11:22:29 -0300 André Almeida wrote:
>
> Fix the following warning:
>
> Documentation/gpu/drm-uapi.rst:450: WARNING: Title underline too short.
>
> Task information
> --- [docutils]
>
> Fixes: cd37124b4093 ("drm/doc: Add a section about "Task informatio
On 18.06.2025 14:25, Tomi Valkeinen wrote:
> On 18/06/2025 15:06, Marek Szyprowski wrote:
>> Commit c9b1150a68d9 ("drm/atomic-helper: Re-order bridge chain pre-enable
>> and post-disable") changed the call sequence to the CRTC enable/disable
>> and bridge pre_enable/post_disable methods, so those b
On Wed, Jun 18, 2025 at 3:19 PM Danilo Krummrich wrote:
>
> On Wed, Jun 18, 2025 at 02:56:37PM -0700, Rob Clark wrote:
> > On Wed, Jun 18, 2025 at 2:23 PM Danilo Krummrich wrote:
> > >
> > > On Tue, Jun 17, 2025 at 06:43:21AM -0700, Rob Clark wrote:
> > > > On Tue, Jun 17, 2025 at 5:48 AM Rob Cla
On Wed, Jun 18, 2025 at 02:56:37PM -0700, Rob Clark wrote:
> On Wed, Jun 18, 2025 at 2:23 PM Danilo Krummrich wrote:
> >
> > On Tue, Jun 17, 2025 at 06:43:21AM -0700, Rob Clark wrote:
> > > On Tue, Jun 17, 2025 at 5:48 AM Rob Clark
> > > wrote:
> > > >
> > > > On Tue, Jun 17, 2025 at 2:51 AM Dan
On Tue, Jun 17, 2025 at 06:43:21AM -0700, Rob Clark wrote:
> On Tue, Jun 17, 2025 at 5:48 AM Rob Clark wrote:
> >
> > On Tue, Jun 17, 2025 at 2:51 AM Danilo Krummrich wrote:
> > >
> > > On Mon, Jun 16, 2025 at 03:25:08PM -0700, Rob Clark wrote:
> > > > On Mon, Jun 16, 2025 at 2:39 PM Danilo Krumm
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Reload late binding fw during runtime resume.
v2: Flush worker during runtime suspend
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 2 +-
drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 +
drivers/gpu/drm/xe/xe_pm.c
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Extract and print version info of the late binding binary.
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 132 -
drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 3 +
drivers/gpu/drm/xe/xe_uc_fw_
On Wed, Jun 18, 2025 at 2:23 PM Danilo Krummrich wrote:
>
> On Tue, Jun 17, 2025 at 06:43:21AM -0700, Rob Clark wrote:
> > On Tue, Jun 17, 2025 at 5:48 AM Rob Clark
> > wrote:
> > >
> > > On Tue, Jun 17, 2025 at 2:51 AM Danilo Krummrich wrote:
> > > >
> > > > On Mon, Jun 16, 2025 at 03:25:08PM
On Wed, Jun 18, 2025 at 11:48 AM Anusha Srivatsa
wrote:
>
>
> On Wed, Jun 18, 2025 at 4:23 AM Maxime Ripard wrote:
>
>> On Wed, Jun 18, 2025 at 10:51:58AM +0200, Luca Ceresoli wrote:
>> > Hello Anusha, Francesco,
>> >
>> > On Tue, 17 Jun 2025 11:17:20 -0500
>> > Anusha Srivatsa wrote:
>> >
>> >
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Introduce a debug filesystem node to disable late binding fw reload
during the system or runtime resume. This is intended for situations
where the late binding fw needs to be loaded from user mode.
You haven't replied to my question on the previous
On Wed, Jun 18, 2025 at 01:15:16PM +0800, Ling Xu wrote:
> 在 6/16/2025 7:28 PM, Ling Xu 写道:
> > 在 4/8/2025 4:14 PM, Srinivas Kandagatla 写道:
> >>
> >>
> >> On 07/04/2025 10:13, Ling Xu wrote:
> >>> 在 3/21/2025 1:11 AM, Srinivas Kandagatla 写道:
>
>
> On 20/03/2025 09:14, Ling Xu wrote:
On Tue, Jun 17, 2025 at 11:56:11AM -0700, Randy Dunlap wrote:
> Add header to pull in readl/writel and friends.
> This eliminates the following build errors:
>
> drivers/gpu/drm/msm/dp/dp_panel.c: In function 'msm_dp_read_link':
> drivers/gpu/drm/msm/dp/dp_panel.c:33:16: error: implicit declarati
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Search for late binding firmware binaries and populate the meta data of
firmware structures.
v2 (Daniele):
- drm_err if firmware size is more than max pay load size
- s/request_firmware/firmware_request_nowarn/ as firmware will
not be availa
On 2025-06-17 15:45, David Francis wrote:
> Add new ioctl DRM_IOCTL_AMDGPU_CRIU_BO_INFO.
>
> This ioctl returns a list of bos with their handles, sizes,
> and flags and domains.
>
> This ioctl is meant to be used during CRIU checkpoint and
> provide information needed to reconstruct the bos
> in
On Wed, Jun 18, 2025 at 01:45:40PM -0500, Mario Limonciello wrote:
> On 6/18/2025 9:12 AM, Simona Vetter wrote:
> > On Wed, Jun 18, 2025 at 11:11:26AM +0200, Thomas Zimmermann wrote:
> > > Hi
> > >
> > > Am 17.06.25 um 22:22 schrieb Mario Limonciello:
> > > >
> > > >
> > > > On 6/17/25 2:22 PM,
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Load late binding firmware
v2:
- s/EAGAIN/EBUSY/
- Flush worker in suspend and driver unload (Daniele)
v3:
- Use retry interval of 6s, in steps of 200ms, to allow
other OS components release MEI CL handle (Sasha)
Signed-off-by: Badal Nila
The PPU flop reset is required on some hardware to clear the
temporary registers. This implementation follows the code
implemented in the public galcore kernel module code to this
for the PPU.
v2: - Move flop reset data to etnaviv_drm_private and initialize it
from etnaviv_gpu_bind (Lucas)
Signed-off-by: Gert Wollny
---
drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c
b/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c
index c33647e96636..bf4cae4be815 100644
--- a/drivers/gpu/drm/etnav
v2: fix formatting and remove superfluous masking (Lucas)
Signed-off-by: Gert Wollny
---
drivers/gpu/drm/etnaviv/etnaviv_buffer.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.h
b/drivers/gpu/drm/etnaviv/etnaviv_buffer.h
index caf820d9
Dear all,
this is the second version of the patches to add a PPU flop reset to
drm/etnaviv. The first version of the series was send as an RFC to
etna...@lists.freedesktop.org only.
This series adds running the PPU flop reset which is required for some
hardware. This implementation was tested
Signed-off-by: Gert Wollny
---
drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 71 +---
drivers/gpu/drm/etnaviv/etnaviv_buffer.h | 85
2 files changed, 86 insertions(+), 70 deletions(-)
create mode 100644 drivers/gpu/drm/etnaviv/etnaviv_buffer.h
diff --git a/
v2: move some defines into the header that resided
in etnaviv_flop_reset.c
Signed-off-by: Gert Wollny
---
drivers/gpu/drm/etnaviv/state_3d.xml.h | 97 ++
1 file changed, 97 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/state_3d.xml.h
b/drivers/gpu/drm/etnaviv/s
This is required to know whether to be able to avoid allocating
the flop reset data if non of the available GPUs actually need
it.
Signed-off-by: Gert Wollny
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/
From: Matthew Brost
The migration functionality and track-keeping of per-pagemap VRAM
mapped to the CPU mm is not per GPU_vm, but rather per pagemap.
This is also reflected by the functions not needing the drm_gpusvm
structures. So move to drm_pagemap.
With this, drm_gpusvm shouldn't really acce
Hi Dave, Simona,
Fixes for 6.16.
The following changes since commit e04c78d86a9699d136910cfc0bdcf01087e3267e:
Linux 6.16-rc2 (2025-06-15 13:49:41 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.16-2025-06-18
for you to fe
On 6/18/2025 12:00 PM, Badal Nilawar wrote:
Introducing xe_late_bind_fw to enable firmware loading for the devices,
such as the fan controller, during the driver probe. Typically,
firmware for such devices are part of IFWI flash image but can be
replaced at probe after OEM tuning.
This patch b
On Wed, Jun 18, 2025 at 10:23:15PM +0200, Danilo Krummrich wrote:
> On Thu, Jun 12, 2025 at 11:01:51PM +0900, Alexandre Courbot wrote:
> > @@ -237,6 +237,67 @@ pub(crate) fn new(
> > },
> > )?;
> >
> > +// Check that the WPR2 region does not already exists - if it
>
On Thu, Jun 12, 2025 at 11:01:51PM +0900, Alexandre Courbot wrote:
> @@ -237,6 +237,67 @@ pub(crate) fn new(
> },
> )?;
>
> +// Check that the WPR2 region does not already exists - if it does,
> the GPU needs to be
> +// reset.
> +if regs::NV_PFB_PRI
Add an operation to populate a part of a drm_mm with device
private memory. Clarify how migration using it is intended
to work.
v3:
- Kerneldoc fixes and updates (Matt Brost).
v4:
- More kerneldoc fixes. Rebase.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/drm
Add runtime PM since we might call populate_mm on a foreign device.
v3:
- Fix a kerneldoc failure (Matt Brost)
- Revert the bo type change from device to kernel (Matt Brost)
v4:
- Add an assert in xe_svm_alloc_vram (Matt Brost)
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Brost
---
dri
This patchset modifies the migration part of drm_gpusvm to drm_pagemap and
adds a populate_mm() op to drm_pagemap.
The idea is that the device that receives a pagefault determines if it wants to
migrate content and to where. It then calls the populate_mm() method of relevant
drm_pagemap.
This fun
On Thu, Jun 12, 2025 at 11:01:28PM +0900, Alexandre Courbot wrote:
> Hi everyone,
>
> The feedback on v4 has been (hopefully) addressed. I guess the main
> remaining unknown is the direction of the `num` module ; for this
> iteration, following the received feedback I have eschewed the extension
>
Hi Dave and Sima,
Here goes our first drm-xe-next pull-request towards 6.17.
The important part to mention is on the top of the tag below:
- uAPI addition for Media OA
- The restoration of a fix accidentally missed in a merge commit
- GPUSVM changes
Also, SVM enabling work itself, platform enabl
From: Marko Kiiskila
Commit 81256a50aa0f ("x86/mm: Make memremap(MEMREMAP_WB) map memory as
encrypted by default") changed the default behavior of
memremap(MEMREMAP_WB) and started mapping memory as encrypted.
The driver requires the fifo memory to be decrypted to communicate with
the host but wa
On Mon Jun 16, 2025 at 8:41 AM CEST, Alexandre Courbot wrote:
> On Sun Jun 15, 2025 at 4:16 AM JST, Benno Lossin wrote:
>> On Thu Jun 12, 2025 at 4:01 PM CEST, Alexandre Courbot wrote:
>>> +#[inline(always)]
>>> +pub const fn [](v: $t) -> u32 {
>>
>> Can we name this `find_l
Reload late binding fw during runtime resume.
v2: Flush worker during runtime suspend
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 2 +-
drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 +
drivers/gpu/drm/xe/xe_pm.c | 6 ++
3 files changed, 8 insertions(+), 1 de
Extract and print version info of the late binding binary.
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 132 -
drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 3 +
drivers/gpu/drm/xe/xe_uc_fw_abi.h | 69 +++
3 files changed, 2
Do not review
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index 30ed74ad29ab..b161e1156c73 100644
--- a/drivers/gpu/drm/xe/Kconfig
+++ b/drivers/gpu/drm/xe/Kconfig
@@ -44,6
Reload late binding fw during S2Idle/S3 resume.
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index 91923fd4af80..6c44a075a6ab 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++
Introduce a debug filesystem node to disable late binding fw reload
during the system or runtime resume. This is intended for situations
where the late binding fw needs to be loaded from user mode.
v2:
-s/(uval == 1) ? true : false/!!uval/ (Daniele)
Signed-off-by: Badal Nilawar
---
drivers/gp
Load late binding firmware
v2:
- s/EAGAIN/EBUSY/
- Flush worker in suspend and driver unload (Daniele)
v3:
- Use retry interval of 6s, in steps of 200ms, to allow
other OS components release MEI CL handle (Sasha)
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c
From: Alexander Usyskin
Add late binding component driver.
It allows pushing the late binding configuration from, for example,
the Xe graphics driver to the Intel discrete graphics card's CSE device.
Signed-off-by: Alexander Usyskin
Signed-off-by: Badal Nilawar
---
v2:
- Use generic naming (J
Search for late binding firmware binaries and populate the meta data of
firmware structures.
v2 (Daniele):
- drm_err if firmware size is more than max pay load size
- s/request_firmware/firmware_request_nowarn/ as firmware will
not be available for all possible cards
v3 (Daniele):
- init fir
Introducing xe_late_bind_fw to enable firmware loading for the devices,
such as the fan controller, during the driver probe. Typically,
firmware for such devices are part of IFWI flash image but can be
replaced at probe after OEM tuning.
This patch binds mei late binding component to enable firmwar
From: Alexander Usyskin
Allow to bus client to obtain client mtu.
Signed-off-by: Alexander Usyskin
Signed-off-by: Badal Nilawar
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/misc/mei/bus.c | 13 +
include/linux/mei_cl_bus.h | 1 +
2 files changed, 14 insertions(+)
diff --g
On Tue, Jun 17, 2025 at 12:23:41PM +0200, Jan Kara wrote:
> On Mon 16-06-25 20:33:28, Lorenzo Stoakes wrote:
> > Update nearly all generic_file_mmap() and generic_file_readonly_mmap()
> > callers to use generic_file_mmap_prepare() and
> > generic_file_readonly_mmap_prepare() respectively.
> >
> >
On Tue, Jun 17, 2025 at 10:30:54PM -0700, Vivek Kasireddy wrote:
> When we try to allocate a folio via alloc_hugetlb_folio_reserve(),
> we need to ensure that there is an active reservation associated
> with the allocation. Otherwise, our allocation request would fail
> if there are no active reser
Introducing firmware late binding feature to enable firmware loading
for the devices, such as the fan controller and voltage regulator,
during the driver probe.
Typically, firmware for these devices are part of IFWI flash image but
can be replaced at probe after OEM tuning.
v2:
- Dropped voltage
On 18/06/25 10:58 AM, Vivek Kasireddy wrote:
> There are cases when we try to pin a folio but discover that it has
> not been faulted-in. So, we try to allocate it in memfd_alloc_folio()
> but there is a chance that we might encounter a fatal crash/failure
> (VM_BUG_ON(!h->resv_huge_pages) in al
Lorenzo Stoakes wrote:
> This is preferred to the existing f_op->mmap() hook as it does require a
> VMA to be established yet,
Did you mean ".. doesn't require a VMA to be established yet, ..."
David
On 6/16/25 2:33PM, Lorenzo Stoakes wrote:
Since commit c84bf6dd2b83 ("mm: introduce new .mmap_prepare() file
callback"), the f_op->mmap() hook has been deprecated in favour of
f_op->mmap_prepare().
We have provided generic .mmap_prepare() equivalents, so update all file
systems that specify thes
On Mon, 2025-06-16 at 21:41 +0100, Al Viro wrote:
> On Mon, Jun 16, 2025 at 08:33:19PM +0100, Lorenzo Stoakes wrote:
> > REVIEWER'S NOTES
> >
> >
> > I am basing this on the mm-new branch in Andrew's tree, so let me know if I
> > should rebase anything here. Given the mm bits touc
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