On 23/06/2024 13:06, Akhil P Oommen wrote:
> Document Adreno X185 GMU in the dt-binding specification.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 23/06/2024 13:06, Akhil P Oommen wrote:
> This series adds support for the Adreno X1-85 GPU found in Qualcomm's
> compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
> naming scheme for Adreno GPU, 'X' stands for compute series, '1' denotes
> 1st generation and '8' & '5' denotes
Add the necessary dt nodes for gpu support in X1E80100.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +
1 file changed, 195 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
Document Adreno X185 GMU in the dt-binding specification.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
Add support in drm/msm driver for the Adreno X185 gpu found in
Snapdragon X1 Elite chipset.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++
drivers/gpu/drm/msm/adreno/adreno_device.c
This series adds support for the Adreno X1-85 GPU found in Qualcomm's
compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
naming scheme for Adreno GPU, 'X' stands for compute series, '1' denotes
1st generation and '8' & '5' denotes the tier and the SKU which it
belongs.
X1-85 has
On Sun, Jun 23, 2024 at 7:59 AM Dmitry Baryshkov
wrote:
>
> On Sun, Jun 23, 2024 at 01:25:52AM GMT, Barnabás Czémán wrote:
> > From: Daniil Titov
> >
> > Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
> >
> > Signed-off-by: Daniil Titov
> > Signed-off-by: Barnabás Czémán
>
Are you planning on submitting a bogus CVE for this patch too?
- Joshie ✨
On June 22, 2024 9:22:19 AM GMT+01:00, Ma Ke wrote:
>In amdgpu_connector_add_common_modes(), the return value of drm_cvt_mode()
>is assigned to mode, which will lead to a NULL pointer dereference on
>failure of
The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.
Add a quirk to override that the minimum backlight PWM to "0" which
leads to a much lower minimum brightness, which is still visible.
Tested on a Framework
The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.
Add a generic quirk infrastructure for backlight configuration to
override the settings provided by the firmware.
Also add amdgpu as a user of that
Panels using a PWM-controlled backlight source without an do not have a
standard way to communicate their valid PWM ranges.
On x86 the ranges are read from ACPI through driver-specific tables.
The built-in ranges are not necessarily correct, or may grow stale if an
older device can be retrofitted
Not all platforms provide correct PWM backlight capabilities through ATIF.
Use the generic drm backlight quirk infrastructure to override the
capabilities where necessary.
Signed-off-by: Thomas Weißschuh
---
drivers/gpu/drm/amd/amdgpu/Kconfig| 1 +
On 23/06/2024 01:25, Barnabás Czémán wrote:
> The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new
> compatible for it.
>
> Signed-off-by: Barnabás Czémán
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 23/06/2024 01:25, Barnabás Czémán wrote:
> Add the compatible for the MDP5 found on MSM8937.
>
> Signed-off-by: Barnabás Czémán
> ---
Reviewed-by: Krzysztof Kozlowski
---
This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process,
On Sun, Jun 23, 2024 at 03:38:23PM +0800, Sui Jingfeng wrote:
> Hi,
>
> On 6/23/24 03:29, Dmitry Torokhov wrote:
> > > In case of non-OF match (which
> > > > includes the case where you use software nodes) the match data is coming
> > > > from matching spi_device_id entry in the driver.
> > >
>
Hi,
On 6/23/24 03:29, Dmitry Torokhov wrote:
In case of non-OF match (which
includes the case where you use software nodes) the match data is coming
from matching spi_device_id entry in the driver.
We don't care about much how it is probed now, rather, after the driver
probed by a non-OF
On 6/21/24 13:30, Sunil Kovvuri Goutham wrote:
+
+What:
/sys/kernel/debug/habanalabs_cn/hbl_cn/nic_disable_decap
+What:
/sys/kernel/debug/habanalabs_cn/hbl_cn/nic_inject_rx_err
+What:
>> /sys/kernel/debug/habanalabs_cn/hbl_cn/nic_mac_lane_remap
Hi Maxime：
> -Original Message-
> From: Maxime Ripard
> Sent: 2024年5月22日 15:25
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com;
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 5:06
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com;
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月21日 23:25
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com;
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 4:53
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com;
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 5:08
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com;
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 5:14
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com;
Hi Dmitry:
> -Original Message-
> From: Dmitry Baryshkov
> Sent: 2024年5月22日 4:51
> To: Keith Zhao
> Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; rf...@kernel.org;
> laurent.pinch...@ideasonboard.com; jo...@kwiboo.se;
> jernej.skra...@gmail.com;
On Thu, 30 May 2024 13:56:44 +0800, Jun Nie wrote:
> This is follow up update to Jonathan's patch set.
>
> Changes vs V5:
> - Add hardware version check for compression bit change in cfg2 register
>
> Changes vs V4:
> - Polish width calculation with helper function
> - Split cfg2 compression
On Tue, 23 Apr 2024 00:36:58 +0200, Konrad Dybcio wrote:
> Shaving off some cruft
>
> obj files seem to be identical pre and post cleanup which is always
> a good sign
>
>
Applied, thanks!
[1/2] drm/msm/dsi: Remove dsi_phy_read/write()
On Fri, 07 Jun 2024 16:22:57 +0300, Dmitry Baryshkov wrote:
> This patchset sits on top Maxime's HDMI connector patchset ([1]).
>
> Currently this is an RFC exploring the interface between HDMI bridges
> and HDMI connector code. This has been lightly verified on the Qualcomm
> DB820c, which has
On Thu, 20 Jun 2024 13:17:30 -0700, Abhinav Kumar wrote:
> clear_pending_flush() ctl op is always assigned irrespective of the DPU
> hardware revision. Hence there is no needed to check whether the op has
> been assigned before calling it.
>
> Drop the checks across the driver for
On Tue, 14 May 2024 15:55:06 +0300, Jani Nikula wrote:
> Convert more drivers to struct drm_edid.
>
> Compile tested only.
>
> Jani Nikula (11):
> drm/rockchip: cdn-dp: get rid of drm_edid_raw()
> drm/sti/sti_hdmi: convert to struct drm_edid
> drm/bridge: analogix_dp: convert to struct
On Thu, 13 Jun 2024 20:05:03 +0300, Dmitry Baryshkov wrote:
> Command-mode DSI panels need to signal the display controlller when
> vsync happens, so that the device can start sending the next frame. Some
> devices (Google Pixel 3) use a non-default pin, so additional
> configuration is
On Thu, 09 May 2024 19:52:04 +0200, Barnabás Czémán wrote:
> CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
> so better to skip CTL irq callback register/unregister
> make dpu_ctl_cfg be able to define without intr_start.
>
>
Applied, thanks!
[1/1] drm/msm/dpu:
On Sat, 15 Jun 2024 00:58:51 +0300, Danila Tikhonov wrote:
> This series adds MDSS and DPU support for SM7150.
>
> Changes in v3:
> - Swap DPU and MDSS patches (Krzysztof)
> - Add an explanation of the abbreviation DPU in patch 1 (Krzysztof)
> - Switch qseed3_1_4 on qseed3_2_4 in patch 2
The following changes since commit 1ddaaa244021aba8496536a6627b4ad2bc0f936a:
Merge tag 'amd-drm-next-6.11-2024-06-07' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2024-06-11 14:01:55
+1000)
are available in the Git repository at:
On 6/21/24 18:33, Andrew Lunn wrote:
>> I see other vendors have debugfs entries for debug configurations or
>> settings, not just for dumping debug info.
>
> Did you see any added in the last few years? This is also something
> DaveM pushed back on. We want uniform APIs so that all devices look
On 6/19/24 19:13, Andrew Lunn wrote:
> On Wed, Jun 19, 2024 at 07:16:20AM +, Omer Shpigelman wrote:
>> On 6/18/24 17:19, Andrew Lunn wrote:
>> +static u32 hbl_en_get_mtu(struct hbl_aux_dev *aux_dev, u32 port_idx)
>> +{
>> + struct hbl_en_port *port = HBL_EN_PORT(aux_dev,
On Sun, Jun 23, 2024 at 01:25:54AM GMT, Barnabás Czémán wrote:
> From: Daniil Titov
>
> Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only
> difference from existing msm8916 configuration is number of phy
> and io_start addresses.
>
> Signed-off-by: Daniil Titov
> Signed-off-by:
On Sun, Jun 23, 2024 at 11:11 AM Matthew Wilcox wrote:
>
> On Sun, Jun 23, 2024 at 10:29:30AM +0800, Yafang Shao wrote:
> > On Fri, Jun 21, 2024 at 9:57 PM Matthew Wilcox wrote:
> > >
> > > On Fri, Jun 21, 2024 at 10:29:54AM +0800, Yafang Shao wrote:
> > > > +++ b/mm/internal.h
> > >
> > > Why
On Sun, Jun 23, 2024 at 01:25:52AM GMT, Barnabás Czémán wrote:
> From: Daniil Titov
>
> Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
>
> Signed-off-by: Daniil Titov
> Signed-off-by: Barnabás Czémán
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89
>
On HDMI connectors which use drm_bridge_connector and DRM_BRIDGE_OP_HDMI
IGT chokes on the max_bpc property in several kms_properties tests due
to the the drm_bridge_connector failing to reset HDMI-related
properties.
Call __drm_atomic_helper_connector_hdmi_reset() if there is a
the
With the introduction of the HDMI Connector framework the driver might
end up creating the max_bpc property with min = max = 8. IGT insists
that such properties carry the 'immutable' flag. Automatically set the
flag if the driver asks for the max_bpc property with min == max.
Fixes: aadb3e16b8f3
Running IGT tests on Qualcomm Dragonboard820c uncovered two issues with
the HDMI Connector implementation and with its integration into the
drm_bridge_connector. Fix those issues.
Signed-off-by: Dmitry Baryshkov
---
Changes in v2:
- Actually pass the flags to drm_property_create_range().
- Link
Running IGT tests on Qualcomm Dragonboard820c uncovered two issues with
the HDMI Connector implementation and with its integration into the
drm_bridge_connector. Fix those issues.
Signed-off-by: Dmitry Baryshkov
---
Dmitry Baryshkov (2):
drm/bridge-connector: reset the HDMI connector state
On HDMI connectors which use drm_bridge_connector and DRM_BRIDGE_OP_HDMI
IGT chokes on the max_bpc property in several kms_properties tests due
to the the drm_bridge_connector failing to reset HDMI-related
properties.
Call __drm_atomic_helper_connector_hdmi_reset() if there is a
the
With the introduction of the HDMI Connector framework the driver might
end up creating the max_bpc property with min = max = 8. IGT insists
that such properties carry the 'immutable' flag. Automatically set the
flag if the driver asks for the max_bpc property with min == max.
Fixes: aadb3e16b8f3
On Sun, Jun 23, 2024 at 10:29:30AM +0800, Yafang Shao wrote:
> On Fri, Jun 21, 2024 at 9:57 PM Matthew Wilcox wrote:
> >
> > On Fri, Jun 21, 2024 at 10:29:54AM +0800, Yafang Shao wrote:
> > > +++ b/mm/internal.h
> >
> > Why are you putting __kstrndup in a header file when it's only used
> > in
On Fri, Jun 21, 2024 at 9:57 PM Matthew Wilcox wrote:
>
> On Fri, Jun 21, 2024 at 10:29:54AM +0800, Yafang Shao wrote:
> > +++ b/mm/internal.h
>
> Why are you putting __kstrndup in a header file when it's only used
> in util.c?
I want to make it always inlined. However, it is not recommended to
On Fri, Jun 21, 2024 at 9:51 PM Simon Horman wrote:
>
> On Fri, Jun 21, 2024 at 10:29:54AM +0800, Yafang Shao wrote:
> > These three functions follow the same pattern. To deduplicate the code,
> > let's introduce a common help __kstrndup().
> >
> > Suggested-by: Andrew Morton
> > Signed-off-by:
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new
compatible for it.
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 +
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml| 1 +
2 files changed, 2 insertions(+)
From: Daniil Titov
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only
difference from existing msm8916 configuration is number of phy
and io_start addresses.
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
Add the compatible for the MDP5 found on MSM8937.
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
From: Daniil Titov
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89
1 file changed, 89 insertions(+)
diff --git
This patch series adds support for the MDP and DSI PHY as found on the
MSM8937 platform.
Signed-off-by: Barnabás Czémán
---
Barnabás Czémán (2):
dt-bindings: display/msm: qcom, mdp5: Add msm8937 compatible
dt-bindings: msm: dsi-phy-28nm: Document msm8937 compatible
Daniil Titov (2):
Currently the DRM DSC functions are selected by the
DRM_DISPLAY_DP_HELPER Kconfig symbol. This is not optimal, since the DSI
code (both panel and host drivers) end up selecting the seemingly
irrelevant DP helpers. Split the DSC code to be guarded by the separate
DRM_DISPLAY_DSC_HELPER Kconfig
The HDMI driver already has msm_hdmi_hpd_enable() and
msm_hdmi_hpd_disable() functions. Wire them into the
msm_hdmi_bridge_funcs, so that HPD can be enabled and disabled
dynamically rather than always having HPD events generation enabled.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry
It is completely not obvious, but the so-called 'hpd' clocks and
regulators are required for the HDMI host to function properly. Merge
pwr and hpd regulators. Use regulators, clocks and pinctrl to implement
proper runtime PM callbacks.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
The HDMI block needs to be enabled to properly generate HPD events. Make
sure it is not turned off in the disable paths if HPD delivery is enabled.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h
Supporting simultaneous check of native HPD and the external GPIO proved
to be less stable than just native HPD. Drop the hpd-gpios support,
leaving just the native HPD support. In case the native HPD doesn't work
the user is urged to switch to specifying the HPD property to the
hdmi-connector
We must be sure that the HDMI controller is powered on, while performing
the DDC transfer. Add corresponding runtime PM calls to
msm_hdmi_i2c_xfer().
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_i2c.c | 14 --
1 file changed, 12
The only clock which has frequency being set through hpd_freqs is the
"core" aka MDSS_HDMI_CLK clock. It always has the specified frequency,
so we can drop corresponding clk_set_rate() call together with the
hpd_freq infrastructure.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
As these clocks are now used in the runtime PM callbacks, they have no
connection to 'HPD'. Rename corresponding fields to follow clocks
purpose, to power up the HDMI controller.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 26
Expand the HDMI_CFG() macro in HDMI config description. It has no added
value other than hiding some boilerplate declarations.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 16
drivers/gpu/drm/msm/hdmi/hdmi.h | 2 +-
2 files
The last platform using legacy clock names for HDMI block (APQ8064)
switched to new clock names in 5.16. It's time to stop caring about old
DT, drop hand-coded helpers and switch to clk_bulk_* API.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 24
drivers/gpu/drm/msm/hdmi/hdmi.h| 6
According to the vendor kernel [1] , the alt_iface clock should be
enabled together with the rest of HPD clocks, to make HPD to work
properly.
[1]
https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03
Reviewed-by: Jessica Zhang
Reviewed-by: Konrad
The pm_runtime_get_sync() function is a bad choise for runtime power
management. Switch HDMI driver to pm_runtime_resume_and_get() and add
proper error handling, while we are at it.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 +-
The mode_set callback is deprecated, it doesn't get the
drm_bridge_state, just mode-related argumetns. Also Abhinav pointed out
that HDMI timings should be programmed after setting up HDMI PHY and
PLL. Rework the code to program HDMI timings at the end of
atomic_pre_enable().
Signed-off-by:
The MSM HDMI driver is plagued with the long-standing bug. If HDMI cable
is disconnected, in most of the cases cable reconnection will not be
detected properly. We have been carrying the patch from [1] in our
integration tree for ages. The time has come to fix the long-standing
bug and implement
On Sun, Jun 23, 2024 at 02:04:00AM +0800, Sui Jingfeng wrote:
> Hi,
>
> On 6/22/24 03:58, Dmitry Torokhov wrote:
> > Hi Sui,
> >
> > On Sun, Apr 28, 2024 at 04:36:50AM +0800, Sui Jingfeng wrote:
> > > Because the software node backend of the fwnode API framework lacks an
> > > implementation for
Hi,
On 6/22/24 03:58, Dmitry Torokhov wrote:
Hi Sui,
On Sun, Apr 28, 2024 at 04:36:50AM +0800, Sui Jingfeng wrote:
Because the software node backend of the fwnode API framework lacks an
implementation for the .device_get_match_data function callback. This
makes it difficult to use(and/or
Allow userspace to use explicit synchronization with atomic async flips.
That means that the flip will wait for some hardware fence, and then
will flip as soon as possible (async) in regard of the vblank.
Signed-off-by: André Almeida
---
This patch is originally from a patchset, but it doesn't
In cdv_intel_lvds_get_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_mode_duplicate(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/gma500/cdv_intel_lvds.c | 2 ++
1 file changed, 2
In amdgpu_connector_add_common_modes(), the return value of drm_cvt_mode()
is assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_cvt_mode(). Add a check to avoid npd.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 ++
1 file changed, 2
Hello,
Not sure when this started exactly (if needed, I can do a git bisect) but with
Linux-6.6 (currently running 6.6.31) I get the following set of warnings during
the boot on NVIDIA Quadro K600:
[3.814473] Bogus possible_crtcs: [ENCODER:64:sor-0002-0fc1]
possible_crtcs=0xf (full crtc
Hi Dave, Sima,
More new stuff for 6.11.
The following changes since commit b95fa494d6b74c30eeb4a50481aa1041c631754e:
drm/amdgpu: add RAS is_rma flag (2024-06-05 11:25:14 -0400)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
> In cdv_intel_lvds_get_modes(), the return value of drm_mode_duplicate()
> is assigned to mode, which will lead to a NULL pointer dereference on
> failure of drm_mode_duplicate(). Add a check to avoid npd.
1. Can a wording approach (like the following) be a better change description?
A null
> In amdgpu_connector_add_common_modes(), the return value of drm_cvt_mode()
> is assigned to mode, which will lead to a NULL pointer dereference on
> failure of drm_cvt_mode(). Add a check to avoid npd.
Can a wording approach (like the following) be a better change description?
A null
On Thu, Jun 13, 2024 at 08:21:59PM GMT, Marijn Suijten wrote:
> Maybe retitle this to something that more closely resembles "remove unset
> is_te_using_watchdog_timer field"?
Well, it really moves vsync_source selection to
_dpu_kms_initialize_dsi(), it doesn't just drop the
On Wed, Nov 08, 2023 at 01:27:22PM GMT, Tomi Valkeinen wrote:
> From: Aradhya Bhatia
>
> With new connector model, tc358767 will not create the connector, when
> DRM_BRIDGE_ATTACH_NO_CONNECTOR is set and display-controller driver will
> rely on format negotiation to setup the encoder format.
>
On Sat, Jun 22, 2024 at 05:16:58PM GMT, Aradhya Bhatia wrote:
>
>
> On 17-Jun-24 13:41, Dmitry Baryshkov wrote:
> > On Mon, Jun 17, 2024 at 07:40:32AM GMT, Jan Kiszka wrote:
> >> On 16.02.24 15:57, Marek Vasut wrote:
> >>> On 2/16/24 10:10, Tomi Valkeinen wrote:
> Ok. Does anyone have a
On Fri, Jun 21, 2024 at 05:53:53PM +0200, Marek Vasut wrote:
> Document default DP port preemphasis configurable via new DT property
> "toshiba,pre-emphasis". This is useful in case the DP link properties
> are known and starting link training from preemphasis setting of 0 dB
> is not useful. The
On 22.06.2024 1:36 PM, Konrad Dybcio wrote:
> On 20.06.2024 11:52 PM, Barnabás Czémán wrote:
>> From: Otto Pflüger
>>
>> Add support for Adreno 306A GPU what is found in MSM8917 SoC.
>> This GPU marketing name is Adreno 308.
>>
>> Signed-off-by: Otto Pflüger
>> [use internal name of the GPU,
On 17-Jun-24 13:41, Dmitry Baryshkov wrote:
> On Mon, Jun 17, 2024 at 07:40:32AM GMT, Jan Kiszka wrote:
>> On 16.02.24 15:57, Marek Vasut wrote:
>>> On 2/16/24 10:10, Tomi Valkeinen wrote:
Ok. Does anyone have a worry that these patches make the situation
worse for the DSI case than
On Thu, Jun 20, 2024 at 01:17:30PM GMT, Abhinav Kumar wrote:
> clear_pending_flush() ctl op is always assigned irrespective of the DPU
> hardware revision. Hence there is no needed to check whether the op has
> been assigned before calling it.
>
> Drop the checks across the driver for
On Sat, Jun 15, 2024 at 12:58:53AM GMT, Danila Tikhonov wrote:
> Add definitions for the display hardware used on the Qualcomm SM7150
> platform.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../msm/disp/dpu1/catalog/dpu_5_2_sm7150.h| 335 ++
>
On Thu, May 09, 2024 at 12:14:19PM GMT, Abhinav Kumar wrote:
>
>
> On 5/9/2024 10:52 AM, Barnabás Czémán wrote:
> > CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
> > so better to skip CTL irq callback register/unregister
> > make dpu_ctl_cfg be able to define
On 20.06.2024 11:52 PM, Barnabás Czémán wrote:
> From: Otto Pflüger
>
> Add support for Adreno 306A GPU what is found in MSM8917 SoC.
> This GPU marketing name is Adreno 308.
>
> Signed-off-by: Otto Pflüger
> [use internal name of the GPU, reword the commit message]
> Signed-off-by: Barnabás
The cdns-dsi controller requires that it be turned on completely before
the input DPI's source has begun streaming[0]. Not having that, allows
for a small window before cdns-dsi enable and after cdns-dsi disable
where the previous entity (in this case tidss's videoport) to continue
streaming DPI
Allow the D-Phy config checks to use mode->clock instead of
mode->crtc_clock during mode_valid checks, like everywhere else in the
driver.
Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework")
Signed-off-by: Aradhya Bhatia
---
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 2 +-
The order of init of DSI link and DSI phy is wrong. The DSI link needs
to be configured before the DSI phy is getting configured. Otherwise,
the D-Phy is unable to lock in on the incoming PLL Reference clock[0].
Fix the order of inits.
[0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E
Instead of manually finding the next bridge/panel, and maintaining the
panel-bridge (in-case the next entity is a panel), switch to using the
automatically managing devm_drm_of_get_bridge() API.
Drop the drm_panel support completely from the driver while at it.
Signed-off-by: Aradhya Bhatia
---
If any normal DCS write command has already been transmitted prior to
transmitting any Zero-Parameter DCS command, then it is necessary to
clear the TX FIFO by resetting it. Otherwise, the FIFO points to another
location, and the DCS command transmits unnecessary data causing the
panel to not
Move the bridge pre_enable call before crtc enable, and the bridge
post_disable call after the crtc disable.
The sequence of enable after this patch will look like:
bridge[n]_pre_enable
...
bridge[1]_pre_enable
crtc_enable
encoder_enable
Change the existing (and deprecated) bridge hooks, to the bridge
atomic APIs.
Add drm helpers for duplicate_state, destroy_state, and bridge_reset
bridge hooks.
Further add support for the input format negotiation hook.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Aradhya Bhatia
---
Add a helper API that can be used by the DSI hosts to find the required
input bus format for the given output dsi pixel format.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Aradhya Bhatia
---
drivers/gpu/drm/drm_mipi_dsi.c | 37 ++
include/drm/drm_mipi_dsi.h
Hello all,
This series provides some crucial fixes and improvements for the Cadence's DSI
TX (cdns-dsi) controller found commonly in Texas Instruments' J7 family of SoCs
as well as in AM62P.
Along with that, this series aims to fix the color-shift issue that has been
going on with the DSI
Initialize the Phy during the cdns-dsi _resume(), and de-initialize it
during the _suspend().
Also power-off the Phy from bridge_disable.
Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework")
Signed-off-by: Aradhya Bhatia
---
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 10
Once the DSI Link and DSI Phy are initialized, the code needs to wait
for Clk and Data Lanes to be ready, before continuing configuration.
This is in accordance with the DSI Start-up procedure, found in the
Technical Reference Manual of Texas Instrument's J721E SoC[0] which
houses this DSI TX
Fix the OF node pointer passed to the of_drm_find_bridge() call to find
the next bridge in the display chain.
To find the next bridge in the pipeline, we need to pass "np" - the OF
node pointer of the next entity in the devicetree chain. Passing
"of_node" to of_drm_find_bridge will make the
On 6/22/24 07:14, Jeff Johnson wrote:
With ARCH=i386, make allmodconfig && make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/char/agp/ali-agp.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/char/agp/ati-agp.o
WARNING: modpost: missing
On 6/22/24 08:07, Jeff Johnson wrote:
With ARCH=i386, make allmodconfig && make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/video/console/mdacon.o
Add the missing invocation of the MODULE_DESCRIPTION() macro to all
files which have a MODULE_LICENSE().
This
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