On 5/14/2023 10:01 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:12, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation and flipping when calculating src
positions for the wide plane parts.
Signed-off-by: Dmitry Baryshkov
998 and SC8180X in the
title.
On 2023-05-12 11:00:16, Kuogee Hsieh wrote:
From: Abhinav Kumar
There are some platforms has DSC blocks but it is not declared at catalog.
Some platforms have DSC blocks which have not yet been declared in the
catalog.*
For completeness, this patch adds DSC blo
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF indices. As of commit ef58e0ad3436
("drm/msm/dpu: get INTF blocks directly rather than through RM") the hw
resources struct was removed, leaving
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
As the debugfs is fully cleared on drm device removal, drop the
encoder-specific cleanup function, remove debugfs_root from dpu_encoder
struct and also remove phys_encoder late_register() ops which has been
unused since the driver being added.
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation and flipping when calculating src
positions for the wide plane parts.
Signed-off-by: Dmitry Baryshkov
Do we need to have a fixes tag for this? This means we dont consider
rotation while calculating src
On 5/12/2023 11:50 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:47, Abhinav Kumar wrote:
On 5/12/2023 11:21 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from
On 5/12/2023 11:21 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both
On 5/10/2023 11:15 PM, Marijn Suijten wrote:
On 2023-05-10 14:03:14, Jessica Zhang wrote:
On 5/9/2023 11:33 PM, Marijn Suijten wrote:
On 2023-05-09 15:06:50, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Reviewed-by:
On 5/10/2023 11:28 PM, Dmitry Baryshkov wrote:
On 11/05/2023 00:03, Jessica Zhang wrote:
On 5/9/2023 11:33 PM, Marijn Suijten wrote:
On 2023-05-09 15:06:50, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Reviewed-by:
On 5/10/2023 9:39 PM, Dmitry Baryshkov wrote:
On 11/05/2023 07:38, Abhinav Kumar wrote:
On 5/10/2023 9:29 PM, Dmitry Baryshkov wrote:
On 11/05/2023 01:07, Kuogee Hsieh wrote:
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, en
On 5/10/2023 9:29 PM, Dmitry Baryshkov wrote:
On 11/05/2023 01:07, Kuogee Hsieh wrote:
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine moved to INTF with the help of the flush mechanism.
Nit: was
On 5/10/2023 4:55 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2023-05-10 13:31:04)
The internal_hpd flag was introduced to handle external DP HPD derived from GPIO
pinmuxed into DP controller.
Was it? It looks more like it was done to differentiate between eDP and
DP, because
Hi Stephen
On 5/10/2023 4:19 PM, Kuogee Hsieh wrote:
internal_hpd is referenced at both plug and unplug handle.
The majority purpose of mutext is try to serialize internal_hpd between
dp_bridge_hpd_disable() and either plug or unplug handle.
On 5/10/2023 4:11 PM, Abhinav Kumar wrote
On 5/10/2023 3:46 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2023-05-10 13:31:05)
Intrenal_hpd is referenced by event thread but set by drm bridge callback
context. Add mutex to protect internal_hpd to avoid conflicts between
threads.
Signed-off-by: Kuogee Hsieh
---
This patch looks
On 5/8/2023 4:30 AM, Dmitry Baryshkov wrote:
On 08/05/2023 14:02, Leonard Lausen wrote:
Abhinav Kumar writes:
On 5/7/2023 7:15 PM, Bjorn Andersson wrote:
When booting with the cable connected on my X13s, 100 is long enough
for
my display to time out and require me to disconnect
On 5/9/2023 4:42 AM, Dmitry Baryshkov wrote:
On 09/05/2023 11:54, Konrad Dybcio wrote:
On 9.05.2023 10:23, Neil Armstrong wrote:
On 09/05/2023 01:27, Dmitry Baryshkov wrote:
On 08/05/2023 23:09, Abhinav Kumar wrote:
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19
On 5/8/2023 5:47 PM, Dmitry Baryshkov wrote:
On 09/05/2023 03:45, Abhinav Kumar wrote:
On 5/8/2023 4:27 PM, Dmitry Baryshkov wrote:
On 08/05/2023 23:09, Abhinav Kumar wrote:
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count
On 5/8/2023 4:27 PM, Dmitry Baryshkov wrote:
On 08/05/2023 23:09, Abhinav Kumar wrote:
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count is calculated using slice_count. This is
incorrect
as downstream uses slice per packet
On 5/8/2023 4:08 PM, Dmitry Baryshkov wrote:
On 09/05/2023 00:46, Jessica Zhang wrote:
On 5/7/2023 9:00 AM, Marijn Suijten wrote:
On 2023-05-05 14:23:50, Jessica Zhang wrote:
Add DATA_COMPRESS feature flag to DPU INTF block.
In DPU 7.x and later, DSC/DCE enablement registers have been
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count is calculated using slice_count. This is incorrect
as downstream uses slice per packet, which is different from
slice_count.
Slice count represents the number of soft slices per
On 5/7/2023 7:15 PM, Bjorn Andersson wrote:
On Mon, May 08, 2023 at 01:06:13AM +, Leonard Lausen wrote:
This reverts commit e17af1c9d861dc177e5b56009bd4f71ace688d97.
Removing the delay of 100 units broke hot plug detection for USB-C displays on
qcom sc7180 lazor devices. Lazor uses mdss
On 5/4/2023 2:56 PM, Marijn Suijten wrote:
On 2023-04-12 16:25:20, Jessica Zhang wrote:
hdisplay for compressed images should be calculated as bytes_per_slice *
slice_count. Thus, use MSM DSC helper to calculate hdisplay for
dsi_timing_setup instead of directly using mode->hdisplay.
Changes
On 5/4/2023 12:59 PM, Dmitry Baryshkov wrote:
On 04/05/2023 22:50, Abhinav Kumar wrote:
On 5/4/2023 12:36 PM, Marijn Suijten wrote:
On 2023-05-04 11:25:44, Abhinav Kumar wrote:
Sure, if you really prefer a split I'd go for two patches:
1. Add the flag to the enum and catalog;
2. Add
On 5/4/2023 12:36 PM, Marijn Suijten wrote:
On 2023-05-04 11:25:44, Abhinav Kumar wrote:
Sure, if you really prefer a split I'd go for two patches:
1. Add the flag to the enum and catalog;
2. Add the ops guard (functional change).
Then don't forget to reword the commit message, following
On 5/4/2023 11:23 AM, Marijn Suijten wrote:
On 2023-05-04 20:53:33, Dmitry Baryshkov wrote:
On Thu, 4 May 2023 at 20:49, Marijn Suijten
wrote:
PP_BLK_TE is no longer there.
marcos -> macros.
On 2023-05-04 09:46:41, Kuogee Hsieh wrote:
At legacy chipsets, it required DPU_PINGPONG_DSC
it to my branch to test.
Validated writeback just in case with this, hence please use
Tested-by: Abhinav Kumar # sc7280
Dmitry Baryshkov (7):
drm/msm/dpu: merge dpu_encoder_init() and dpu_encoder_setup()
drm/msm/dpu: drop dpu_encoder_early_unregister
drm/msm/dpu: separate common
Add writeback support for sc7280. This was validated with kms_writeback
test case in IGT.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
b
On 5/2/2023 2:42 PM, Dmitry Baryshkov wrote:
On 03/05/2023 00:03, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both
On 5/2/2023 4:58 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:57, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Signed-off
On 5/2/2023 4:54 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:51, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
WB is not present on the device.
On 5/2/2023 4:15 PM, Dmitry Baryshkov wrote:
On Wed, 3 May 2023 at 02:04, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use
, this will not affect functionality of intf or
wb and cleans it up well , so I am fine with this. Hence,
Reviewed-by: Abhinav Kumar
One minor comment/question.
@@ -761,7 +761,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
struct dpu_encoder_phys_cmd *cmd_enc = NULL;
int
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 31 +--
On 5/2/2023 1:54 PM, Dmitry Baryshkov wrote:
On Tue, 2 May 2023 at 23:45, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
Signed-off-by: Dmitry Baryshkov
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
Signed-off-by: Dmitry Baryshkov
---
There are two reasons to have the debugfs removed in the early_unregister:
1) Today, registration
On 5/1/2023 2:27 PM, Dmitry Baryshkov wrote:
On 02/05/2023 00:22, Abhinav Kumar wrote:
On 5/1/2023 1:45 PM, Dmitry Baryshkov wrote:
On 01/05/2023 22:58, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no reason to split the dpu_encoder interface
On 5/1/2023 1:45 PM, Dmitry Baryshkov wrote:
On 01/05/2023 22:58, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no reason to split the dpu_encoder interface into separate
_init() and _setup() phases. Merge them into a single function.
I think the reason
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no reason to split the dpu_encoder interface into separate
_init() and _setup() phases. Merge them into a single function.
I think the reason for having this split was to pass a valid encoder to
the interface_modeset_init() and then
On 5/1/2023 11:56 AM, Dmitry Baryshkov wrote:
On 01/05/2023 21:49, Abhinav Kumar wrote:
On 4/29/2023 2:25 PM, Dmitry Baryshkov wrote:
The driver doesn't support hsic/memcolor and pcc SSPP subblocks.
Drop corresponding definitions.
Signed-off-by: Dmitry Baryshkov
---
Changes since v2
this should be dropped. Once that is fixed,
Reviewed-by: Abhinav Kumar
* @format_list: Pointer to list of supported formats
* @num_formats: Number of supported formats
* @virt_format_list: Pointer to list of supported formats for virtual planes
@@ -399,9 +396,6 @@ struct dpu_sspp_sub_blks
On 4/29/2023 12:45 PM, Dmitry Baryshkov wrote:
On Sat, 29 Apr 2023 at 11:43, Abhinav Kumar wrote:
On 4/28/2023 9:35 PM, Dmitry Baryshkov wrote:
On 29/04/2023 07:04, Abhinav Kumar wrote:
On 4/28/2023 8:21 PM, Dmitry Baryshkov wrote:
On Sat, 29 Apr 2023 at 05:50, Abhinav Kumar
wrote
On 4/28/2023 9:30 PM, Dmitry Baryshkov wrote:
On 29/04/2023 07:29, Abhinav Kumar wrote:
On 4/28/2023 7:42 PM, Dmitry Baryshkov wrote:
The driver doesn't support hsic/memcolor, pcc and igc SSPP subblocks.
Drop corresponding definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu
On 4/28/2023 9:35 PM, Dmitry Baryshkov wrote:
On 29/04/2023 07:04, Abhinav Kumar wrote:
On 4/28/2023 8:21 PM, Dmitry Baryshkov wrote:
On Sat, 29 Apr 2023 at 05:50, Abhinav Kumar
wrote:
On 4/28/2023 6:41 PM, Dmitry Baryshkov wrote:
On 29/04/2023 04:08, Abhinav Kumar wrote:
On 4/28
On 4/28/2023 7:42 PM, Dmitry Baryshkov wrote:
The driver doesn't support hsic/memcolor, pcc and igc SSPP subblocks.
Drop corresponding definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8
1 file changed, 8 deletions(-)
diff --git
On 4/28/2023 8:21 PM, Dmitry Baryshkov wrote:
On Sat, 29 Apr 2023 at 05:50, Abhinav Kumar wrote:
On 4/28/2023 6:41 PM, Dmitry Baryshkov wrote:
On 29/04/2023 04:08, Abhinav Kumar wrote:
On 4/28/2023 5:45 PM, Dmitry Baryshkov wrote:
On 29/04/2023 02:45, Kuogee Hsieh wrote:
Legacy DPU
On 4/28/2023 8:12 PM, Dmitry Baryshkov wrote:
On Sat, 29 Apr 2023 at 05:51, Abhinav Kumar wrote:
On 4/28/2023 7:46 PM, Dmitry Baryshkov wrote:
On Sat, 29 Apr 2023 at 02:45, Kuogee Hsieh wrote:
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated
of this change.
This seriel is rebase on [1], [2] and catalog fixes from [3].
[1]: https://patchwork.freedesktop.org/series/116851/
[2]: https://patchwork.freedesktop.org/series/116615/
[3]: https://patchwork.freedesktop.org/series/112332/
Abhinav Kumar (2):
drm/msm/dpu: add DSC 1.2 hw blocks
On 4/28/2023 6:41 PM, Dmitry Baryshkov wrote:
On 29/04/2023 04:08, Abhinav Kumar wrote:
On 4/28/2023 5:45 PM, Dmitry Baryshkov wrote:
On 29/04/2023 02:45, Kuogee Hsieh wrote:
Legacy DPU requires PP hardware block involved into setting up DSC
Nit: to be envolved
data path. This patch
On 4/28/2023 5:52 PM, Dmitry Baryshkov wrote:
On 29/04/2023 02:45, Kuogee Hsieh wrote:
During DSC preparation, add run time calculation to figure out what
usage modes, split mode and merge mode, is going to be setup.
This patch doesn't determine the mode. It changes programming of DSC
On 4/28/2023 5:30 PM, Dmitry Baryshkov wrote:
On 29/04/2023 02:45, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Reported-by: kernel test robot
What exactly was reported?
On 4/28/2023 5:45 PM, Dmitry Baryshkov wrote:
On 29/04/2023 02:45, Kuogee Hsieh wrote:
Legacy DPU requires PP hardware block involved into setting up DSC
Nit: to be envolved
data path. This patch add DDPU_PINGPONG_DSC feature bit to both
adds
PP_BLK and PP_BLK_TE so that both
On 4/28/2023 6:04 PM, Dmitry Baryshkov wrote:
On 29/04/2023 04:03, Abhinav Kumar wrote:
On 4/28/2023 5:35 PM, Dmitry Baryshkov wrote:
On 29/04/2023 02:45, Kuogee Hsieh wrote:
From: Abhinav Kumar
In preparation of calling ping-pong DSC related functions only
for chipsets which have
On 4/28/2023 5:35 PM, Dmitry Baryshkov wrote:
On 29/04/2023 02:45, Kuogee Hsieh wrote:
From: Abhinav Kumar
In preparation of calling ping-pong DSC related functions only
for chipsets which have such a design add the dsc blocks for the
chipsets for which DSC is present but was not added
change dspp -> DSPP in commit text
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/d
:
- drop IGC related code from dpu_hw_catalog too
- update commit text accordingly
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 10 --
2 files
Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
than DSPP_MSM8998_MASK, lets drop the latter.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp
which was auto added before
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1
dsi-controller-main: Document qcom,master-dsi
and qcom,sync-dual-dsi
https://gitlab.freedesktop.org/abhinavk/msm/-/commit/ca29699a57ec
Best regards,
--
Abhinav Kumar
weak lm pairings in msm8998 hw catalog
https://gitlab.freedesktop.org/abhinavk/msm/-/commit/686eb89b1036
Best regards,
--
Abhinav Kumar
missing writeback log_mask
https://gitlab.freedesktop.org/abhinavk/msm/-/commit/a432fc31f03d
Best regards,
--
Abhinav Kumar
r during unbind
https://gitlab.freedesktop.org/abhinavk/msm/-/commit/85c636284cb6
Best regards,
--
Abhinav Kumar
---
Changes in v2:
- pick up tags
- fix typo (need -> needs)
.../bindings/display/msm/dsi-controller-main.yaml| 12
1 file changed, 12 insertions(+)
Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI
bindings")
Reviewed-by: Abhinav Kumar
] dp_ctrl_push_idle: PUSH_IDLE pattern timedout
Other basic use-cases still seem to work fine hence add a
a module parameter to allow toggling psr enable/disable till
PSR related issues are hashed out with IGT.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 6 +-
1 file changed
On 4/27/2023 8:57 AM, Dmitry Baryshkov wrote:
On 26/04/2023 22:22, Abhinav Kumar wrote:
Since Gamma Correction (GC) block is currently unused, drop
related code from the dpu hardware catalog otherwise this
becomes a burden to carry across chipsets in the catalog.
Signed-off-by: Abhinav
xes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
Signed-off-by: Marijn Suijten
---
Reviewed-by: Abhinav Kumar
says the size of the PINGPONG block is 0xd4 and not 0"
from the commit text while applying, otherwise
Reviewed-by: Abhinav Kumar
uot;drm/msm/dpu: add support for SM8450")
Signed-off-by: Marijn Suijten
---
Reviewed-by: Abhinav Kumar
Sorry for the spam, this should have been v2, I have fixed that and
resent this series.
On 4/26/2023 12:20 PM, Abhinav Kumar wrote:
Gamma correction blocks (GC) are not used today so lets remove
the usage of DPU_DSPP_GC in the dspp flush to make it easier
to remove GC from the catalog.
We can
Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
than DSPP_MSM8998_MASK, lets drop the latter.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ++--
drivers/gpu/drm/msm
Inverse gamma correction blocks (IGC) are not used today so lets
remove the usage of DPU_DSPP_IGC in the dspp flush to make it easier
to remove IGC from the catalog.
We can add this back when IGC is properly supported in DPU with
one of the standard DRM properties.
Signed-off-by: Abhinav Kumar
Since Gamma Correction (GC) block is currently unused, drop
related code from the dpu hardware catalog otherwise this
becomes a burden to carry across chipsets in the catalog.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Link: https://lore.kernel.org/r/20230421224721.12738-2
Gamma correction blocks (GC) are not used today so lets remove
the usage of DPU_DSPP_GC in the dspp flush to make it easier
to remove GC from the catalog.
We can add this back when GC is properly supported in DPU with
one of the standard DRM properties.
Signed-off-by: Abhinav Kumar
Reviewed
Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
than DSPP_MSM8998_MASK, lets drop the latter.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ++--
drivers/gpu/drm/msm
Gamma correction blocks (GC) are not used today so lets remove
the usage of DPU_DSPP_GC in the dspp flush to make it easier
to remove GC from the catalog.
We can add this back when GC is properly supported in DPU with
one of the standard DRM properties.
Signed-off-by: Abhinav Kumar
Reviewed
Since Gamma Correction (GC) block is currently unused, drop
related code from the dpu hardware catalog otherwise this
becomes a burden to carry across chipsets in the catalog.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Link: https://lore.kernel.org/r/20230421224721.12738-2
Inverse gamma correction blocks (IGC) are not used today so lets
remove the usage of DPU_DSPP_IGC in the dspp flush to make it easier
to remove IGC from the catalog.
We can add this back when IGC is properly supported in DPU with
one of the standard DRM properties.
Signed-off-by: Abhinav Kumar
On 4/26/2023 12:08 PM, Marijn Suijten wrote:
On 2023-04-26 09:24:19, Abhinav Kumar wrote:
On 4/25/2023 4:05 PM, Marijn Suijten wrote:
According to downstream sources this DITHER sub-block sits at an offset
of 0xe0 with version 0x2. The PP_BLK_DITHER macro is _not_ used as
downstream
On 4/25/2023 4:05 PM, Marijn Suijten wrote:
According to downstream sources this DITHER sub-block sits at an offset
of 0xe0 with version 0x2. The PP_BLK_DITHER macro is _not_ used as
downstream still says the size of the PINGPONG block is 0xd4 and not 0.
the PINGPONG block size is 0x0
terrupt regions")
Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP")
Signed-off-by: Marijn Suijten
---
Reviewed-by: Abhinav Kumar
d ("drm/msm/dpu: add support for SM8450")
Signed-off-by: Marijn Suijten
Reviewed-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 4/25/2023 3:15 PM, Marijn Suijten wrote:
On 2023-04-25 14:55:56, Abhinav Kumar wrote:
I'll see whether I can include these fixes before sending v3 (got all
the other changes in and am all-ready to send it): is there any other
SoC you're seeing this issue on?
Thats alright, you can
On 4/25/2023 2:53 PM, Marijn Suijten wrote:
On 2023-04-25 14:37:21, Abhinav Kumar wrote:
On 4/25/2023 1:43 PM, Marijn Suijten wrote:
On 2023-04-25 09:47:30, Abhinav Kumar wrote:
On 4/25/2023 9:33 AM, Marijn Suijten wrote:
On 2023-04-25 09:18:58, Abhinav Kumar wrote:
On 4/24/2023 11
On 4/25/2023 1:43 PM, Marijn Suijten wrote:
On 2023-04-25 09:47:30, Abhinav Kumar wrote:
On 4/25/2023 9:33 AM, Marijn Suijten wrote:
On 2023-04-25 09:18:58, Abhinav Kumar wrote:
On 4/24/2023 11:54 PM, Marijn Suijten wrote:
On 2023-04-24 16:09:45, Abhinav Kumar wrote:
dither block
On 4/19/2023 7:41 AM, Arnaud Vrac wrote:
Match the values found in the downstream msm-4.4 kernel sde driver.
Signed-off-by: Arnaud Vrac
---
Reviewed-by: Abhinav Kumar
On 4/25/2023 2:09 PM, Dmitry Baryshkov wrote:
On Tue, 25 Apr 2023 at 19:11, Abhinav Kumar wrote:
On 4/25/2023 7:26 AM, Dmitry Baryshkov wrote:
On Tue, 25 Apr 2023 at 11:55, Marijn Suijten
wrote:
On 2023-04-25 10:54:47, Dmitry Baryshkov wrote:
On 25/04/2023 10:16, Marijn Suijten
On 4/25/2023 9:33 AM, Marijn Suijten wrote:
On 2023-04-25 09:18:58, Abhinav Kumar wrote:
On 4/24/2023 11:54 PM, Marijn Suijten wrote:
On 2023-04-24 16:09:45, Abhinav Kumar wrote:
dither block should be present on many other chipsets too but looks like
on sm8550 was enabling it. Not sure
On 4/24/2023 11:54 PM, Marijn Suijten wrote:
On 2023-04-24 16:09:45, Abhinav Kumar wrote:
dither block should be present on many other chipsets too but looks like
on sm8550 was enabling it. Not sure how it was validated there. But we
are enabling dither, even other chipsets have this block
On 4/25/2023 7:26 AM, Dmitry Baryshkov wrote:
On Tue, 25 Apr 2023 at 11:55, Marijn Suijten
wrote:
On 2023-04-25 10:54:47, Dmitry Baryshkov wrote:
On 25/04/2023 10:16, Marijn Suijten wrote:
On 2023-04-24 16:23:17, Abhinav Kumar wrote:
On 4/24/2023 3:54 PM, Dmitry Baryshkov wrote
in the topology. In the previous config the
reservation code could never find an lm pair without a matching feature
set.
Signed-off-by: Arnaud Vrac
Reviewed-by: Abhinav Kumar
On 4/17/2023 1:21 PM, Marijn Suijten wrote:
Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the
PINGPONG block and into the INTF. Implement the necessary callbacks in
the INTF block, and use these callbacks together with the INTF_TEAR
interrupts. Additionally, disable
and the #define keyword.
Signed-off-by: Marijn Suijten
---
Reviewed-by: Abhinav Kumar
jn Suijten
---
Reviewed-by: Abhinav Kumar
On 4/24/2023 3:25 PM, Marijn Suijten wrote:
On 2023-04-24 13:44:55, Abhinav Kumar wrote:
On 4/17/2023 1:21 PM, Marijn Suijten wrote:
These offsets do not fall under the MDP TOP block and do not fit the
comment right above. Move them to dpu_hw_interrupts.c next to the
repsective
On 4/24/2023 3:54 PM, Dmitry Baryshkov wrote:
On Tue, 25 Apr 2023 at 01:03, Marijn Suijten
wrote:
On 2023-04-21 16:25:15, Abhinav Kumar wrote:
On 4/21/2023 1:53 PM, Marijn Suijten wrote:
The Resource Manager already iterates over all available blocks from the
catalog, only to pass
On 4/24/2023 3:30 PM, Marijn Suijten wrote:
On 2023-04-24 13:53:13, Abhinav Kumar wrote:
On 4/17/2023 1:21 PM, Marijn Suijten wrote:
SM8550 only comes with a DITHER subblock inside the PINGPONG block,
hence the name and a block length of zero. However, the PP_BLK macro
name was typo'd
M8550")
Signed-off-by: Marijn Suijten
This change itself is fine, hence
Reviewed-by: Abhinav Kumar
one comment below
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
2 files changed, 9 insert
pport")
Signed-off-by: Marijn Suijten
This change itself is fine, hence
Reviewed-by: Abhinav Kumar
One comment below.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 3 ---
2 files changed, 4 insertions(+), 4 deletion
On 4/17/2023 1:21 PM, Marijn Suijten wrote:
No hardware beyond kona (sm8250) defines the TE2 PINGPONG sub-block
offset downstream. Even though neither downstream nor upstream utilizes
these registers in any way, remove the erroneous specification for
SC8280XP, SM8350 and SM8450 to prevent
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