Hi, YT:
On Mon, 2016-09-12 at 18:15 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-07 at 12:58 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > > This patch update enable/disable flow of DSI module and MIPI
Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> update connections for OVL, RDMA, BLS, DSI
>
> Signed-off-by: YT Shen
> ---
[snip...]
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 53065c7..0850aa4 100644
> --- a/
Hi, YT:
On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-07 at 10:33 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > > From: shaoming chen
> > >
> >
Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 78
> ++
> 1 file changed, 78 insertions(+)
>
[snip...]
>
> +st
Hi, YT:
On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote:
> Hi CK,
>
> On Wed, 2016-09-07 at 13:37 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> > > This patch add support for the Mediatek MT2701 DISP subsystem.
&
Hi, Bibby:
Sorry for the late reply.
On Wed, 2016-08-17 at 14:58 +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao
>
> Pixel clock should be 297MHz when resolution is 4K.
>
>From the code you modified, I think title should be: "Enlarge pll_rate
range from (, ) to (, )"
In description, you can ex
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
[snip...]
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> This patch update enable/disable flow of DSI module and MIPI TX module
>
> Signed-off-by: shaoming chen
> Signed-off-by: YT Shen
> ---
I think the description is too simple. Please briefly describe WHY of
this patch. The original enab
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 188
> +
> 1 file changed, 188 insertions(+)
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 76
> ++
> 1 file changed, 76 insertions(+)
>
[snip...]
>
> +st
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> update connections for OVL, RDMA, BLS, DSI
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +
> 1 file changed, 25 insertions(+)
>
[snip...]
> @@ -111,6 +119,9 @@ static unsigne
Hi, YT:
On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote:
> There are some hardware settings changed, between MT8173 & MT2701:
> DISP_OVL address offset changed, color format definition changed.
> DISP_RDMA fifo size changed.
> DISP_COLOR offset changed.
> MIPI_TX pll setting changed.
> And add pr
Hi, YT:
On Wed, 2016-08-10 at 15:24 +0800, YT Shen wrote:
> Hi CK,
>
> On Fri, 2016-08-05 at 18:08 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> > > From: shaoming chen
> > >
> >
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 76
>
> 1 file changed, 76 insertions(+)
>
> diff --git a/driver
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 261
>
> 1 file changed, 261 insertions(+)
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6 ++
> drivers/gpu/drm/mediatek/mtk_disp_
Hi, YT:
On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> This patch adds the device nodes for the DISP function blocks for MT2701
>
> Signed-off-by: YT Shen
> ---
> arch/arm/boot/dts/mt2701.dtsi | 86
> +
> 1 file changed, 86 insertions(+)
>
> diff
Hi, YT:
On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 286
>
> 1 file changed, 286 insertions(+)
Hi, YT:
On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 92
>
> 1 file changed, 92 insertions(+)
>
> diff --git a/driver
r did the driver
> respect any user configured src coordinates, so panning and such would
> have been totally broken. It should be all good now.
>
> Cc: CK Hu
> Cc: linux-mediatek at lists.infradead.org
> Signed-off-by: Ville Syrjälä
> ---
Acked-by:
Hi, Bibby:
On Fri, 2016-07-29 at 17:04 +0800, Bibby Hsieh wrote:
> From: Daniel Kurtz
>
> It is not actually useful to a mtk plane to know its zpos/index, so just
> remove this field.
>
> This let's us completely remove struct mtk_drm_plane in a follow up patch.
'let's us'? My English is not a
Hi, YT:
On Thu, 2016-07-28 at 15:17 +0800, YT Shen wrote:
> Hi Philipp, CK,
>
> On Thu, 2016-07-28 at 10:07 +0800, CK Hu wrote:
> > Hi, YT:
> >
> > On Wed, 2016-07-27 at 12:03 +0200, Philipp Zabel wrote:
> > > Am Dienstag, den 26.07.2016, 18:42
Hi, YT:
On Wed, 2016-07-27 at 12:03 +0200, Philipp Zabel wrote:
> Am Dienstag, den 26.07.2016, 18:42 +0800 schrieb YT Shen:
> > Hi CK,
> >
> > On Wed, 2016-07-20 at 14:53 +0800, CK Hu wrote:
> > > Hi, YT:
> > >
> > > Some comments inline.
> &g
Hi, Bibby:
On Mon, 2016-07-25 at 14:24 +0800, Bibby Hsieh wrote:
> Hi, CK,
>
> Thanks for your comments.
>
> On Wed, 2016-07-20 at 15:57 +0800, CK Hu wrote:
> > Hi, Bibby:
> >
> > Some comments inline.
> >
> > On Wed, 2016-07-20 at 12:03 +080
Hi, Bibby:
On Thu, 2016-07-21 at 11:21 +0800, Bibby Hsieh wrote:
> Hi, CK
>
> I'm appreciate your comments.
>
>
[snip...]
> > >
> > > @@ -469,7 +484,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct
> > > mtk_ddp_comp *ovl)
> > > if (state->pending_config) {
> > > mtk_dd
Hi, Bibby:
Some comments inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao
>
> Pixel clock should be 297MHz when resolution is 4K.
>
> Signed-off-by: Junzhi Zhao
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 184
> +++
Hi, Bibby:
One comment inline.
On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao
>
> In order to improve 4K resolution performance,
> we have to enhance the HDMI driving currend
> when clock rate is greater than 165MHz.
>
> Signed-off-by: Junzhi Zhao
> Signed-off-by: B
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6
> drivers/gpu/d
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi and mipi tx driver for mipi panel support
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 169
> ++--
> drivers/gp
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 322
>
> 1 file cha
Hi, YT:
Some comments inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 130
>
> 1 file changed, 130 insertions(+)
Hi, YT:
One comment inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6
> drivers/gpu/drm
Hi, YT:
One comment inline.
On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote:
> We need to acquire mutex before using the resources,
> and need to release it after finished.
> So we don't need to write registers in the blanking period.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediat
Hi, Bibby:
Some comments inline.
On Thu, 2016-07-07 at 15:37 +0800, Bibby Hsieh wrote:
> Some panels only accept bpc (bit per color) 6-bit.
> But, the default bpc in mt8173 display data path is 8-bit.
> If we didn't enable dithering function to convert bpc,
> display cannot show the smooth graysc
Hi, Bibby:
Some comments inline.
On Thu, 2016-07-07 at 15:37 +0800, Bibby Hsieh wrote:
> Apply gamma function to correct brightness values.
> It applies arbitrary mapping curve to compensate the
> incorrect transfer function of the panel.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/
gt; there had been no further comments and I sent the pull request as the
> > other sub-sys.
> >
> > I'm sorry for my mistake, I will re-arrange the tree for upstream.
> > Next time, I will check with maintainer by email first, and sent the
> > pull request.
> >
> It might be a bit hard to find out who's the maintainer considering
> MAINTAINERS has no entry for this driver.
>
> Looking at how things are going Philipp Zabel will be the more likely
> person for the task, yet I would be nice if someone from the Mediatek
> squad is helping him out - CK Hu perhaps ?
>
> Regards,
> Emil
I'm willing to be one of Mediatek DRM driver maintainer. I wish this
would make things easier.
Regards,
CK
Hi, YT:
One comment inline.
On Thu, 2016-06-09 at 00:03 +0800, YT Shen wrote:
> We need to acquire mutex before using the resources,
> and need to release it after finished.
> So we don't need to write registers in the blanking period.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediate
Hi, YT:
Some comments inline.
On Thu, 2016-06-09 at 00:03 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6
> drivers/gpu/d
Hi, YT:
One comment below.
On Fri, 2016-05-20 at 23:05 +0800, yt.shen at mediatek.com wrote:
> From: YT Shen
>
> There are some hardware settings changed, between MT8173 & MT2701:
> DISP_OVL address offset changed, color format definition changed.
> DISP_RDMA fifo size changed.
> DISP_COLOR off
Hi, YT:
Some comments below.
On Fri, 2016-05-20 at 23:05 +0800, yt.shen at mediatek.com wrote:
> From: YT Shen
>
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen
>
> +static void mtk_ddp_mux_sel(void __iome
Hi, YT:
On Thu, 2016-05-12 at 19:49 +0800, yt.shen at mediatek.com wrote:
> From: YT Shen
>
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701, and we have shadow
> register support here.
>
> Signed-off-by: YT Shen
> ---
> @@ -385,12 +422
Hi, Philipp:
On Thu, 2016-02-04 at 13:48 +0100, Philipp Zabel wrote:
> Am Donnerstag, den 04.02.2016, 14:37 +0800 schrieb CK Hu:
> > Hi Philipp:
> >
> > On Wed, 2016-02-03 at 12:01 +0100, Philipp Zabel wrote:
> > > Hi Daniel,
> > >
> >
> &g
Hi Philipp:
On Wed, 2016-02-03 at 12:01 +0100, Philipp Zabel wrote:
> Hi Daniel,
>
> > > +static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
> > > +{
> > > + if (!dsi->enabled)
> > > + return;
> > > +
> > > + if (dsi->panel) {
> > > + if (drm_panel_di
rm_bridge_remove(&ps_bridge->bridge);
+
+ return 0;
+}
+
+static const struct i2c_device_id ps8640_i2c_table[] = {
+ {"parade,ps8640", 0},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, ps8640_i2c_table);
+
+static const struct of_device_id ps8640_match[] = {
+ { .compatible = "parade,ps8640" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ps8640_match);
+
+static struct i2c_driver ps8640_driver = {
+ .id_table = ps8640_i2c_table,
+ .probe = ps8640_probe,
+ .remove = ps8640_remove,
+ .driver = {
+ .name = "parade,ps8640",
+ .owner = THIS_MODULE,
+ .of_match_table = ps8640_match,
+ },
+};
+module_i2c_driver(ps8640_driver);
+
+MODULE_AUTHOR("Jitao Shi ");
+MODULE_AUTHOR("CK Hu ");
+MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
From: Jitao Shi
Add documentation for DT properties supported by ps8640
DSI-eDP converter.
Signed-off-by: Jitao Shi
---
.../devicetree/bindings/video/bridge/ps8640.txt| 48
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/b
This patch is a DRM Driver for Mediatek SoC MT8173.
Now support one crtc with MIPI DSI interface.
We used GEM framework for buffer management and use iommu for
physically non-continuous memory.
Signed-off-by: CK Hu
---
drivers/gpu/drm/Kconfig |2 +
drivers/gpu/drm
This patch includes
1. Mediatek DRM Device binding
2. Mediatek DSI Device binding
3. Mediatek CRTC Main Device binding
4. Mediatek DDP Device binding
Signed-off-by: CK Hu
---
.../bindings/drm/mediatek/mediatek,crtc-main.txt | 38 ++
.../bindings/drm/mediatek/mediatek
d.org/pipermail/linux-mediatek/2015-March/58.html
2. add IOMMU dma_ops
cherry picked from git://linux-arm.org/linux-rm iommu/dma
commit d76a1911b02185bdc5f8b5525f9228cf266725c5
CK Hu (2):
dt-bindings: drm/mediatek: Add Mediatek DRM dts binding
drm/mediatek: Add DRM Driv
This patch adds a drm_bridge driver for the IT6151 MIPI to eDP
bridge chip.
Signed-off-by: CK Hu
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/it6151.c | 601
Add devicetree bindings for IT6151 MIPI to eDP bridge chip driver.
Signed-off-by: CK Hu
Signed-off-by: Jitao Shi
---
Documentation/devicetree/bindings/drm/bridge/it6151.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/bridge
This patch adds a drm_bridge driver for the IT6151 MIPI to eDP
bridge chip.
Signed-off-by: CK Hu
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/it6151.c | 601
Add devicetree bindings for IT6151 MIPI to eDP bridge chip driver.
---
Documentation/devicetree/bindings/drm/bridge/it6151.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/bridge/it6151.txt
diff --git a/Documentation/devicetree/b
701 - 752 of 752 matches
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