define
- use devm_clk_get(>dev, "tcpdcore")
- add extcon node description
- add #sound-dai-cells description
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
---
.../bindings/display/rockchip/cdn-dp-rockchip.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/cdn
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/Kconfig| 9 +
drivers/gpu/drm/rockchip/Makefile
,
this branch has no rk3399.dtsi, so the patch about dts is not included
in this series.
Chris Zhong (6):
phy: Add USB Type-C PHY driver for rk3399
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
drm/rockchip: vop: add cdn DP support for rk3399
Documentation: bindings: add
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
---
.../bindings/display/rockchip/cdn-dp-rockchip.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/cdn
/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/Kconfig| 9 +
drivers/gpu/drm/rockchip/Makefile
about dts is not included
in this series.
Chris Zhong (6):
phy: Add USB Type-C PHY driver for rk3399
Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
drm/rockchip: vop: add cdn DP support for rk3399
Documentation: bindings: add dt documentation for cdn DP controller
ASoC: cdn
i, pre;
> unsigned long mpclk, pllref, tmp;
> unsigned int m = 1, n = 1, target_mbps = 1000;
> unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
> + int bpp;
>
> bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> if (bpp < 0) {
Reviewed-by: Chris Zhong
Thanks
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Changes in v7.2:
- make sure disable clk when drm_panel_prepare err (Mark Yao)
Changes in v7:
- modify the config to tristate for modules build (Mark
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Changes in v7.1:
- make sure disable clk when drm_panel_prepare err (Mark Yao)
Changes in v7:
- modify the config to tristate for modules build (Mark
Hi Mark
On 01/06/2016 09:48 AM, Mark yao wrote:
> On 2015å¹´12æ23æ¥ 11:43, Chris Zhong wrote:
>> +static int dw_mipi_dsi_register(struct drm_device *drm,
>> + struct dw_mipi_dsi *dsi)
>> +{
>> +struct drm_encoder *encoder = >encoder
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Changes in v7:
- modify the config to tristate for modules build (Mark Yao)
- Pass NULL 'name' to drm_encoder_init() to fix compile err (Mark Yao
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
o bindings/display/rockchip/
Chris Zhong (5):
drm/rockchip: return a true clock rate to adjusted_mode
Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
drm: rockchip: Support Synopsys DW MIPI DSI
ARM: dts: rockchip: add rk3288 mipi_dsi nodes
ARM: dts: rockchip: add su
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v6.3:
- move the mipi_en gate to ockchip_drm_crtc_mode_config
Changes in v6.2:
- Remove the atomic feature check (Mark Yao)
Changes in v6.1:
- Add atomic API
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v6.2:
- Remove the atomic feature check (Mark Yao)
Changes in v6.1:
- Add atomic API support (Heiko Stübne)
Changes in v6:
- Do not use bridge driver
Hi Heiko
Thanks for your reminder.
I have post the v6.1 mipi patch with the atomic support.
<https://patchwork.kernel.org/patch/7881781/>
On 12/17/2015 05:29 PM, Heiko Stübner wrote:
> Hi Chris,
>
> Am Mittwoch, 16. Dezember 2015, 18:10:10 schrieb Chris Zhong:
>>
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v6.1:
- Add atomic API support (Heiko Stübne)
Changes in v6:
- Do not use bridge driver (Thierry Reding)
- Optimization the phy init sequence
Changes in v5
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v6:
- Do not use bridge driver (Thierry Reding)
- Optimization the phy init sequence
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
mode_fixup
Changes in v3:
- move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
Chris Zhong (5):
drm/rockchip: return a true clock rate to adjusted_mode
Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
drm: rockchip: Support Synopsys DW MIPI DSI
ARM: dts: roc
On 11/26/2015 04:04 PM, Thierry Reding wrote:
> On Thu, Nov 26, 2015 at 03:03:54PM +0800, Chris Zhong wrote:
>> Hi Thierry
>>
>> Thanks for your feedback.
>>
>>
>> On 11/21/2015 12:07 AM, Thierry Reding wrote:
>>> On Fri, Nov 20, 2015 at 04:15:
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip
add Synopsys DesignWare MIPI DSI host controller driver support.
Signed-off-by: Chris Zhong
Signed-off-by: Liu Ying
---
Changes in v5:
Adviced by Thierry
- use hyphens instead of underscore
- use encoder in drm_bridge
- reformatting the dptdin table
- use readx_poll_timeout to check register
Check the validity of post_disable/pre_enable in bridge->funcs before
call them.
Signed-off-by: Chris Zhong
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/drm_bridge.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
- move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
Changes in v2:
- add the mipi clk id in a single patch
Chris Zhong (9):
clk: rockchip: add id for mipidsi sclk on rk3288
clk: rockchip: add mipidsi clocks on rk3288
drm/rockchip: return a true clock rate to adjusted_mode
drm:
Hi Thierry
Thanks for your feedback.
On 11/21/2015 12:07 AM, Thierry Reding wrote:
> On Fri, Nov 20, 2015 at 04:15:32PM +0800, Chris Zhong wrote:
>> add Synopsys DesignWare MIPI DSI host controller driver support.
>>
>> Signed-off-by: Chris Zhong
>> ---
>>
&g
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion
This binding specifies a set of common properties for display panels. It
can be used as a basis by bindings for specific panels.
Bindings for three specific panels are provided to show how the
simple panel binding can be used.
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v4
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
Changes in v4:
Alphabetically arranged the name
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 34
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v4: None
Changes in v3:
move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
Changes in v2: None
.../display/rockchip/dw_mipi_dsi_rockchip.txt
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile
add Synopsys DesignWare MIPI DSI host controller driver support.
Signed-off-by: Chris Zhong
---
Changes in v4:
eliminate some warnning
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge
From: Liu Ying <ying@freescale.com>
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
---
Changes in v4:
remove gpr property from example, since it is noused now.
add the descr
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/inclu
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
---
Changes in v4:
use
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk
Adds a new id for the sclk supplying the mipidsi on rk3288 socs.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2:
add the mipi clk id in a single patch
include/dt-bindings/clock/rk3288-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt
isplay/bridge
move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
move boe,tv080wum-nl0.txt to bindings/display/panel/
Changes in v2:
add the mipi clk id in a single patch
As Thierry.Reding comment, add a documentation for this panel.
Chris Zhong (11):
clk: rockchip: add id for mipids
Hi Emil
On 11/19/2015 10:41 PM, Emil Velikov wrote:
> On 19 November 2015 at 03:35, Chris Zhong wrote:
>> The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller
>> IP. This series adds support for a Synopsys DesignWare MIPI DSI host
>> controller DRM bridge
On 11/19/2015 03:08 PM, Mark yao wrote:
> On 2015å¹´11æ19æ¥ 11:35, Chris Zhong wrote:
>> +
>> +/*
>> + * Sometimes the clock driver can not set a accurate clock_rate
>> for vop,
>> + * get the true rate of vop_dclk
This binding specifies a set of common properties for display panels. It
can be used as a basis by bindings for specific panels.
Bindings for three specific panels are provided to show how the
simple panel binding can be used.
Signed-off-by: Chris Zhong
---
Changes in v3:
move boe,tv080wum-nl0
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 33 +
1 file changed, 33 insertions(+)
diff --git
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers
add Synopsys DesignWare MIPI DSI host controller driver support.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/i
Sometimes the clock driver can not set a accurate clock_rate for vop,
get the true rate of vop_dclk and set it back to adjusted_mode, since
the mipi dsi driver need to use the clock to make the calculation of
Blanking.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
tation for this panel.
Chris Zhong (10):
clk: rockchip: add id for mipidsi sclk on rk3288
clk: rockchip: add mipidsi clocks on rk3288
drm/rockchip: return a true clock rate to adjusted_mode
drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
drm: rockchip: Support Synopsys DesignWar
Hi Rob
On 11/02/2015 11:06 PM, Rob Herring wrote:
> On Sat, Oct 31, 2015 at 7:56 AM, Chris Zhong wrote:
>
> Your subject should be more specific with the panel name.
I'll write more specific in subject next version.
>
>> This binding specifies a set of common properties
This binding specifies a set of common properties for display panels. It
can be used as a basis by bindings for specific panels.
Bindings for three specific panels are provided to show how the
simple panel binding can be used.
Signed-off-by: Chris Zhong
---
Changes in v2:
As Thierry.Reding
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip
add Synopsys DesignWare MIPI DSI host controller driver support.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/bridge/Kconfig |9 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi
Sometimes the clock driver can not set a accurate clock_rate for vop,
get the true rate of vop_dclk and set it back to adjusted_mode, since
the mipi dsi driver need to use the clock to make the calculation of
Blanking.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm
in v2:
add the mipi clk id in a single patch
add vendor prefix for boe
As Thierry.Reding comment, add a documentation for this panel.
Chris Zhong (11):
clk: rockchip: add id for mipidsi sclk on rk3288
clk: rockchip: add mipidsi clocks on rk3288
drm/rockchip: return a true clock rate to adjuste
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/panel/panel-simple.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
add Synopsys DesignWare MIPI DSI host controller driver support.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 ++
include/drm/bridge
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f
Sometimes the clock driver can not set a accurate clock_rate for vop,
get the true rate of vop_dclk and set it back to adjusted_mode, since
the mipi dsi driver need to use the clock to make the calculation of
Blanking.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
only use the MIPI DSI video mode.
The MIPI DSI feature is tested on rk3288 evb board, backport them to
chrome os kernel v3.14, and it can display normally.
This patchset is base on the patchset from Ying.liu at freescale.com.
<http://www.spinics.net/lists/dri-devel/msg77181.html>
Chris Zh
201 - 267 of 267 matches
Mail list logo
