Re: [PATCH v2 5/7] drm/msm/adreno: Add A702 support

On Fri, Feb 23, 2024 at 9:28 PM Konrad Dybcio wrote: > > The A702 is a weird mix of 600 and 700 series.. Perhaps even a > testing ground for some A7xx features with good ol' A6xx silicon. > It's basically A610 that's been beefed up with some new registers > and hw features (like APRIV!), that was

Re: [PATCH v5 09/18] drm/msm: import A6xx XML display registers database

On Mon, Apr 1, 2024 at 3:52 AM Dmitry Baryshkov wrote: > > Import Adreno registers database for A6xx from the Mesa, commit > 639488f924d9 ("freedreno/registers: limit the rules schema"). > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4970 >

Re: drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:843:6: error: variable 'out' set but not used

On Tue, Mar 26, 2024 at 7:47 PM Dmitry Baryshkov wrote: > > On Tue, 26 Mar 2024 at 21:32, Abhinav Kumar wrote: > > > > > > > > On 3/26/2024 12:10 PM, Dmitry Baryshkov wrote: > > > On Tue, 26 Mar 2024 at 20:31, Abhinav Kumar > > > wrote: > > >> > > >> > > >> > > >> On 3/26/2024 11:19 AM, Dmitry

Re: [PATCH] drm/msm/a6xx: specify UBWC config for sc7180

eck. > > Rather than adding the check to a6xx_set_ubwc_config(), fill in the > UBWC config for a618 (based on readings from SC7180). > > Reported-by: Leonard Lausen > Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 > Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config s

Re: [PATCH] drm/msm/a6xx: skip programming of UBWC registers for a618

k. Thus it ends up rewriting hardware registers with the default > (incorrect) values. Add the !a618 check to this function. > > Reported-by: Leonard Lausen > Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 > Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config setting