Hi,
On 2/9/21 9:13 AM, Thomas Zimmermann wrote:
> Hi
>
> Am 08.02.21 um 18:43 schrieb Hans de Goede:
>> Hi,
>>
>> On 2/8/21 2:50 PM, Thomas Zimmermann wrote:
>>> (was: drm/vboxvideo: Vmap/vunmap cursor BO in prepare_fb and cleanup_fb)
>>>
>>&g
m using VboxSVGA graphics
and I've not found any problems:
Tested-by: Hans de Goede
Regards,
Hans
>
> drivers/gpu/drm/drm_gem_atomic_helper.c | 148 +++-
> drivers/gpu/drm/vboxvideo/vbox_mode.c | 28 ++---
> include/drm/drm_gem_atomic_helper.h |
Hi,
On 2/4/21 11:36 AM, Daniel Vetter wrote:
> On Thu, Feb 4, 2021 at 11:19 AM Patrik Jakobsson
> wrote:
>>
>> On Wed, Feb 3, 2021 at 1:00 PM Andy Shevchenko
>> wrote:
>>>
>>> On Tue, Jan 26, 2021 at 5:25 PM Patrik Jakobsson
>>> wrote:
On Tue, Jan 26, 2021 at 1:37 PM Andy Shevchenko
Hi,
On 2/3/21 12:14 PM, Thomas Zimmermann wrote:
> Hi
>
> Am 03.02.21 um 11:44 schrieb Daniel Vetter:
>> On Wed, Feb 03, 2021 at 11:34:21AM +0100, Thomas Zimmermann wrote:
>>> Hi
>>>
>>> Am 03.02.21 um 11:29 schrieb Daniel Vetter:
On Wed, Jan 27, 2021 at 03:05:03PM +0100, Thomas Zimmermann
Hi,
On 2/3/21 10:54 AM, Andy Shevchenko wrote:
> On Tue, Jan 26, 2021 at 4:23 PM Hans de Goede wrote:
>> On 1/26/21 1:38 PM, Andy Shevchenko wrote:
>>> Hi guys,
>>>
>>> This is first part of Intel MID outdated platforms removal. It's collected
>>&g
:00:02.0: [drm] failed to retrieve link info, disabling
eDP
Indicating that everything is working as it should.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i
Factor the code to check if a pipe is currently enabled out of
assert_pipe() and put it in a new intel_pipe_is_enabled() helper,
so that it can be re-used without copy-pasting it.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_display.c | 20 ++--
drivers
Hi,
On 1/26/21 9:54 PM, Andy Shevchenko wrote:
> On Tue, Jan 26, 2021 at 8:33 PM Hans de Goede wrote:
>> On 1/26/21 6:14 PM, Andy Shevchenko wrote:
>>> On Tue, Jan 26, 2021 at 6:55 PM Patrik Jakobsson
>>> wrote:
>>>> On Tue, Jan 26, 2021 at 4:51 PM Andy Sh
Hi,
On 1/26/21 6:14 PM, Andy Shevchenko wrote:
> On Tue, Jan 26, 2021 at 6:55 PM Patrik Jakobsson
> wrote:
>> On Tue, Jan 26, 2021 at 4:51 PM Andy Shevchenko
>> wrote:
>>>
>>> On Tue, Jan 26, 2021 at 5:25 PM Patrik Jakobsson
>>> wrote:
On Tue, Jan 26, 2021 at 1:37 PM Andy Shevchenko
Hi,
On 1/26/21 1:38 PM, Andy Shevchenko wrote:
> Hi guys,
>
> This is first part of Intel MID outdated platforms removal. It's collected
> into
> immutable branch with a given tag, please pull to yours subsystems.
>
> (All changes are tagged by the respective maintainers)
>
> Thanks,
>
>
Hi,
On 1/20/21 10:18 PM, Hans de Goede wrote:
> Hi,
>
> On 1/20/21 9:56 PM, Jared Baldridge wrote:
>> The OneGX1 Pro has a fairly unique combination of generic strings,
>> but we additionally match on the BIOS date just to be safe.
>>
>> Signed-off-by: Jared Ba
Hi,
On 1/20/21 9:56 PM, Jared Baldridge wrote:
> The OneGX1 Pro has a fairly unique combination of generic strings,
> but we additionally match on the BIOS date just to be safe.
>
> Signed-off-by: Jared Baldridge
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede
Hi,
On 1/7/21 6:04 PM, Daniel Vetter wrote:
> Hi Hans,
>
> On Tue, Dec 29, 2020 at 02:02:30PM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 12/28/20 7:39 PM, Peter Robinson wrote:
>>> The info message was showing the mapped address for the framebuffer. To
Hi,
On 1/15/21 1:14 PM, Christian König wrote:
> Hans do you have any more comments or a tested-by?
Sorry, I've been busy chasing after another 5.11 regression,
no comments, also no tested-by, but I do fully expect this to solve
the issue.
> Otherwise I push it to drm-misc-fixes today.
That
Hi,
On 1/13/21 9:25 AM, Christian König wrote:
> Hi Hans,
>
> Am 12.01.21 um 19:32 schrieb Hans de Goede:
>> GFP_TRANSHUGE_LIGHT includes __GFP_HIGHMEM and combining
>> __GFP_HIGHMEM with __GFP_DMA32 is not allowed.
>>
>> So we must not set add GFP_TRAN
nd
hisilicon/hibmc drivers.
Cc: Christian König
Fixes: d099fc8f540a ("drm/ttm: new TT backend allocation pool v3")
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/ttm/ttm_pool.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c
Hi,
On 11/24/20 4:49 PM, Ville Syrjälä wrote:
> On Wed, Nov 18, 2020 at 01:40:58PM +0100, Hans de Goede wrote:
>> Commit 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode")
>> added an intel_dsi_msleep() helper which skips sleeping if the
>> MIP
ch looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
> ---
> drivers/video/fbdev/simplefb.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/video/fbdev/simplefb.c b/drivers/video/fbdev/simplefb.c
> index 533a047d07a2..62f0ded70
Hi,
On 11/18/20 1:40 PM, Hans de Goede wrote:
> Commit 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode")
> added an intel_dsi_msleep() helper which skips sleeping if the
> MIPI-sequences have a version of 3 or newer and the panel is in vid-mode;
> and it mov
Hi,
On 10/27/20 2:51 PM, Hans de Goede wrote:
> Add missing pci_iounmap() calls to properly unmap the memory on
> probe-failure and remove.
>
> Reported-by: kernel test robot
> Reported-by: Dan Carpenter
> Signed-off-by: Hans de Goede
For some reason the spam-filter used
s: 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode")
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/vlv_dsi.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i
Hi Daniel,
Quick self intro: I have take over drivers/platform/x86
maintainership from Andy; and I'm working my way through
the backlog of old patches in patchwork:
https://patchwork.kernel.org/project/platform-driver-x86/list/
On 9/2/20 7:38 PM, Daniel Dadap wrote:
> Some upcoming notebook
Hi,
On 11/3/20 12:30 PM, Thomas Zimmermann wrote:
> Hi
>
> Am 03.11.20 um 12:09 schrieb Hans de Goede:
>> Hi,
>>
>> On 11/3/20 11:36 AM, Thomas Zimmermann wrote:
>>> The drivers gm12u320 and udl operate on USB devices. They leave the PCI
>>> device
: Add USB helpers
> drm/tiny/gm12u320: Retrieve USB device from struct drm_device.dev
> drm/udl: Retrieve USB device from struct drm_device.dev
Thanks.
The entire series looks good to me:
Reviewed-by: Hans de Goede
Note you may want to wait with pushing this to drm-misc until t
Hi,
On 11/1/20 6:41 PM, rwri...@hpe.com wrote:
> From: Randy Wright
>
> For several months, I've been experiencing GPU hangs when starting
> Cinnamon on an HP Pavilion Mini 300-020 if I try to run an upstream
> kernel. I reported this recently in
>
Add missing pci_iounmap() calls to properly unmap the memory on
probe-failure and remove.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/vboxvideo/vbox_main.c | 23 ---
1 file changed, 16 insertions(+), 7
Hi,
On 10/22/20 12:57 PM, Thomas Zimmermann wrote:
> Hi Hans
>
> On 22.10.20 12:17, Hans de Goede wrote:
>> Hi,
>>
>> On 10/22/20 11:30 AM, Thomas Zimmermann wrote:
>>> Hi
>>>
>>> On 22.10.20 11:20, Hans de Goede wrote:
>>&
Hi,
On 10/22/20 11:30 AM, Thomas Zimmermann wrote:
> Hi
>
> On 22.10.20 11:20, Hans de Goede wrote:
>> Hi,
>>
>> On 10/21/20 3:07 PM, Thomas Zimmermann wrote:
>>> The drivers gm12u320 and udl operate on USB devices. They leave the
>>> PCI device
in struct drm_device.udev
> drm/udl: Store USB device in struct drm_device.udev
This series looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
>
> drivers/gpu/drm/tiny/gm12u320.c | 52 +
> drivers/gpu/drm/udl/udl_connector.c | 8 ++--
Hi Tom,
Quick self intro: I have take over drivers/platform/x86
maintainership from Andy.
On 10/17/20 6:09 PM, t...@redhat.com wrote:
> From: Tom Rix
>
> This is a upcoming change to clean up a new warning treewide.
> I am wondering if the change could be one mega patch (see below) or
> normal
helpers. Vboxvideo was the
last user of these internal functions.
Signed-off-by: Thomas Zimmermann
Nice cleanup.
I've given this a test-run in an actual VirtualBox vm, focussing on
cursor sprite changes and I don't see any regressions, so:
Tested-by: Hans de Goede
Thomas, I assume that you
Hi,
On 9/8/20 1:04 PM, Stephen Rothwell wrote:
Hi Hans,
On Tue, 8 Sep 2020 10:22:06 +0200 Hans de Goede wrote:
On 9/8/20 6:00 AM, Stephen Rothwell wrote:
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/display/intel_panel.c
between commit
Hi Stephen,
On 9/8/20 6:00 AM, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/display/intel_panel.c
between commit:
f8bd54d21904 ("drm/i915: panel: Use atomic PWM API for devs with an external PWM
controller")
Hi,
On 9/3/20 2:56 PM, Andy Shevchenko wrote:
On Thu, Sep 03, 2020 at 03:48:16PM +0300, Andy Shevchenko wrote:
On Thu, Sep 03, 2020 at 01:23:27PM +0200, Hans de Goede wrote:
the question is do we need to have similar in acpi_lpss.c?
For example,
static const struct lpss_device_desc
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use DIV_ROUND_UP_ULL because pwm_state.period and .duty_cycle are now u64
de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 27 ++
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 4072d7062efd..df7472a3b9f8 100644
--- a/drivers/gpu/drm
Replace the enable, disable and config pwm_ops with an apply op,
to support the new atomic PWM API.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use do_div when calculating level because pwm_state.period
the minimum level.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 5a13089d2fc0
be honored.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-crc.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 44ec7d5b63e1..81232da0c767 100644
--- a/drivers/pwm
the
PWM_OUTPUT_ENABLE bit. This is fixed by an earlier patch in this series.
After the dropping of this workaround, the usleep call, which seems
unnecessary to begin with, has no useful effect anymore, so drop that too.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
Changes in v7:
- Fix
_ONCE flag and setting that for the CHT PWM controllers.
Acked-by: Rafael J. Wysocki
Signed-off-by: Hans de Goede
---
Changes in v2:
- Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX
---
drivers/acpi/acpi_lpss.c | 21 +
1 file changed, 17 insertions(+), 4
.
Honoring the VBT specified PWM frequency will also hopefully fix the
various bug reports which we have received about users perceiving the
backlight to flicker after a suspend/resume cycle.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
.../drm/i915/display/intel_display_types.h| 1
setting a divider of 128 (register-value 127).
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set
to reduce the amount of churn in the patch-set a bit
---
drivers/pwm/pwm
it again on re-enable.
Acked-by: Uwe Kleine-König
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Remove paragraph about tri-stating the output from the commit message,
we don't have a datasheet so this was just an unfounded guess
- 1).
Fixes: 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit")
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v5:
- Use clamp_val(... instead of clam_t(unsigned long long, ...
Changes in v3:
- Change upper
Ideapad Miix 310 and 320 models
and various Medion models.
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v10:
- Fixup some wording / mistakes in the commit message
Changes in v9:
- This is a new patch in v9 of this series
---
drivers/pwm/pwm-lpss.c | 21
/ duty_cycle calculations to take the
extra division by 256 into account.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Use NSEC_PER_USEC instead of adding a new (non-sensical) NSEC_PER_MHZ define
---
drivers/pwm/pwm-crc.c | 6 +++---
1 file
parameter to
the new pwm_lpss_prepare_enable() helper, which allows using it in that
path too.
Suggested-by: Andy Shevchenko
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-lpss.c | 45 --
1 file ch
wm: lpss: Avoid potential overflow of base_unit")
Reviewed-by: Andy Shevchenko
Acked-by: Uwe Kleine-König
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Add Fixes tag
- Add Reviewed-by: Andy Shevchenko tag
---
drivers/pwm/pwm-lpss.c | 6 +++---
1 file changed, 3 insert
the update
bit, which is necessary to get the controller to actually use/apply
the restored base-unit and on-time-div values.
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v9:
- This is a new patch in v9 of this series
---
drivers/pwm/pwm-lpss-platform.c | 1 -
drivers/pwm/pwm
rail PWM controllers will be resumed in the
no-irq phase. Together with the device-link added by the pwm-get this
ensures that the PWM controller will be on when the troublesome PS0
method runs, which stops it from poking the PWM controller.
Acked-by: Rafael J. Wysocki
Signed-off-by: Hans de Goede
---
Hi All,
Here is hopefully the last version of this series, as everything seems
to be ready for merging this now.
The only difference from v9 is correcting some mistakes in the commit-msg of:
[PATCH v10 06/17] pwm: lpss: Make pwm_lpss_apply() not rely on hardware state
I plan is to push the
Hi,
On 9/3/20 12:59 PM, Thierry Reding wrote:
On Thu, Sep 03, 2020 at 12:51:03PM +0200, Hans de Goede wrote:
Before this commit pwm_lpss_apply() was making 2 assuming
2 pre-conditions were met by the existing hardware state:
I think that "making 2" is too much.
You're righ
.
Honoring the VBT specified PWM frequency will also hopefully fix the
various bug reports which we have received about users perceiving the
backlight to flicker after a suspend/resume cycle.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
.../drm/i915/display/intel_display_types.h| 1
parameter to
the new pwm_lpss_prepare_enable() helper, which allows using it in that
path too.
Suggested-by: Andy Shevchenko
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-lpss.c | 45 --
1 file ch
setting a divider of 128 (register-value 127).
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set
to reduce the amount of churn in the patch-set a bit
---
drivers/pwm/pwm
Ideapad Miix 310 and 320 models
and various Medion models.
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-lpss.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index 8a136ba2a583..9c5c7217c9b6 100644
the update
bit, which is necessary to get the controller to actually use/apply
the restored base-unit and on-time-div values.
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-lpss-platform.c | 1 -
drivers/pwm/pwm-lpss.c | 24
drivers/pwm/pwm-lpss.h | 3 ---
3
the
PWM_OUTPUT_ENABLE bit. This is fixed by an earlier patch in this series.
After the dropping of this workaround, the usleep call, which seems
unnecessary to begin with, has no useful effect anymore, so drop that too.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
Changes in v7:
- Fix
the minimum level.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 5a13089d2fc0
be honored.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-crc.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 44ec7d5b63e1..81232da0c767 100644
--- a/drivers/pwm
Replace the enable, disable and config pwm_ops with an apply op,
to support the new atomic PWM API.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use do_div when calculating level because pwm_state.period
/ duty_cycle calculations to take the
extra division by 256 into account.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Use NSEC_PER_USEC instead of adding a new (non-sensical) NSEC_PER_MHZ define
---
drivers/pwm/pwm-crc.c | 6 +++---
1 file
de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 27 ++
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 4072d7062efd..df7472a3b9f8 100644
--- a/drivers/gpu/drm
it again on re-enable.
Acked-by: Uwe Kleine-König
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Remove paragraph about tri-stating the output from the commit message,
we don't have a datasheet so this was just an unfounded guess
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use DIV_ROUND_UP_ULL because pwm_state.period and .duty_cycle are now u64
- 1).
Fixes: 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit")
Reviewed-by: Andy Shevchenko
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v5:
- Use clamp_val(... instead of clam_t(unsigned long long, ...
Changes in v3:
- Change upper
rail PWM controllers will be resumed in the
no-irq phase. Together with the device-link added by the pwm-get this
ensures that the PWM controller will be on when the troublesome PS0
method runs, which stops it from poking the PWM controller.
Acked-by: Rafael J. Wysocki
Signed-off-by: Hans de Goede
---
_ONCE flag and setting that for the CHT PWM controllers.
Acked-by: Rafael J. Wysocki
Signed-off-by: Hans de Goede
---
Changes in v2:
- Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX
---
drivers/acpi/acpi_lpss.c | 21 +
1 file changed, 17 insertions(+), 4
wm: lpss: Avoid potential overflow of base_unit")
Reviewed-by: Andy Shevchenko
Acked-by: Uwe Kleine-König
Acked-by: Thierry Reding
Signed-off-by: Hans de Goede
---
Changes in v3:
- Add Fixes tag
- Add Reviewed-by: Andy Shevchenko tag
---
drivers/pwm/pwm-lpss.c | 6 +++---
1 file changed, 3 insert
Hi All,
So the bug-fix which prompted v8, lead to some discussion about the pwm-lpss
suspend/resume code. So as discussed this version drops the following 2
patches:
[PATCH v8 06/17] pwm: lpss: Use pwm_lpss_restore() when restoring state on
resume
[PATCH v8 07/17] pwm: lpss: Always update state
Hi,
On 8/31/20 3:15 PM, Thierry Reding wrote:
On Mon, Aug 31, 2020 at 01:46:28PM +0200, Hans de Goede wrote:
Hi,
On 8/31/20 1:10 PM, Thierry Reding wrote:
On Sun, Aug 30, 2020 at 02:57:42PM +0200, Hans de Goede wrote:
Before this commit a suspend + resume of the LPSS PWM controller
would
Hi,
On 8/31/20 10:56 AM, Andy Shevchenko wrote:
On Sun, Aug 30, 2020 at 02:57:43PM +0200, Hans de Goede wrote:
This commit removes a check where we would skip writing the ctrl register
and then setting the update bit in case the ctrl register already contains
the correct values.
In a perfect
Hi,
On 8/31/20 1:10 PM, Thierry Reding wrote:
On Sun, Aug 30, 2020 at 02:57:42PM +0200, Hans de Goede wrote:
Before this commit a suspend + resume of the LPSS PWM controller
would result in the controller being reset to its defaults of
output-freq = clock/256, duty-cycle=100%, until someone
Hi,
On 8/31/20 1:13 PM, Thierry Reding wrote:
On Sun, Aug 30, 2020 at 02:57:43PM +0200, Hans de Goede wrote:
This commit removes a check where we would skip writing the ctrl register
and then setting the update bit in case the ctrl register already contains
the correct values.
In a perfect
Replace the enable, disable and config pwm_ops with an apply op,
to support the new atomic PWM API.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use do_div when calculating level because pwm_state.period and .duty_cycle
are now u64
Changes
the
PWM_OUTPUT_ENABLE bit. This is fixed by an earlier patch in this series.
After the dropping of this workaround, the usleep call, which seems
unnecessary to begin with, has no useful effect anymore, so drop that too.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
Changes in v7:
- Fix
/ duty_cycle calculations to take the
extra division by 256 into account.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v3:
- Use NSEC_PER_USEC instead of adding a new (non-sensical) NSEC_PER_MHZ define
---
drivers/pwm/pwm-crc.c | 6 +++---
1 file changed, 3 insertions
setting a divider of 128 (register-value 127).
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v3:
- Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set
to reduce the amount of churn in the patch-set a bit
---
drivers/pwm/pwm-crc.c | 17
be honored.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-crc.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 44ec7d5b63e1..81232da0c767 100644
--- a/drivers/pwm/pwm-crc.c
+++ b/drivers/pwm
the minimum level.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 5a13089d2fc0
.
Honoring the VBT specified PWM frequency will also hopefully fix the
various bug reports which we have received about users perceiving the
backlight to flicker after a suspend/resume cycle.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
.../drm/i915/display/intel_display_types.h| 1
apad Miix 310 and 320 models and
various Medion models.
Signed-off-by: Hans de Goede
---
Changes in v8:
- New patch in v8 of this patch-set
---
drivers/pwm/pwm-lpss.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index 9a740
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use DIV_ROUND_UP_ULL because pwm_state.period and .duty_cycle are now u64
Changes in v5:
- Fix
de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 27 ++
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 4072d7062efd..df7472a3b9f8 100644
--- a/drivers/gpu/drm
it again on re-enable.
Acked-by: Uwe Kleine-König
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v3:
- Remove paragraph about tri-stating the output from the commit message,
we don't have a datasheet so this was just an unfounded guess
---
drivers/pwm/pwm-crc.c | 4
parameter to
the new pwm_lpss_prepare_enable() helper, which allows using it in that
path too.
Suggested-by: Andy Shevchenko
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
drivers/pwm/pwm-lpss.c | 45 --
1 file changed, 26 insertions(+), 19
-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v8:
- Drop optimization to skip restore if current ctrl reg is the same as our saved
ctrl reg value (because this causes issues on some devices)
- Simplify pwm_lpss_restore_state() to not rely on the current state
- Modify commit
_ONCE flag and setting that for the CHT PWM controllers.
Acked-by: Rafael J. Wysocki
Signed-off-by: Hans de Goede
---
Changes in v2:
- Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX
---
drivers/acpi/acpi_lpss.c | 21 +
1 file changed, 17 insertions(+), 4
wm: lpss: Avoid potential overflow of base_unit")
Reviewed-by: Andy Shevchenko
Acked-by: Uwe Kleine-König
Signed-off-by: Hans de Goede
---
Changes in v3:
- Add Fixes tag
- Add Reviewed-by: Andy Shevchenko tag
---
drivers/pwm/pwm-lpss.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
- 1).
Fixes: 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit")
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v5:
- Use clamp_val(... instead of clam_t(unsigned long long, ...
Changes in v3:
- Change upper limit of clamp to (base_unit_range - 1)
-
Hi All,
Unfortunately while testing some unrelated things I found another issue with
this series related to the CHT ACPI GFX0._PS3 code poking the PWM controller
in unexpected ways.
This new version contains a new patch: "[PATCH v8 07/17] pwm: lpss: Always
update state and set update bit" fixing
rail PWM controllers will be resumed in the
no-irq phase. Together with the device-link added by the pwm-get this
ensures that the PWM controller will be on when the troublesome PS0
method runs, which stops it from poking the PWM controller.
Acked-by: Rafael J. Wysocki
Signed-off-by: Hans de Goede
---
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use DIV_ROUND_UP_ULL because pwm_state.period and .duty_cycle are now u64
Changes in v5:
- Fix
Replace the enable, disable and config pwm_ops with an apply op,
to support the new atomic PWM API.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use do_div when calculating level because pwm_state.period and .duty_cycle
are now u64
Changes
the minimum level.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 7fb162fac8a1
de Goede
---
drivers/gpu/drm/i915/display/intel_panel.c | 27 ++
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index bbde3b12c311..ec6b9d704542 100644
--- a/drivers/gpu/drm
.
Honoring the VBT specified PWM frequency will also hopefully fix the
various bug reports which we have received about users perceiving the
backlight to flicker after a suspend/resume cycle.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
.../drm/i915/display/intel_display_types.h| 1
the
PWM_OUTPUT_ENABLE bit. This is fixed by an earlier patch in this series.
After the dropping of this workaround, the usleep call, which seems
unnecessary to begin with, has no useful effect anymore, so drop that too.
Acked-by: Jani Nikula
Signed-off-by: Hans de Goede
---
Changes in v7:
- Fix
/ duty_cycle calculations to take the
extra division by 256 into account.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v3:
- Use NSEC_PER_USEC instead of adding a new (non-sensical) NSEC_PER_MHZ define
---
drivers/pwm/pwm-crc.c | 6 +++---
1 file changed, 3 insertions
701 - 800 of 1992 matches
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