On 27/06/2025 14:38, Jocelyn Falempe wrote:
On 32bits ARM, u64 divided by a constant is not optimized to a
multiply by inverse by the compiler [1].
So do the multiply by inverse explicitly for this architecture.
Gentle ping.
Best regards,
--
Jocelyn
Link: https://github.com/llvm/llvm
On 19/07/2025 20:23, Ville Syrjälä wrote:
On Wed, Jun 18, 2025 at 11:31:21AM +0200, Jocelyn Falempe wrote:
drm_panic draws in linear framebuffer, so it's easier to re-use the
current framebuffer, and disable tiling in the panic handler, to show
the panic screen.
This assumes that the alig
On 16/07/2025 23:48, Askar Safin wrote:
On Wed, 16 Jul 2025 02:00:56 +0400 Jocelyn Falempe
wrote ---
> Yes, that's the default if you use a drm driver like bochs with fbdev
Thank you for answer! I just tried kernel from drm-tip with this config with
drm_panic in qemu. A
On 15/07/2025 22:35, Askar Safin wrote:
On Tue, 15 Jul 2025 12:57:04 +0400 Jocelyn Falempe
wrote ---
> "Normal panics", is just the console logs through fbcon. The problem is
Thank you for answer! Is this possible to configure system such that fbcon
works norma
On 14/07/2025 02:04, Askar Safin wrote:
Are normal panics (i. e. not drm panics) still supposed to work with bochs?
"Normal panics", is just the console logs through fbcon. The problem is
that this is not designed to work in a panic context, so on some driver
it can work, but it's not reliabl
x27;s PCIE2MBOX feature, which
is unused.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_2600.c | 33 +
drivers/gpu/drm/ast/ast_post.h | 3 ---
2 files changed, 1 insertion(+), 35 dele
On 02/07/2025 15:12, Thomas Zimmermann wrote:
Set VGACRB6[5], which disables asynchronous sequencer resets via
VGASR0[1]. This was most likely an oversight when adding support
for Gen7. Aligns Gen7 with the earlier Gen4+.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed
function. Keep
this behavior for now.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_2000.c | 32 +++
drivers/gpu/drm/ast/ast_2100.c | 2 ++
drivers/gpu/drm/ast/ast_2300.c | 33
constants and helper macros for these cases. Also add a helper
macro for testing. Update Gen1 and Gen2+ accordingly.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_2000.c | 16
drivers/gpu/drm/ast/ast_2100
On 02/07/2025 15:12, Thomas Zimmermann wrote:
Declare struct ast_dramstruct in ast_post.h and remove its original
header file.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_2000.c| 2 +-
drivers/gpu/drm
a single change. The split simplifies both cases. Also move
the DRAM init tables for each Gen into the respective source
file. No changes to the overall logic.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/Makefile
.
Reviewed-by: Jocelyn Falempe
Also fix coding style in several places. No changes to the overall
logic.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/Makefile |1 +
drivers/gpu/drm/ast/ast_2300.c | 1295
drivers/gpu/drm/ast/ast_drv.h |3
.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/Makefile | 1 +
drivers/gpu/drm/ast/ast_2500.c| 567 ++
drivers/gpu/drm/ast/ast_dram_tables.h | 62 ---
drivers/gpu/drm/ast/ast_drv.c | 2 +-
drivers/gpu
On 02/07/2025 15:12, Thomas Zimmermann wrote:
Move POST code for Gen7+ to separate source file and hide it in
ast_2600_post(). There's not much going on here except for enabling
the DP transmitter chip.
Thanks, it looks good to me.
Only a cosmetic comment below.
Reviewed-by: Jocelyn Fa
On 02/07/2025 15:12, Thomas Zimmermann wrote:
Provide POST helpers in header file before splitting up the AST
POST code.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_post.c | 10 +-
drivers/gpu/drm/ast
ned-off-by: Jocelyn Falempe
---
Can this be merged through the drm-intel-next, as this is were the
offending commit was merged.
drivers/gpu/drm/ttm/ttm_bo_util.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index ad
-devel/c0a2771c-f3f5-4d4c-aa82-d673b3c5c...@gmail.com/
Fixes: 675008f196ca ("drm/panic: Use a decimal fifo to avoid u64 by u64 divide")
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/drm_panic_qr.rs | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git
On 27/06/2025 13:44, Miguel Ojeda wrote:
On Fri, Jun 27, 2025 at 11:41 AM Jocelyn Falempe wrote:
+/// On arm32 architecture, dividing an u64 by a constant will generate a call
+/// to __aeabi_uldivmod which is not present in the kernel.
+/// So use the multiply by inverse method for this
On 27/06/2025 13:36, Alice Ryhl wrote:
On Fri, Jun 27, 2025 at 11:41 AM Jocelyn Falempe wrote:
On 32bits ARM, u64 divided by a constant is not optimized to a
multiply by inverse by the compiler [1].
So do the multiply by inverse explicitly for this architecture.
Link: https://github.com/llvm
-devel/c0a2771c-f3f5-4d4c-aa82-d673b3c5c...@gmail.com/
Fixes: 675008f196ca ("drm/panic: Use a decimal fifo to avoid u64 by u64 divide")
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/drm_panic_qr.rs | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git
() has the same
signature as the other conversion functions, which is required for
further updates to drm_fb_blit(). Also makes the format-conversion
helper available to panic handlers, if necessary.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
On 25/06/2025 00:18, Jocelyn Falempe wrote:
On 24/06/2025 20:55, Andrei Lalaev wrote:
On 18.04.25 18:48, Jocelyn Falempe wrote:
On 32bits ARM, u64/u64 is not supported [1], so change the algorithm
to use a simple fifo with decimal digits as u8 instead.
This is slower but should compile on all
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/i915/display/intel_plane.c | 20
1 file change
On 24/06/2025 20:55, Andrei Lalaev wrote:
On 18.04.25 18:48, Jocelyn Falempe wrote:
On 32bits ARM, u64/u64 is not supported [1], so change the algorithm
to use a simple fifo with decimal digits as u8 instead.
This is slower but should compile on all architecture.
Link:
https://lore.kernel.org
The vaddr of the fbdev framebuffer is private to the struct
intel_fbdev, so this function is needed to access it for drm_panic.
Also the struct i915_vma is different between i915 and xe, so it
requires a few functions to access fbdev->vma->iomap.
Signed-off-by: Jocelyn Falempe
---
v2:
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++
.../drm/i915/display/intel_display_types.h| 2 ++
2 files ch
When the panic handler is called, configure the psr to send the full
framebuffer to the monitor, otherwise the panic screen is only
partially visible.
Signed-off-by: Jocelyn Falempe
---
v8:
* Added in v8
drivers/gpu/drm/i915/display/intel_plane.c | 7 +++
drivers/gpu/drm/i915/display
essing the
framebuffer, so this will be handled by the following patches.
Signed-off-by: Jocelyn Falempe
---
v4:
* Add support for Xe driver.
v6:
* Use struct intel_display instead of drm_i915_private for intel_atomic_plane.c
v7:
* Fix mismatch {} in intel_panic_flush() (Jani Nikula)
Implement both functions for i915 and xe, they prepare the work for
drm_panic support.
They both use kmap_try_from_panic(), and map one page at a time, to
write the panic screen on the framebuffer.
Signed-off-by: Jocelyn Falempe
---
v5:
* Use iosys_map for intel_bo_panic_map().
v7:
* Return
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
.../drm/i915/display/skl_universal_plane.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm
Encapsulate the struct intel_framebuffer into an xe_framebuffer
or i915_framebuffer, and allow to add specific fields for each
variant for the panic use-case.
This is particularly needed to have a struct xe_res_cursor available
to support drm panic on discrete GPU.
Signed-off-by: Jocelyn Falempe
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
v8:
* Pass the tiling function to intel_bo_panic_setup()
v10:
* Use the s
If the ttm bo is backed by pages, then it's possible to safely kmap
one page at a time, using kmap_try_from_panic().
Unfortunately there is no way to do the same with ioremap, so it
only supports the kmap case.
This is needed for proper drm_panic support with xe driver.
Signed-off-by: Jo
This allows driver to set some private data in get_scanout_buffer(),
and re-use them in set_pixel() callback.
Signed-off-by: Jocelyn Falempe
---
v10:
* Added in v10, to avoid static variables
include/drm/drm_panic.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm
d a struct xe_res_cursor
to support discrete GPU later.
Jocelyn Falempe (11):
drm/panic: Add a private field to struct drm_scanout_buffer
drm/i915/fbdev: Add intel_fbdev_get_map()
drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes
drm/i915/display: Add a disable_tiling() for
On 13/06/2025 15:20, Ryosuke Yasuoka wrote:
Add drm_panic moudle for bochs drm so that panic screen can be displayed
on panic.
I just pushed it to drm-misc-next, with the typo in the commit message
fixed.
Thanks,
--
Jocelyn
Signed-off-by: Ryosuke Yasuoka
---
drivers/gpu/drm/tiny/boch
Best regards,
--
Jocelyn
Best regards,
~Maarten
On 2025-06-18 11:31, Jocelyn Falempe wrote:
This adds drm_panic support for i915 and xe driver.
I've tested it on the 4 intel laptops I have at my disposal.
* Haswell with 128MB of eDRAM.
* Comet Lake i7-10850H
* Raptor Lake i7-1370P (wi
On 19/06/2025 08:37, Ryosuke Yasuoka wrote:
On Thu, Jun 19, 2025 at 3:12 PM Jocelyn Falempe wrote:
On 13/06/2025 15:20, Ryosuke Yasuoka wrote:
Add drm_panic moudle for bochs drm so that panic screen can be displayed
on panic.
Thanks for the patch, it's simple and looks good
On 13/06/2025 15:20, Ryosuke Yasuoka wrote:
Add drm_panic moudle for bochs drm so that panic screen can be displayed
on panic.
Thanks for the patch, it's simple and looks good to me.
Reviewed-by: Jocelyn Falempe
If no objections, I will push it next Monday.
Best regards,
--
Jo
inize. It also has the slight benefit of
removing a degree of freedom on which to bikeshed. Thus apply the
changes and enable the lint -- no functional change intended.
Thanks, it looks good to me, for the drm_panic_qr.rs part.
Acked-by: Jocelyn Falempe
Link: https://rust-lang.github.io/rust-c
On 18/06/2025 15:55, Christian König wrote:
On 6/18/25 11:31, Jocelyn Falempe wrote:
If the ttm bo is backed by pages, then it's possible to safely kmap
one page at a time, using kmap_try_from_panic().
Unfortunately there is no way to do the same with ioremap, so it
only supports the
When the panic handler is called, configure the psr to send the full
framebuffer to the monitor, otherwise the panic screen is only
partially visible.
Signed-off-by: Jocelyn Falempe
---
v8:
* Added in v8
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +++
drivers/gpu/drm/i915/display
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 20 +++
1 file change
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
v8:
* Pass the tiling function to intel_bo_panic_setup()
.../gpu/drm/i915/di
essing the
framebuffer, so this will be handled by the following patches.
Signed-off-by: Jocelyn Falempe
---
v4:
* Add support for Xe driver.
v6:
* Use struct intel_display instead of drm_i915_private for intel_atomic_plane.c
v7:
* Fix mismatch {} in intel_panic_flush() (Jani Nikula)
Implement both functions for i915 and xe, they prepare the work for
drm_panic support.
They both use kmap_try_from_panic(), and map one page at a time, to
write the panic screen on the framebuffer.
Signed-off-by: Jocelyn Falempe
---
v5:
* Use iosys_map for intel_bo_panic_map().
v7:
* Return
If the ttm bo is backed by pages, then it's possible to safely kmap
one page at a time, using kmap_try_from_panic().
Unfortunately there is no way to do the same with ioremap, so it
only supports the kmap case.
This is needed for proper drm_panic support with xe driver.
Signed-off-by: Jo
This allows driver to set some private data in get_scanout_buffer(),
and re-use them in set_pixel() callback.
Signed-off-by: Jocelyn Falempe
---
v10:
* Added in v10, to avoid static variables
include/drm/drm_panic.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
.../drm/i915/display/skl_universal_plane.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++
.../drm/i915/display/intel_display_types.h| 2 ++
2 files ch
in struct intel_framebuffer
(Maarten Lankhorst)
* Add error handling if i915_gem_object_panic_pages() returns NULL
* Declare struct drm_scanout_buffer instead of including
in intel_bo.h
Jocelyn Falempe (10):
drm/panic: Add a private field to struct drm_scanout_buffer
drm/i915/fbdev: Add intel_fbd
The vaddr of the fbdev framebuffer is private to the struct
intel_fbdev, so this function is needed to access it for drm_panic.
Also the struct i915_vma is different between i915 and xe, so it
requires a few functions to access fbdev->vma->iomap.
Signed-off-by: Jocelyn Falempe
---
v2:
On 12/06/2025 10:53, Thomas Zimmermann wrote:
Fix the compile-time warning
drivers/gpu/drm/mgag200/mgag200_ddc.c: warning: EXPORT_SYMBOL() is not used, but
#include is present
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers
On 12/06/2025 10:42, Thomas Zimmermann wrote:
Fix the compile-time warning
drivers/gpu/drm/ast/ast_mode.c: warning: EXPORT_SYMBOL() is not used, but #include
is present
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm
essing the
framebuffer, so this will be handled by the following patches.
Signed-off-by: Jocelyn Falempe
---
v4:
* Add support for Xe driver.
v6:
* Use struct intel_display instead of drm_i915_private for intel_atomic_plane.c
v7:
* Fix mismatch {} in intel_panic_flush() (Jani Nikula)
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
v8:
* Pass the tiling function to intel_bo_panic_setup()
.../gpu/drm/i915/di
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
.../drm/i915/display/skl_universal_plane.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm
When the panic handler is called, configure the psr to send the full
framebuffer to the monitor, otherwise the panic screen is only
partially visible.
Signed-off-by: Jocelyn Falempe
---
v8:
* Added in v8
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +++
drivers/gpu/drm/i915/display
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 20 +++
1 file change
If the ttm bo is backed by pages, then it's possible to safely kmap
one page at a time, using kmap_try_from_panic().
Unfortunately there is no way to do the same with ioremap, so it
only supports the kmap case.
This is needed for proper drm_panic support with xe driver.
Signed-off-by: Jo
Implement both functions for i915 and xe, they prepare the work for
drm_panic support.
They both use kmap_try_from_panic(), and map one page at a time, to
write the panic screen on the framebuffer.
Signed-off-by: Jocelyn Falempe
---
v5:
* Use iosys_map for intel_bo_panic_map().
v7:
* Return
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++
.../drm/i915/display/intel_display_types.h| 2 ++
2 files ch
The vaddr of the fbdev framebuffer is private to the struct
intel_fbdev, so this function is needed to access it for drm_panic.
Also the struct i915_vma is different between i915 and xe, so it
requires a few functions to access fbdev->vma->iomap.
Signed-off-by: Jocelyn Falempe
---
v2:
c_pages in i915_gem_object_panic_finish()
Also change i915_panic_pages allocation to kmalloc, as kvmalloc is not
safe to call from the panic handler.
* Fix dim checkpatch warnings.
Jocelyn Falempe (9):
drm/i915/fbdev: Add intel_fbdev_get_map()
drm/i915/display/i9xx: Add a disable_tiling(
On 06/06/2025 15:24, Jani Nikula wrote:
On Fri, 06 Jun 2025, Jocelyn Falempe wrote:
Implement both functions for i915 and xe, they prepare the work for
drm_panic support.
They both use kmap_try_from_panic(), and map one page at a time, to
write the panic screen on the framebuffer.
Signed-off
On 06/06/2025 14:28, Christian König wrote:
On 6/6/25 13:48, Jocelyn Falempe wrote:
If the ttm bo is backed by pages, then it's possible to safely kmap
one page at a time, using kmap_try_from_panic().
I strongly assume that we don't care about locking anything in this case, don&#x
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++
.../drm/i915/display/intel_display_types.h| 2 ++
2 files ch
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
.../drm/i915/display/skl_universal_plane.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
v8:
* Pass the tiling function to intel_bo_panic_setup()
.../gpu/drm/i915/di
When the panic handler is called, configure the psr to send the full
framebuffer to the monitor, otherwise the panic screen is only
partially visible.
Signed-off-by: Jocelyn Falempe
---
v8:
* Added in v8
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +++
drivers/gpu/drm/i915/display
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 20 +++
1 file change
Implement both functions for i915 and xe, they prepare the work for
drm_panic support.
They both use kmap_try_from_panic(), and map one page at a time, to
write the panic screen on the framebuffer.
Signed-off-by: Jocelyn Falempe
---
v5:
* Use iosys_map for intel_bo_panic_map().
v7:
* Return
essing the
framebuffer, so this will be handled by the following patches.
Signed-off-by: Jocelyn Falempe
---
v4:
* Add support for Xe driver.
v6:
* Use struct intel_display instead of drm_i915_private for intel_atomic_plane.c
v7:
* Fix mismatch {} in intel_panic_flush() (Jani Nikula)
If the ttm bo is backed by pages, then it's possible to safely kmap
one page at a time, using kmap_try_from_panic().
Unfortunately there is no way to do the same with ioremap, so it
only supports the kmap case.
This is needed for proper drm_panic support with xe driver.
Signed-off-by: Jo
The vaddr of the fbdev framebuffer is private to the struct
intel_fbdev, so this function is needed to access it for drm_panic.
Also the struct i915_vma is different between i915 and xe, so it
requires a few functions to access fbdev->vma->iomap.
Signed-off-by: Jocelyn Falempe
---
v2:
time.
* Configure psr to send the full framebuffer update.
Jocelyn Falempe (9):
drm/i915/fbdev: Add intel_fbdev_get_map()
drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes
drm/i915/display: Add a disable_tiling() for skl planes
drm/ttm: Add ttm_bo_kmap_try_from_panic()
drm/i915
On 26/05/2025 11:01, Ryosuke Yasuoka wrote:
Add drm_panic module for hyperv drm so that panic screen can be
displayed on panic.
I've just pushed it to drm-misc-next.
Thanks for your contribution.
--
Jocelyn
Signed-off-by: Ryosuke Yasuoka
---
drivers/gpu/drm/hyperv/hyperv_drm_modeset.c
On 26/05/2025 11:01, Ryosuke Yasuoka wrote:
Add drm_panic module for hyperv drm so that panic screen can be
displayed on panic.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Ryosuke Yasuoka
---
drivers/gpu/drm/hyperv/hyperv_drm_modeset.c | 36
On 22/05/2025 23:05, Lucas De Marchi wrote:
On Fri, May 23, 2025 at 06:32:43AM +1000, Dave Airlie wrote:
On Fri, 23 May 2025 at 01:10, Lucas De Marchi
wrote:
On Thu, May 22, 2025 at 04:52:18PM +1000, Dave Airlie wrote:
>From: Dave Airlie
>
>This reduces this struct from 16 to 8 bytes, and it
On 27/04/2025 12:18, Ryosuke Yasuoka wrote:
Drop simple-KMS in favor of regular atomic helpers to make the code more
modular. The simple-KMS helper mix up plane and CRTC state, so it is
obsolete and should go away [1]. Since it just split the simple-pipe
functions into per-plane and per-CRTC, no
r red, green and blue. The driver reduces them to 8 bit to make
them fit into hardware registers.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_mode.c | 69 +-
1 file changed, 42 inser
r red,
green and blue. The driver reduces them to 8 bit to make them fit
into hardware registers.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/mgag200/mgag200_drv.h| 4 +-
drivers/gpu/drm/mgag200/mgag200_g200er.c | 4 +-
dr
with increasing luminance, but
later patches can change this. For PCs, a VGA default palette could
be used.
If we plan to use it for driver with 10bits gamma LUT, then it's fine
for me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_color_mg
On 09/05/2025 10:23, Thomas Zimmermann wrote:
Provide helpers that program hardware gamma LUTs. Tha gamma ramp is
either provided by the driver or generated by the helper.
The DRM driver exports the GAMMA_LUT property with a fixed number of
entries per color component, such as 256 on 8-bit-wide
Add myself and Javier as maintainer for drm_panic, drm_panic_qr_code
and drm_log.
Signed-off-by: Jocelyn Falempe
Acked-by: Thomas Zimmermann
---
v2:
* move DRM LOG to keep the entries sorted (Jani Nikula)
MAINTAINERS | 28
1 file changed, 28 insertions(+)
diff
On 06/05/2025 15:52, Jani Nikula wrote:
On Tue, 06 May 2025, Jocelyn Falempe wrote:
Add myself and Javier as maintainer for drm_panic, drm_panic_qr_code
and drm_log.
Signed-off-by: Jocelyn Falempe
---
MAINTAINERS | 28
1 file changed, 28 insertions(+)
diff
Add myself and Javier as maintainer for drm_panic, drm_panic_qr_code
and drm_log.
Signed-off-by: Jocelyn Falempe
---
MAINTAINERS | 28
1 file changed, 28 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 38df6b159a3b..df3abdcf1767 100644
--- a/MAINTAINERS
On 18/04/2025 18:48, Jocelyn Falempe wrote:
On 32bits ARM, u64/u64 is not supported [1], so change the algorithm
to use a simple fifo with decimal digits as u8 instead.
This is slower but should compile on all architecture.
I applied it to drm-misc/drm-misc-next.
Thanks for the reviews
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 69 ++-
.../drm
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 23 ++-
1 file change
On Lunar Lake, if the panic occurs when fbcon is active, the panic
screen is only partially visible on the screen. Adding this
intel_frontbuffer_flush() call solves the issue.
It's probably not safe to do that in the panic handler, but that's
still better than nothing.
Signed-off-b
essing the
framebuffer, so this will be handled by the following patches.
Signed-off-by: Jocelyn Falempe
---
v4:
* Add support for Xe driver.
v6:
* Use struct intel_display instead of drm_i915_private for intel_atomic_plane.c
v7:
* Fix mismatch {} in intel_panic_flush() (Jani Nikula)
.../gp
Prepare the work for drm_panic support. This is used to map the
current framebuffer, so the CPU can overwrite it with the panic
message.
Signed-off-by: Jocelyn Falempe
---
v5:
* Use iosys_map for intel_bo_panic_map().
v7:
* Return int for i915_gem_object_panic_map() (Ville Syrjälä
The vaddr of the fbdev framebuffer is private to the struct
intel_fbdev, so this function is needed to access it for drm_panic.
Also the struct i915_vma is different between i915 and xe, so it
requires a few functions to access fbdev->vma->iomap.
Signed-off-by: Jocelyn Falempe
---
v2:
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
.../drm/i915/display/skl_universal_plane.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm
ze is always smaller
than the tiled.
Signed-off-by: Jocelyn Falempe
---
v7:
* Reword commit message about alignment/size when disabling tiling (Ville
Syrjälä)
drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++
.../drm/i915/display/intel_display_types.h| 2 ++
2 files ch
iling (Ville
Syrjälä)
Jocelyn Falempe (8):
drm/i915/fbdev: Add intel_fbdev_get_map()
drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes
drm/i915/display: Add a disable_tiling() for skl planes
drm/i915/gem: Add i915_gem_object_panic_map()
drm/i915/display: Add drm_panic support
On 18/04/2025 20:18, Miguel Ojeda wrote:
On Fri, Apr 18, 2025 at 6:51 PM Jocelyn Falempe wrote:
Link:
https://lore.kernel.org/dri-devel/caniq72ke45eowckmhwhvmwxc03dxr4rnxxkvx+hvwdblopz...@mail.gmail.com/
[1]
Thanks for fixing that -- some tags for your consideration:
Reported-by: Miguel
]
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/drm_panic_qr.rs | 71 ++---
1 file changed, 48 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/drm_panic_qr.rs b/drivers/gpu/drm/drm_panic_qr.rs
index 6025a705530e..dd55b1cb764d 100644
--- a/drivers/gpu/drm
On 16/04/2025 14:24, Miguel Ojeda wrote:
On Wed, Apr 16, 2025 at 2:21 PM Miguel Ojeda wrote:
`///` should still be used for private items [1]. Some of the items in
this file do so already, so do it for a few other clear candidates in
the file.
I just pushed it to drm-misc-next
Thanks,
--
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