On 9/28/23 13:16, Dmitry Baryshkov wrote:
Port Qualcomm QMP HDMI PHY to the generic PHY framework. Split the
generic part and the msm8996 part. When adding support for msm8992/4 and
msm8998 (which also employ QMP for HDMI PHY), one will have to provide
the PLL programming part only.
Signed-of
On 9/28/23 13:16, Dmitry Baryshkov wrote:
Drop source files used by old HDMI PHY and HDMI PLL drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 216 ---
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 51 --
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c |
: Konrad Dybcio
Konrad
On 9/28/23 13:16, Dmitry Baryshkov wrote:
In preparation to converting MSM HDMI driver to use PHY framework, which
requires phy_power_on() calls to be paired with phy_power_off(), add a
conditional call to msm_hdmi_phy_powerdown() before the call to
msm_hdmi_phy_powerup().
Signed-off-by: Dmit
On 9/28/23 13:16, Dmitry Baryshkov wrote:
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
This looks good, but I'm far from knowledgeable in terms of drm, so:
Acked-by: K
On 9/28/23 13:16, Dmitry Baryshkov wrote:
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Konrad Dybcio
Konrad
On 9/28/23 13:16, Dmitry Baryshkov wrote:
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---Reviewed-by: Konrad Dybcio
Konrad
On 10/23/23 22:20, Rob Clark wrote:
On Mon, Oct 23, 2023 at 12:56 PM Konrad Dybcio wrote:
On 10/23/23 21:42, Rob Clark wrote:
On Mon, Oct 23, 2023 at 7:29 AM Konrad Dybcio wrote:
New GPUs still use the lower 2 bytes of the chip id (in whatever form
it comes) to signify silicon
On 10/23/23 21:42, Rob Clark wrote:
On Mon, Oct 23, 2023 at 7:29 AM Konrad Dybcio wrote:
New GPUs still use the lower 2 bytes of the chip id (in whatever form
it comes) to signify silicon revision. Drop the warning that makes it
sound as if that was unintended.
Fixes: 90b593ce1c9e (&quo
New GPUs still use the lower 2 bytes of the chip id (in whatever form
it comes) to signify silicon revision. Drop the warning that makes it
sound as if that was unintended.
Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU")
Signed-off-by: Konrad Dybcio
---
d
On 23.10.2023 15:25, Neil Armstrong wrote:
> Hi,
>
> On 23/10/2023 13:55, Arnd Bergmann wrote:
>> From: Arnd Bergmann
>>
>> As with several other panel drivers, this fails to link without the DP
>> helper library:
>>
>> ld: drivers/gpu/drm/panel/panel-raydium-rm692e5.o: in function
>> `rm692e5_p
On 10/16/23 22:22, Akhil P Oommen wrote:
On Tue, Sep 26, 2023 at 08:24:40PM +0200, Konrad Dybcio wrote:
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
On platforms that support it (in firmware), it is necessary to
describe that link, or Adreno register access will
On 10/17/23 09:33, Rob Clark wrote:
On Mon, Oct 16, 2023 at 1:12 PM Akhil P Oommen wrote:
On Tue, Sep 26, 2023 at 08:24:37PM +0200, Konrad Dybcio wrote:
Some (many?) devices with A635 expect a ZAP shader to be loaded.
Set the file name to allow for that.
Signed-off-by: Konrad Dybcio
_send'
Add the usual dependency that still allows compiling without QMP but
otherwise avoids the broken combination of options.
Fixes: 88a0997f2f949 ("drm/msm/a6xx: Send ACD state to QMP at GMU resume")
Signed-off-by: Arnd Bergmann
---
Right, thanks!
Reviewed-by: Konrad Dybcio
Konrad
these issues.
Reported-by: Dan Carpenter
Fixes: 88a0997f2f94 ("drm/msm/a6xx: Send ACD state to QMP at GMU resume")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/g
On 10/10/23 01:33, Richard Acayan wrote:
The Snapdragon 670 has a display subsystem for controlling and
outputting to the display. Add support for it in the device tree.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Richard Acayan
---
[...]
+ interconnects = <&mmss_n
Add support for the 2700x1224 AMOLED BOE panel bundled with a RM692E5
driver IC, as found on the Fairphone 5 smartphone.
Co-developed-by: Luca Weiss
Signed-off-by: Luca Weiss
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile
Raydium RM692E5 is a display driver IC used to drive AMOLED DSI panels.
Describe it.
Reviewed-by: Conor Dooley
Signed-off-by: Konrad Dybcio
---
.../bindings/display/panel/raydium,rm692e5.yaml| 73 ++
1 file changed, 73 insertions(+)
diff --git
a/Documentation
The Fairphone 5 smartphone ships with a BOE AMOLED panel in conjunction
with a Raydium RM692E5 driver IC. This series adds the bindings and driver
for that.
Signed-off-by: Konrad Dybcio
---
Changes in v2:
DRIVER:
- Remove 1ms sleeps after each DCS command submission
- Remove WARN_ON from probe
On 29.09.2023 00:00, Jessica Zhang wrote:
> Hi Konrad,
>
> On 9/27/2023 6:19 AM, Konrad Dybcio wrote:
>> Add support for the 2700x1224 AMOLED BOE panel bundled with a RM692E5
>> driver IC, as found on the Fairphone 5 smartphone.
>>
>> Co-developed-by: Luca We
On 28.09.2023 19:09, Conor Dooley wrote:
> On Wed, Sep 27, 2023 at 03:19:01PM +0200, Konrad Dybcio wrote:
>> Raydium RM692E5 is a display driver IC used to drive AMOLED DSI panels.
>> Describe it.
>>
>> Signed-off-by: Konrad Dybcio
>> ---
>> .../bind
On 28.09.2023 13:16, Dmitry Baryshkov wrote:
> From: Sandor Yu
>
> Allow HDMI PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
>
> The parameters added here are based on HDMI PHY
> implementation practices. The current set of parameter
Add support for the 2700x1224 AMOLED BOE panel bundled with a RM692E5
driver IC, as found on the Fairphone 5 smartphone.
Co-developed-by: Luca Weiss
Signed-off-by: Luca Weiss
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile
Raydium RM692E5 is a display driver IC used to drive AMOLED DSI panels.
Describe it.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/panel/raydium,rm692e5.yaml| 73 ++
1 file changed, 73 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/panel
The Fairphone 5 smartphone ships with a BOE AMOLED panel in conjunction
with a Raydium RM692E5 driver IC. This series adds the bindings and driver
for that.
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (2):
dt-bindings: display: panel: Add Raydium RM692E5
drm/panel: Add driver for
On 26.09.2023 01:26, Richard Acayan wrote:
> The Snapdragon 670 uses similar clocks (with one frequency added) to the
> Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU
> with configuration from the Pixel 3a downstream kernel.
>
> Since revision 4.0 is SDM845, reuse some confi
On 26.09.2023 21:10, Danila Tikhonov wrote:
>
> I think you mean by name downstream dt - sdmmagpie-gpu.dtsi
>
> You can see the forked version of the mainline here:
> https://github.com/sm7150-mainline/linux/blob/next/arch/arm64/boot/dts/qcom/sm7150.dtsi
>
> All fdt that we got here, if it is us
On 26.09.2023 19:42, Danila Tikhonov wrote:
> SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
> 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
> to zero decimal places.
>
> Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn).
>
> Add t
On 26.09.2023 20:24, Konrad Dybcio wrote:
> Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU.
> Describe that and make sure it doesn't interfere with Chrome devices.
>
> Signed-off-by: Konrad Dybcio
> ---
> arch/arm64/boot/dts/qcom/sc7280-
On 26.09.2023 20:24, Konrad Dybcio wrote:
> The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
> mark the GPU one as well.
>
> Signed-off-by: Konrad Dybcio
> ---
Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support")
Sorry.
Konrad
The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
mark the GPU one as well.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
A643 (A635 speedbin 0xac) tops out at 812 MHz. Fill in the
opp-supported-hw appropriately.
Note that fuseval 0xac is referred to as speedbin 1 downstream, but
that was already in use upstream, so 2 was chosen instead.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 12
.
Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support")
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.
Downstream calls this the "speedbin 1", but that number is already
occupied. Use index two.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/
Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU.
Describe that and make sure it doesn't interfere with Chrome devices.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 2 ++
arch/arm64/boot/dts/qcom/sc7280.dtsi
eniently always bound to fuseval == 0).
Fixes: c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx
Some (many?) devices with A635 expect a ZAP shader to be loaded.
Set the file name to allow for that.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm
as it says on the can
drm/msm patches for Rob
arm64 patches for linux-arm-msm
for use with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408
tested on QCM6490 (SC7280-IOT) Fairphone FP5
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (7):
drm/msm/a6xx: Fix unknown speedbin
d GPU that can't receive data on its end of the bus.
Failing to do this will result in inexplicable GMU timeouts or worse.
This is a rather ugly hack which introduces a whole lot of latency.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Kon
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu
# on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 88 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 27
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno
8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 96 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 451
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
They use GMU for all things DVFS, just like most A6xx GPUs.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
Documentation
U.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/gmu.yaml | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documenta
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm
: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 428eb138881a
olrz,flushall,noubwc MESA_LOADER_DRIVER_OVERRIDE=zink kmscube
[1]
https://lore.kernel.org/linux-arm-msm/20230517-topic-a7xx_prep-v4-0-b16f273a9...@linaro.org/
[2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt
[3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217
Signed-o
On 9/21/23 02:01, Abhinav Kumar wrote:
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.
sc7280 and all other chipsets using DSC 1.2 use dpu_hw_dsc_init_1_2 and
not dpu_hw_dsc_init
On 9/21/23 01:41, Abhinav Kumar wrote:
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.
No, its correct from what i can tell.
Before inlining it was using PP_BLK_DI
DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2
Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
the block length from a wrong value to another wrong value.
Use the correct one this time.
Fixes: e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths")
Signed-off-by: Konrad Dybcio
---
drivers/g
Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.
Fixes: 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc72
Found a couple mistakes, this series attempts to fix it.
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (3):
drm/msm/dpu: Fix SC7280 PP length
drm/msm/dpu: Add missing DPU_DSC_OUTPUT_CTRL to SC7280
drm/msm/dpu: Fix SC7280 DSC block length
drivers/gpu/drm/msm/disp/dpu1/catalog
On 15.09.2023 14:59, Dan Carpenter wrote:
> The irq_of_parse_and_map() function returns zero on error. It
> never returns negative error codes. Fix the check.
>
> Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
> Signed-off-by: Dan Carpenter
> --
On 13.09.2023 21:19, Danila Tikhonov wrote:
> SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
> 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
> to zero decimal places.
>
> The vendor's FW GMU is called a618_gmu.bin. And also a618 on SM7150 uses
> a61
On 23.08.2023 14:56, Konrad Dybcio wrote:
> A740 builds upon the A730 IP, shuffling some values and registers
> around. More differences will appear when things like BCL are
> implemented.
>
> adreno_is_a740_family is added in preparation for more A7xx GPUs,
> the logic ch
d GPU that can't receive data on its end of the bus.
Failing to do this will result in inexplicable GMU timeouts or worse.
This is a rather ugly hack which introduces a whole lot of latency.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Kon
U.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/gmu.yaml | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documenta
# on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 88 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 27
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu
8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 96 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 451
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
They use GMU for all things DVFS, just like most A6xx GPUs.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
Documentation
: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 20ddb89a4500
olrz,flushall,noubwc MESA_LOADER_DRIVER_OVERRIDE=zink kmscube
[1]
https://lore.kernel.org/linux-arm-msm/20230517-topic-a7xx_prep-v4-0-b16f273a9...@linaro.org/
[2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt
[3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217
Signed-o
On 8.09.2023 17:22, Vignesh Raman wrote:
> Due to the presence of the fastboot micro cable in the CI farm,
> it causes the hardware to remain in gadget mode instead of host mode.
> So it doesn't find the network, which results in failure to mount root
> fs via NFS.
>
> Add an overlay dtso file tha
On 17.08.2023 16:59, Dmitry Baryshkov wrote:
> Enable the onboard displayport controller, connect it to QMP PHY.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 26.08.2023 03:29, Rob Clark wrote:
> On Fri, Aug 25, 2023 at 2:11 PM Konrad Dybcio
> wrote:
>>
>> SM6375 comes with a patchlevel=1. Fix the chipid up to reflect that.
>>
>> Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GP
SM6375 comes with a patchlevel=1. Fix the chipid up to reflect that.
Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
# on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 88 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 27
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm
U.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/gmu.yaml | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documenta
d GPU that can't receive data on its end of the bus.
Failing to do this will result in inexplicable GMU timeouts or worse.
This is a rather ugly hack which introduces a whole lot of latency.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Kon
8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 95 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 451
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno
: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 20ddb89a4500
olrz,flushall,noubwc MESA_LOADER_DRIVER_OVERRIDE=zink kmscube
[1]
https://lore.kernel.org/linux-arm-msm/20230517-topic-a7xx_prep-v4-0-b16f273a9...@linaro.org/
[2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt
[3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217
Signed-o
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
They use GMU for all things DVFS, just like most A6xx GPUs.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
Documentation
On 11.08.2023 18:21, Rob Clark wrote:
> On Fri, Aug 11, 2023 at 9:11 AM Konrad Dybcio
> wrote:
>>
>> On 11.08.2023 18:09, Rob Clark wrote:
>>> On Fri, Aug 11, 2023 at 9:05 AM Rob Clark wrote:
>>>>
>>>> From: Rob Clark
>>>>
>
t;> generation (or "family") will use the same fw, and a690 is in the a660
>> family.
>>
>
> possibly this could be considered as:
>
> Fixes: 5e7665b5e484 ("drm/msm/adreno: Add Adreno A690 support")
For a lack of a better response, "meh"
d GPU that can't receive data on its end of the bus.
Failing to do this will result in inexplicable GMU timeouts or worse.
This is a rather ugly hack which introduces a whole lot of latency.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Kon
A7xx GMUs can be slow as molasses at times.
Increase the timeout to 1 second to match the vendor driver.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 2 +-
1 file changed, 1 insertion
# on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 88 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 27
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu
8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 95 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 451
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
If the GMU can't guarantee the required resources are up, trying to
bring up the GPU is a lost cause. Return early if setting GPU OOB
fails.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_
Add a helper that does exactly what it says on the can, it'll be
required for A7xx.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +
1 file changed, 5 insertions(+)
diff --
Move these wrappers in preparation for use in a6xx_gmu.c
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 +++
2
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm
: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 20ddb89a4500..e132dbff3c4a 100644
--- a
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
They use GMU for all things DVFS, just like most A6xx GPUs.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
Documentation
U.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/gmu.yaml | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documenta
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