The ddc-i2c-bus property should be placed in connector node,
mark the HDMI TX side property as deprecated.
Acked-by: Rob Herring (Arm)
Reviewed-by: Laurent Pinchart
Reviewed-by: Neil Armstrong
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David
The ddc-i2c-bus property should be placed in connector node,
mark the HDMI TX side property as deprecated.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Fabio Estevam
Cc: Jernej Skrabec
Cc: Jonas Karlman
Cc: Krzysztof Kozlowski
On 5/15/24 8:27 AM, Marek Vasut wrote:
The DW HDMI driver core is responsible for parsing the 'ddc-i2c-bus' property,
move the property description into the DW HDMI common DT schema too, so this
property can be used on all devices integrating the DW HDMI core.
Signed-off-by: Marek Vasut
On 5/15/24 5:12 AM, Liu Ying wrote:
On 5/15/24 06:04, Marek Vasut wrote:
The DW HDMI driver core is responsible for parsing the 'ddc-i2c-bus' property,
move the property description into the DW HDMI common DT schema too, so this
property can be used on all devices integrating the DW HDMI core
The DW HDMI driver core is responsible for parsing the 'ddc-i2c-bus' property,
move the property description into the DW HDMI common DT schema too, so this
property can be used on all devices integrating the DW HDMI core.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Conor Dooley
Cc
The DW HDMI driver core is responsible for parsing the 'ddc-i2c-bus' property,
move the property description into the DW HDMI common DT schema too, so this
property can be used on all devices integrating the DW HDMI core.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Conor Dooley
Cc
which make the output video look striped horizontally.
Reviewed-by: Robert Foss
Signed-off-by: Marek Vasut
---
Cc: Adam Ford
Cc: Alexander Stein
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
Cc: Frieder Schrempf
Cc: Jernej Skrabec
Cc: Jonas Karlman
Cc: Laurent Pinchart
Cc: Lucas
On 5/13/24 9:57 AM, Marek Szyprowski wrote:
On 13.05.2024 04:16, Marek Vasut wrote:
Initialize the bridge on attach already, to force lanes into LP11
state, since attach does trigger attach of downstream bridges which
may trigger (e)DP AUX channel mode read.
This fixes a corner case where
at that point the DSI lane mode is undefined.
When the .attach callback is called, the DSI link is surely in LP11 mode.
Toggle the RESX signal here and reconfigure the AUX channel. That way,
the AUX channel communication from this point on does surely run at
10 MHz as it should.
Signed-off-by: Marek Vasut
channel access later in its attach callback.
Signed-off-by: Marek Vasut
---
Cc: Adam Ford
Cc: Alexander Stein
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
Cc: Frieder Schrempf
Cc: Inki Dae
Cc: Jagan Teki
Cc: Jernej Skrabec
Cc: Jonas Karlman
Cc: Laurent Pinchart
Cc: Lucas Stach
Cc
which make the output video look striped horizontally.
Signed-off-by: Marek Vasut
---
Cc: Adam Ford
Cc: Alexander Stein
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
Cc: Frieder Schrempf
Cc: Jernej Skrabec
Cc: Jonas Karlman
Cc: Laurent Pinchart
Cc: Lucas Stach
Cc: Maarten Lankhorst
On 4/22/24 3:04 PM, Adam Ford wrote:
On Mon, Apr 22, 2024 at 8:01 AM Marek Vasut wrote:
On 4/22/24 2:09 PM, Adam Ford wrote:
On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut wrote:
On 2/12/24 12:09 AM, Adam Ford wrote:
When using video sync pulses, the HFP, HBP, and HSA are divided between
On 4/22/24 2:09 PM, Adam Ford wrote:
On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut wrote:
On 2/12/24 12:09 AM, Adam Ford wrote:
When using video sync pulses, the HFP, HBP, and HSA are divided between
the available lanes if there is more than one lane. For certain
timings and lane
struct
samsung_dsim *dsi,
u16 _m, best_m;
u8 _s, best_s;
- p_min = DIV_ROUND_UP(fin, (12 * MHZ));
- p_max = fin / (6 * MHZ);
+ p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * MHZ));
The parenthesis around driver_data... are not needed.
With that fixed:
Reviewed-by: Marek Vasut
On 2/12/24 12:09 AM, Adam Ford wrote:
When using video sync pulses, the HFP, HBP, and HSA are divided between
the available lanes if there is more than one lane. For certain
timings and lane configurations, the HFP may not be evenly divisible.
If the HFP is rounded down, it ends up being too
On 4/21/24 1:09 PM, Ondřej Jirman wrote:
Hi,
Hi,
On Sun, Apr 21, 2024 at 02:22:35AM GMT, Marek Vasut wrote:
Doing modeset in .atomic_pre_enable callback instead of dedicated .mode_set
callback does not seem right. Undo this change, which was added as part of
Actually no. If anything
;TC358762 DSI-to-DPI
bridge->PT800480 DPI panel pipeline. The original fix for HX8394 panel likely
requires HX8394 panel side fix instead.
Fixes: 05aa61334592 ("drm: bridge: dw-mipi-dsi: Fix enable/disable of DSI
controller")
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Biju
/G121X1-L03_Datasheet.pdf
[2]
https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121XCE-L01_Datasheet.pdf
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc
riant.
[1]
https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf
[2]
https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121XCE-L01_Datasheet.pdf
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jessica
TIMING SPECIFICATIONS.
[1]
https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G121X1-L03_Datasheet.pdf
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Neil
/Innolux/G121X1-L03_Datasheet.pdf
Fixes: f8fa17ba812b ("drm/panel: simple: Add support for Innolux G121X1-L03")
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Neil
On 3/7/24 9:09 AM, Sean Nyekjaer wrote:
Hi,
Hi,
We are using the stm32mp1 together with the sn65dsi83 bridge.
The ti,sn65dsi83 driver is (hard) enabling MIPI_DSI_MODE_VIDEO_BURST, then the
st,stm32-dsi driver is adding +20% to the clock speed.
That means our LVDS is +20% higher than
LCDIF variant")
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David Airlie
Cc: Fabio Estevam
Cc: Liu Ying
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: NXP Linux Team
Cc: Pengutronix Kernel Team
Cc: Sascha Hauer
Cc: Shawn Guo
Cc: Stefan Agner
Cc: Thomas Zimmermann
Cc:
LCDIF variant")
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David Airlie
Cc: Fabio Estevam
Cc: Liu Ying
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: NXP Linux Team
Cc: Pengutronix Kernel Team
Cc: Sascha Hauer
Cc: Shawn Guo
Cc: Stefan Agner
Cc: Thomas Zimmermann
Cc:
On 1/18/24 19:39, Marek Vasut wrote:
In case the LCDIF is enabled in DT but unused, the clock used by the
LCDIF are not enabled. Those clock may even have a use count of 0 in
case there are no other users of those clock. This can happen e.g. in
case the LCDIF drives HDMI bridge which has
On 2/16/24 10:10, Tomi Valkeinen wrote:
On 15/02/2024 11:03, Alexander Stein wrote:
Hi everyone,
Am Donnerstag, 15. Februar 2024, 09:53:54 CET schrieb Jan Kiszka:
On 11.12.23 09:07, Aradhya Bhatia wrote:
On 06/12/23 17:41, Tomi Valkeinen wrote:
Hi,
On 08/11/2023 14:45, Alexander Stein
On 1/18/24 19:39, Marek Vasut wrote:
In case the LCDIF is enabled in DT but unused, the clock used by the
LCDIF are not enabled. Those clock may even have a use count of 0 in
case there are no other users of those clock. This can happen e.g. in
case the LCDIF drives HDMI bridge which has
According to new configuration spreadsheet from Toshiba for TC9595,
the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
calculates those PLL input clock as reference clock divided by both
pre-dividers. Add the extra limit.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc
a warning from clock core about this condition.
Note that the lcdif_rpm_suspend() and lcdif_rpm_resume() functions
internally perform the clock disable and enable operations and act
as runtime PM hooks too.
Fixes: 9db35bb349a0 ("drm: lcdif: Add support for i.MX8MP LCDIF variant")
Signed-off
and 16.7M colors (RGB 8-bits) with LED backlight driving circuit.
All input signals are LVDS interface compatible.
G156HAN04.0 is designed for a display unit of notebook style
personal computer and industrial machine.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Elmar Albert
Signed-off-by: Marek Vasut
.
All input signals are LVDS interface compatible.
G156HAN04.0 is designed for a display unit of notebook style
personal computer and industrial machine.
Signed-off-by: Elmar Albert
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jessica Zhang
Cc
@8003: interrupts: [[46], [45]] is too long
from schema $id: http://devicetree.org/schemas/display/fsl,lcdif.yaml#
Signed-off-by: Fabio Estevam
Indeed
Reviewed-by: Marek Vasut
Switch from deprecated unmanaged drm_mode_config_init() to
managed drmm_mode_config_init(). No functional change.
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David Airlie
Cc: Fabio Estevam
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: NXP Linux Team
Cc: Pengutronix Kernel Team
Cc
Switch from deprecated unmanaged drm_mode_config_init() to
managed drmm_mode_config_init(). No functional change.
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David Airlie
Cc: Fabio Estevam
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: NXP Linux Team
Cc: Pengutronix Kernel Team
Cc
Switch from deprecated unmanaged drm_mode_config_init() to
managed drmm_mode_config_init(). No functional change.
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David Airlie
Cc: Fabio Estevam
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: NXP Linux Team
Cc: Pengutronix Kernel Team
Cc
Drop extra space, no functional change.
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David Airlie
Cc: Fabio Estevam
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: NXP Linux Team
Cc: Pengutronix Kernel Team
Cc: Sascha Hauer
Cc: Shawn Guo
Cc: Stefan Agner
Cc: Thomas Zimmermann
Cc
On 11/17/23 09:40, Maxime Ripard wrote:
On Thu, Nov 16, 2023 at 10:15:31PM +0100, Marek Vasut wrote:
On 10/9/23 10:58, Neil Armstrong wrote:
On 09/10/2023 00:33, Marek Vasut wrote:
Add missing .bus_flags = DRM_BUS_FLAG_DE_HIGH to this panel description,
ones which match both the datasheet
On 11/17/23 09:40, Maxime Ripard wrote:
On Thu, Nov 16, 2023 at 10:15:31PM +0100, Marek Vasut wrote:
On 10/9/23 10:58, Neil Armstrong wrote:
On 09/10/2023 00:33, Marek Vasut wrote:
Add missing .bus_flags = DRM_BUS_FLAG_DE_HIGH to this panel description,
ones which match both the datasheet
On 10/9/23 10:58, Neil Armstrong wrote:
On 09/10/2023 00:33, Marek Vasut wrote:
Add missing .bus_flags = DRM_BUS_FLAG_DE_HIGH to this panel description,
ones which match both the datasheet and the panel display_timing flags .
Fixes: 1e29b840af9f ("drm/panel: simple: Add Innolux G101IC
On 10/9/23 11:01, Neil Armstrong wrote:
Hi,
On 09/10/2023 00:32, Marek Vasut wrote:
The Innolux G101ICE-L01 datasheet [1] page 17 table
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
indicates that maximum vertical blanking time is 40 lines.
Currently the driver uses 29 lines.
Fix it, and since
On 11/16/23 17:06, Marc Kleine-Budde wrote:
Hey Marek,
On 15.06.2023 22:19:00, Marek Vasut wrote:
This bridge seems to need the HSE packet, otherwise the image is
shifted up and corrupted at the bottom. This makes the bridge
work with Samsung DSIM on i.MX8MM and i.MX8MP.
I'm using v6.6
Add missing .bus_flags = DRM_BUS_FLAG_DE_HIGH to this panel description,
ones which match both the datasheet and the panel display_timing flags .
Fixes: 1e29b840af9f ("drm/panel: simple: Add Innolux G101ICE-L01 panel")
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David
cannot do 1 px
HSA/VSA, distribute the delays evenly between all three parts.
[1]
https://www.data-modul.com/sites/default/files/products/G101ICE-L01-C2-specification-12042389.pdf
Fixes: 1e29b840af9f ("drm/panel: simple: Add Innolux G101ICE-L01 panel")
Signed-off-by: Marek Vasut
---
false, true);
+ if (ret)
+ return ret;
+
+ if (old_state->fb && new_state->fb->format != old_state->fb->format)
+ crtc_state->mode_changed = true;
+
+ return 0;
}
static void lcdif_plane_primary_atomic_update(struct drm_plane *plane,
Reviewed-by: Marek Vasut
+ LCDC_V8_CTRLDESCL_HIGH0_4);
- }
-
drm_crtc_vblank_on(crtc);
}
Reviewed-by: Marek Vasut
ficiency so set it here too.
+*/
+ writel(CTRLDESCL0_3_P_SIZE(2) | CTRLDESCL0_3_T_SIZE(2) |
+ CTRLDESCL0_3_PITCH(new_pstate->fb->pitches[0]),
+ lcdif->base + LCDC_V8_CTRLDESCL0_3);
}
static bool lcdif_format_mod_supported(struct drm_plane *plane,
Reviewed-by: Marek Vasut
pper_32_bits(paddr)),
lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
}
- lcdif_enable_controller(lcdif);
drm_crtc_vblank_on(crtc);
}
Reviewed-by: Marek Vasut
2 - 256Byte
-* Downstream set it to 256B burst size to improve the memory
+* Downstream sets this to 256B burst size to improve the memory access
* efficiency so set it here too.
With that fixed:
Reviewed-by: Marek Vasut
On 8/26/23 20:33, Mimoja wrote:
Hi,
+CC Dave , he might be able to help with the last part.
I appreciate you taking the time to respond!
On 26.08.23 17:18, Marek Vasut wrote:
On 8/26/23 11:55, Mimoja wrote:
"The .prepare() function is typically called before the display
controller
s
On 8/26/23 11:55, Mimoja wrote:
The struct drm_panel_funcs are offering a prepare() and an enable()
entrypoint for panels. According to drm/panel.h:
"The .prepare() function is typically called before the display controller
starts to transmit video data."
and
"After the display controller has
en sitting on it waiting to see if
Marek or Liu popped up..
I don't see anything which would resemble power domains like on
MX8MM/N/P on the MQ MXSFB, there are such domains for the VPU and DCSS,
but not MXSFB. So
Reviewed-by: Marek Vasut
Drain command transfer FIFO before
transfer").
Fixes: 14806c641582 ("drm: bridge: samsung-dsim: Drain command transfer FIFO before
transfer")
Signed-off-by: Marek Szyprowski
Oh, nice, there is already a bitfield piece in place.
Thanks !
Reviewed-by: Marek Vasut
On 8/7/23 15:00, Marek Szyprowski wrote:
Hi,
diff --git a/include/drm/bridge/samsung-dsim.h
b/include/drm/bridge/samsung-dsim.h
index 05100e91ecb9..18017b3e5d9e 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -62,6 +62,7 @@ struct
14186, 15000 },
.hactive = { 1920, 1920, 1920 },
.hfront_porch = { 80, 90, 100 },
.hback_porch = { 80, 90, 100 },
Odd, now I don't see the flicker anymore.
Tested-by: Marek Vasut # MX8MM with LT9211
Reviewed-by: Marek Vasut
Thanks !
On 8/2/23 20:49, Rob Clark wrote:
On Wed, Aug 2, 2023 at 11:16 AM Dmitry Baryshkov
wrote:
On Wed, 2 Aug 2023 at 20:34, Marek Vasut wrote:
On 8/2/23 15:38, Dmitry Baryshkov wrote:
On 02/08/2023 11:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression
On 8/3/23 17:06, Luca Ceresoli wrote:
Hi Marek,
On Thu, 3 Aug 2023 16:25:37 +0200
Marek Vasut wrote:
On 8/3/23 16:23, Luca Ceresoli wrote:
Hi Marek,
Hi,
On Mon, 31 Jul 2023 23:02:58 +0200
Marek Vasut wrote:
Add support for Innolux G156HCE-L01 15.6" 1920x1080 24bpp
dual-link
On 8/3/23 16:23, Luca Ceresoli wrote:
Hi Marek,
Hi,
On Mon, 31 Jul 2023 23:02:58 +0200
Marek Vasut wrote:
Add support for Innolux G156HCE-L01 15.6" 1920x1080 24bpp
dual-link LVDS TFT panel. Documentation is available at [1].
Interesting, I'm bringing up this exact panel righ
On 8/2/23 19:49, Abhinav Kumar wrote:
Hi Marek
On 8/2/2023 10:25 AM, Marek Vasut wrote:
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut
On 8/2/23 20:16, Dmitry Baryshkov wrote:
On Wed, 2 Aug 2023 at 20:34, Marek Vasut wrote:
On 8/2/23 15:38, Dmitry Baryshkov wrote:
On 02/08/2023 11:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard 845c
(SDM845) devboard.
There's a mismatch
On 8/2/23 14:37, Neil Armstrong wrote:
On 02/08/2023 14:28, Marek Vasut wrote:
On 8/2/23 14:07, Marek Vasut wrote:
On 8/2/23 10:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard
845c
(SDM845) devboard.
There's a mismatch on the real action
- MIPI_DSI_MODE_VIDEO_NO_HFP
- MIPI_DSI_MODE_VIDEO_NO_HBP
which leads to a non-working display on qcom platforms.
[1] 8ddce13ae696 ("drm/bridge: lt9611: Do not generate HFP/HBP/HSA and
EOT packet")
Cc: Marek Vasut
Cc: Robert Foss
Cc: Jagan Teki
Cc: Dmitry Baryshkov
Cc: Abhinav Kumar
Fixes: 8ddce13ae69 (&
On 8/2/23 15:16, Dmitry Baryshkov wrote:
On 02/08/2023 15:07, Marek Vasut wrote:
On 8/2/23 10:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard
845c
(SDM845) devboard.
There's a mismatch on the real action of the following flags
On 8/2/23 14:38, Dmitry Baryshkov wrote:
On 02/08/2023 15:07, Marek Vasut wrote:
On 8/2/23 10:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard
845c
(SDM845) devboard.
There's a mismatch on the real action of the following flags
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP means the HBP period is just skipped by
DSIM
On 8/2/23 14:07, Marek Vasut wrote:
On 8/2/23 10:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard 845c
(SDM845) devboard.
There's a mismatch on the real action of the following flags:
- MIPI_DSI_MODE_VIDEO_NO_HSA
- MIPI_DSI_MODE_VIDEO_NO_HFP
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP means the HBP period is just skipped by
DSIM.
Maybe there is a need for new set of flags which differentiate
between HBP skipped (i.e. NO HBP) and HBP
to a non-working display on qcom platforms.
[1] 8ddce13ae696 ("drm/bridge: lt9611: Do not generate HFP/HBP/HSA and EOT
packet")
Cc: Marek Vasut
Cc: Robert Foss
Cc: Jagan Teki
Cc: Dmitry Baryshkov
Cc: Abhinav Kumar
Fixes: 8ddce13ae69 ("drm/bridge: lt9611: Do not generate HFP/
On 7/31/23 23:34, Doug Anderson wrote:
Hi,
On Mon, Jul 31, 2023 at 2:15 PM Marek Vasut wrote:
On 7/31/23 21:50, Doug Anderson wrote:
Hi,
On Mon, Jul 31, 2023 at 11:03 AM Marek Vasut wrote:
On 7/24/23 15:49, Doug Anderson wrote:
Hi,
[...]
Maybe the EPROBE_DEFER actually happens
On 7/31/23 21:50, Doug Anderson wrote:
Hi,
On Mon, Jul 31, 2023 at 11:03 AM Marek Vasut wrote:
On 7/24/23 15:49, Doug Anderson wrote:
Hi,
[...]
Maybe the EPROBE_DEFER actually happens and triggers the failure ?
I could certainly believe that EPROBE_DEFER is involved.
So
Add entry for Innolux G156HCE-L01 15.6" 1920x1080 24bpp
dual-link LVDS TFT panel. Documentation is available at [1].
[1]
https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/Innolux/G156HCE-L01_Rev.C3_Datasheet.pdf
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Daniel Vette
plays/Innolux/G156HCE-L01_Rev.C3_Datasheet.pdf
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Daniel Vetter
Cc: David Airlie
Cc: Krzysztof Kozlowski
Cc: Neil Armstrong
Cc: Rob Herring
Cc: Sam Ravnborg
Cc: Thierry Reding
Cc: devicet...@vger.kernel.org
Cc: dri-devel@lists.freedeskto
On 7/24/23 15:49, Doug Anderson wrote:
Hi,
[...]
Maybe the EPROBE_DEFER actually happens and triggers the failure ?
I could certainly believe that EPROBE_DEFER is involved.
So no, it is not. It is difficult to set this up and access the signals,
but so I did.
What happens is this:
On 7/18/23 21:33, Doug Anderson wrote:
Hi,
On Tue, Jul 18, 2023 at 10:37 AM Marek Vasut wrote:
On 7/18/23 18:15, Doug Anderson wrote:
Hi,
Hi,
On Tue, Jul 18, 2023 at 8:36 AM Marek Vasut wrote:
On 7/18/23 16:17, Doug Anderson wrote:
Hi,
Hi,
On Sun, Jul 9, 2023 at 6:52 AM Marek
Drain command transfer FIFO before
transfer").
Fixes: 14806c641582 ("Drain command transfer FIFO before transfer")
Signed-off-by: Marek Szyprowski
Reviewed-by: Marek Vasut
Thanks !
rom Toshiba
seem to always make this value equal to the HFP + 10 for DSI->DP
use-case. For DSI->DPI this value should be > 2 and for DPI->DP
it seems to always be 0x64.
Signed-off-by: David Jander
Signed-off-by: Lucas Stach
Tested-by: Marek Vasut # TC9595
Reviewed-by: Marek Vasut
On 7/18/23 18:15, Doug Anderson wrote:
Hi,
Hi,
On Tue, Jul 18, 2023 at 8:36 AM Marek Vasut wrote:
On 7/18/23 16:17, Doug Anderson wrote:
Hi,
Hi,
On Sun, Jul 9, 2023 at 6:52 AM Marek Vasut wrote:
The unprepared_time has to be initialized during probe to probe time
ktime, otherwise
On 7/18/23 16:17, Doug Anderson wrote:
Hi,
Hi,
On Sun, Jul 9, 2023 at 6:52 AM Marek Vasut wrote:
The unprepared_time has to be initialized during probe to probe time
ktime, otherwise panel_simple_resume() panel_simple_wait() call may
wait too short time, or no time at all, which would
On 7/18/23 15:18, Marek Szyprowski wrote:
Samsung DSIM used in older Exynos SoCs (like Exynos 4210, 4x12, 3250)
doesn't report empty level of packer header FIFO. In case of those SoCs,
use the old way of waiting for empty command tranfsfer FIFO, removed
recently by commit 14806c641582 ("Drain
On 7/13/23 20:09, Abhinav Kumar wrote:
On 7/12/2023 10:41 AM, Marek Vasut wrote:
On 7/9/23 03:03, Abhinav Kumar wrote:
On 7/7/2023 1:47 AM, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry
On 7/12/23 20:52, Tim Harvey wrote:
Greetings,
Tim,
I've noticed a regression in 6.5-rc1 that I'm having trouble bisecting
between 6.4 with regards to imx8mm MIPI DSI.
I'm testing on an imx8mm-venice-gw72xx-0x with the following display:
- Powertip PH800480T013-IDF02 compatible panel
-
Teki
wrote:
Hi Amit,
On Wed, Jul 5, 2023 at 10:15 AM Amit Pundir
wrote:
Hi Marek,
On Wed, 5 Jul 2023 at 01:48, Marek Vasut wrote:
Do not generate the HS front and back porch gaps, the HSA gap and
EOT packet, as these packets are not required. This makes the
bridge
work with Samsung
On 7/12/23 17:10, Paulo Pavacic wrote:
Hi,
[...]
Or whether it makes sense to outright have a separate driver. The later
would introduce duplication, but maybe that much duplication is OK.
I would like to create new driver because panel-st7701 seems to be
outdated and is using non-standard
On 7/12/23 14:07, Paulo Pavacic wrote:
Hello all,
sub, 8. srp 2023. u 14:53 Marek Vasut napisao je:
On 7/7/23 17:26, Paulo Pavacic wrote:
Hello Marek,
Hi,
čet, 6. srp 2023. u 17:26 Marek Vasut napisao je:
On 7/6/23 17:18, Paulo Pavacic wrote:
Hello Linus,
čet, 22. lip 2023. u 10:22
ndling")
whatever is left in this driver is just assigned and never used.
Drop the remaining parts.
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: David Airlie
Cc: Douglas Anderson
Cc: Neil Armstrong
Cc: Sam Ravnborg
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/panel/p
On 7/9/23 17:08, Sam Ravnborg wrote:
Hi Marek.
Hi,
On Sun, Jul 09, 2023 at 03:52:31PM +0200, Marek Vasut wrote:
The unprepared_time has to be initialized during probe to probe time
ktime, otherwise panel_simple_resume() panel_simple_wait() call may
wait too short time, or no time at all
the delay is at least what the panel requires from the
time kernel started. The unprepared_time is then updated every time
the panel is suspended in panel_simple_suspend() too.
Fixes: e5e30dfcf3db ("drm: panel: simple: Defer unprepare delay till next
prepare to shorten it")
Signed-off-by: M
The connector type and pixel format are missing for this panel,
add them to prevent various drivers from failing to determine
either of those parameters.
Fixes: 7ee933a1d5c4 ("drm/panel: simple: Add support for AUO T215HVN01")
Signed-off-by: Marek Vasut
---
Cc: Daniel Vetter
Cc: Da
The ULPS EXIT is initialized to 0xaf in downstream BSP as well as older
revisions of this patchset, in newer revisions of the DSIM patchset it
was left out and set to 0. Fix it.
Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support")
Signed-off-by: Marek Vas
On 7/8/23 21:40, Dmitry Baryshkov wrote:
On Sat, 8 Jul 2023 at 22:39, Marek Vasut wrote:
On 7/8/23 17:53, Dmitry Baryshkov wrote:
On 08/07/2023 18:40, Marek Vasut wrote:
On 7/7/23 10:47, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir
On 7/8/23 17:53, Dmitry Baryshkov wrote:
On 08/07/2023 18:40, Marek Vasut wrote:
On 7/7/23 10:47, Neil Armstrong wrote:
On 07/07/2023 09:18, Neil Armstrong wrote:
Hi,
On 06/07/2023 11:20, Amit Pundir wrote:
On Wed, 5 Jul 2023 at 11:09, Dmitry Baryshkov
wrote:
[Adding freedreno@ to cc
On 6/8/23 10:11, Lucas Stach wrote:
Am Mittwoch, dem 07.06.2023 um 15:54 +0200 schrieb Marek Vasut:
On 6/7/23 14:53, Lucas Stach wrote:
Am Freitag, dem 02.06.2023 um 23:34 +0200 schrieb Marek Vasut:
On 6/2/23 21:15, Lucas Stach wrote:
From: David Jander
The documentation is not clear about
delay to be safe.
Signed-off-by: David Jander
Signed-off-by: Lucas Stach
Tested-by: Marek Vasut # TC9595
Reviewed-by: Marek Vasut
, 2023 at 10:15 AM Amit Pundir
wrote:
Hi Marek,
On Wed, 5 Jul 2023 at 01:48, Marek Vasut wrote:
Do not generate the HS front and back porch gaps, the HSA gap and
EOT packet, as these packets are not required. This makes the bridge
work with Samsung DSIM on i.MX8MM and i.MX8MP.
This patch broke
On 7/7/23 17:26, Paulo Pavacic wrote:
Hello Marek,
Hi,
čet, 6. srp 2023. u 17:26 Marek Vasut napisao je:
On 7/6/23 17:18, Paulo Pavacic wrote:
Hello Linus,
čet, 22. lip 2023. u 10:22 Linus Walleij napisao je:
On Wed, Jun 21, 2023 at 5:09 PM Paulo Pavacic wrote:
A lot
On 7/6/23 17:18, Paulo Pavacic wrote:
Hello Linus,
čet, 22. lip 2023. u 10:22 Linus Walleij napisao je:
On Wed, Jun 21, 2023 at 5:09 PM Paulo Pavacic wrote:
A lot of modifications to st7701 are required. I believe it would
result in a driver that doesn't look or work the same. e.g compare
On 7/5/23 15:13, Frank Binns wrote:
On Mon, 2023-06-26 at 10:38 -0500, Adam Ford wrote:
On Mon, Jun 26, 2023 at 8:22 AM Frank Binns wrote:
Hi Adam,
On Sat, 2023-06-17 at 07:48 -0500, Adam Ford wrote:
On Tue, Jun 13, 2023 at 10:20 AM Sarah Walker wrote:
Read the GPU ID register at probe
On 7/5/23 07:46, Jagan Teki wrote:
On Wed, Jul 5, 2023 at 11:09 AM Dmitry Baryshkov
wrote:
[Adding freedreno@ to cc list]
On Wed, 5 Jul 2023 at 08:31, Jagan Teki wrote:
Hi Amit,
On Wed, Jul 5, 2023 at 10:15 AM Amit Pundir wrote:
Hi Marek,
On Wed, 5 Jul 2023 at 01:48, Marek Vasut
On 7/3/23 09:27, Neil Armstrong wrote:
On 15/06/2023 22:15, Marek Vasut wrote:
Wait until the command transfer FIFO is empty before loading in the next
command. The previous behavior where the code waited until command
transfer
FIFO was not full suffered from transfer corruption, where
Add support for handling the HS/VS sync signals polarity in the bridge
driver, otherwise e.g. DSIM bridge feeds the TC358762 inverted polarity
sync signals and the image is shifted to the left, up, and wobbly.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc: David Airlie
The register content and behavior is very similar to TC358764 VP_CTRL.
All the bits except for unknown bit 6 also seem to match, even though
the datasheet is just not available. Add a comment and reuse the bit
definitions.
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: Daniel Vetter
Cc
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