consisten with the current style. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc:
The register PHTR bitfield TESTDOUT is not a single bit, but a
bitfield. Add a MASK macro and a _TEST bitfield value, which is
used by the driver to poll for completion. No functional change.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent
On 9/29/25 6:20 PM, Rain Yang wrote:
On Mon, Sep 29, 2025 at 03:09:01PM +0200, Marek Vasut wrote:
On 9/29/25 11:57 AM, Rain Yang wrote:
On Mon, Sep 29, 2025 at 02:23:01AM +0200, Marek Vasut wrote:
On 9/26/25 7:57 AM, Peng Fan wrote:
Hello Peng,
On Thu, Sep 25, 2025 at 10:38:31PM +0200
On 9/28/25 10:24 AM, Rain Yang wrote:
On Fri, Sep 26, 2025 at 03:32:46PM +0200, Marek Vasut wrote:
On 9/26/25 11:18 AM, Rain Yang wrote:
Hello Jiyu,
as the 0x4d810008 is a write-once register and whose operation has been moved
into the SM side,
so please drop the reset change.
can you also
mi_perf in i.MX95.
Right now, it is indeed fixed at 1 GHz .
--
Best regards,
Marek Vasut
ticket in this website[2].
I use mainline U-Boot 2025.07 with about 10 extra patches, but nothing
significant. I don't think this is U-Boot issue, is it ?
I can rebuild SM, which commit in SM (from imx-sm repository) do I need to
use ?
--
Best regards,
Marek Vasut
Hi Marek,
I think the prob
The instance of the GPU populated in i.MX95 is the G310, describe this
GPU in the DT. Include dummy GPU voltage regulator and OPP tables.
Signed-off-by: Marek Vasut
---
Cc: Boris Brezillon
Cc: Conor Dooley
Cc: David Airlie
Cc: Fabio Estevam
Cc: Jiyu Yang (OSS)
Cc: Krzysztof Kozlowski
Cc
The instance of the GPU populated in Freescale i.MX95 is the
Mali G310, document support for this variant.
Reviewed-by: Alexander Stein
Reviewed-by: Frank Li
Reviewed-by: Rob Herring (Arm)
Signed-off-by: Marek Vasut
---
Cc: Boris Brezillon
Cc: Conor Dooley
Cc: David Airlie
Cc: Fabio
On 9/25/25 2:48 PM, Sebastian Reichel wrote:
Hello Sebastian,
On Thu, Sep 25, 2025 at 02:15:41AM +0200, Marek Vasut wrote:
On 9/24/25 11:46 PM, Sebastian Reichel wrote:
From: Sebastian Reichel
I planned to set the polarity of horizontal and vertical sync, but
accidentally described
Convert register bitfields to GENMASK() macro where applicable.
Use FIELD_PREP() throughout the driver.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
On 9/24/25 3:18 AM, Sebastian Reichel wrote:
Hello Sebastian,
On Tue, Sep 23, 2025 at 04:26:16PM +0300, Laurent Pinchart wrote:
I wonder if the DRM_MODE_FLAG_P[HV]SYNC flags are always the exact
opposite of DRM_MODE_FLAG_N[HV]SYNC. It's probably fine to assume that
here. A quick grep showed on
On 9/23/25 4:16 PM, Laurent Pinchart wrote:
Hello Laurent,
[...]
#define CLOCKSET1 0x101c
-#define CLOCKSET1_LOCK_PHY (1 << 17)
-#define CLOCKSET1_CLKSEL (1 << 8)
-#define CLOCKSET1_CLKINSEL_MASK(3 << 2)
+#define CLOCKSET1_LOCK_PH
consisten with the current style. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc:
Convert register bits to BIT() macro where applicable. This is done
automatically using regex 's@(1 << \([0-9]\+\))@BIT(\1)', except for
bitfields which are manually updated to use GENMASK().
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bing
is done at the very end of this series in the last two patches.
Reviewed-by: Laurent Pinchart
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
Cc: Thomas
of this series in the last two patches.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
Cc: Thomas Zimmermann
Cc: Tomi Valkeinen
Cc: dri-devel
The register TXVMSETR bitfield PIXWDTH is not a single bit, but a
bitfield. Add a MASK macro and document that the only allowed value
that can ever be written into the bitfield is the current value, 1.
No functional change.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
Cc: Thomas Zimmermann
Cc: Tomi Valkeinen
Cc: dri-devel@lists.freedesktop.org
Cc: linux-renesas-...@vger.
On 9/23/25 3:26 PM, Laurent Pinchart wrote:
Hi Marek,
Hello Laurent,
On Mon, Sep 22, 2025 at 08:55:03PM +0200, Marek Vasut wrote:
Introduce TXVMVPRMSET0R_BPP_MASK macro and use FIELD_PREP() to generate
appropriate bitfield from mask and value without bitshift, assign this
value into
consisten with the current style. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc:
should not have any adverse effect on existing hardware.
Marek Vasut (9):
drm/rcar-du: dsi: Fix missing parameter in RXSETR_...EN macros
drm/rcar-du: dsi: Deduplicate mipi_dsi_pixel_format_to_bpp() usage
drm/rcar-du: dsi: Clean up VCLKSET register macros
drm/rcar-du: dsi: Clean up CLOCKSET1
The RXSETR_CRCEN(n) and RXSETR_ECCEN(n) macros both take parameter (n),
add the missing macro parameter. Neither of those macros is used by the
driver, so for now the bug is harmless.
Fixes: 685e8dae19df ("drm/rcar-du: dsi: Implement DSI command support")
Signed-off-by: Marek Vasut
---
Call mipi_dsi_pixel_format_to_bpp() once in rcar_mipi_dsi_set_display_timing()
and store the value into a variable. This slightly simplifies the code.
No functional change.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc
Convert register bitfields to GENMASK() macro where applicable.
Use FIELD_PREP() throughout the driver.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
is done at the very end of this series in the last two patches.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
Cc: Thomas Zimmermann
Cc: Tomi Valkeinen
of this series in the last two patches.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
Cc: Thomas Zimmermann
Cc: Tomi Valkeinen
Cc: dri-devel
. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
Cc
This is the GPU/NPU combined device found on the ST STM32MP25 SoC.
Feature bits taken from the downstream kernel driver 6.4.21.
Signed-off-by: Marek Vasut
---
Cc: Christian Gmeiner
Cc: David Airlie
Cc: Lucas Stach
Cc: Simona Vetter
Cc: dri-devel@lists.freedesktop.org
Cc: etna
tood, thank you.
--
Best regards,
Marek Vasut
On 9/19/25 5:21 PM, Tomi Valkeinen wrote:
Hello Tomi,
On 05/09/2025 00:01, Marek Vasut wrote:
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the panel
On 9/16/25 11:52 AM, Neil Armstrong wrote:
On 16/09/2025 10:15, Marek Vasut wrote:
On 9/5/25 9:51 AM, Neil Armstrong wrote:
On 04/09/2025 22:01, Marek Vasut wrote:
The ILI9881C is a DSI panel, which can be tied to a DSI controller
using OF graph port/endpoint. Allow the port subnode in the
On 9/16/25 1:54 PM, Neil Armstrong wrote:
On 16/09/2025 13:48, Marek Vasut wrote:
On 9/16/25 11:52 AM, Neil Armstrong wrote:
On 16/09/2025 10:15, Marek Vasut wrote:
On 9/5/25 9:51 AM, Neil Armstrong wrote:
On 04/09/2025 22:01, Marek Vasut wrote:
The ILI9881C is a DSI panel, which can be
ite[2].
I use mainline U-Boot 2025.07 with about 10 extra patches, but nothing
significant. I don't think this is U-Boot issue, is it ?
I can rebuild SM, which commit in SM (from imx-sm repository) do I need
to use ?
--
Best regards,
Marek Vasut
On 9/16/25 12:06 PM, Rain Yang wrote:
Hello everyone,
you're right.
*0x4d810008=1, this register is a write-once register, so it was moved into SM
since imx 6.12.3 release, and latest 6.6.52 release. some document work is still
needed in the future.
Hi Marek,
thanks for your effort to make the
On 9/8/25 2:54 PM, Marek Vasut wrote:
Hello Tomi,
On 05/09/2025 00:01, Marek Vasut wrote:
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the panel node
On 9/5/25 9:51 AM, Neil Armstrong wrote:
On 04/09/2025 22:01, Marek Vasut wrote:
The ILI9881C is a DSI panel, which can be tied to a DSI controller
using OF graph port/endpoint. Allow the port subnode in the binding.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc
On 9/10/25 9:37 AM, Nilesh Laad wrote:
From: Yi Zhang
Add bindings for lt9211c.
Signed-off-by: Yi Zhang
Signed-off-by: Nilesh Laad
---
.../bindings/display/bridge/lontium,lt9211c.yaml | 113 +
1 file changed, 113 insertions(+)
diff --git
a/Documentation/devicetree/
On 9/8/25 8:55 AM, Tomi Valkeinen wrote:
Hi,
Hello Tomi,
On 31/08/2025 22:04, Marek Vasut wrote:
Implement support for DSI command transfer. Transmission of both Short
Packet and Long Packet is implemented, so is command transmission to
request response from peripheral device and
On 9/8/25 9:43 AM, Tomi Valkeinen wrote:
Hi,
Hello Tomi,
On 05/09/2025 00:01, Marek Vasut wrote:
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the
Add configuration for the 5" Raspberry Pi 720x1280 DSI panel
based on ili9881. This uses 10px longer horizontal sync pulse
and 10px shorter HBP to avoid very short hsync pulse.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzy
On 9/4/25 5:20 PM, Boris Brezillon wrote:
On Thu, 4 Sep 2025 16:54:38 +0200
Marek Vasut wrote:
On 9/4/25 4:04 PM, Boris Brezillon wrote:
Hello Boris,
I suspect the extra soft reset I did before "un-halted" the GPU and
allowed it to proceed.
Hm, not quite. I mean, you sti
Add configuration for the 5" Raspberry Pi 720x1280 DSI panel
based on ili9881. This uses 10px longer horizontal sync pulse
and 10px shorter HBP to avoid very short hsync pulse.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzy
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the panel node is
optional. Include example binding with panel.
Signed-off-by: Marek Vasut
---
Cc: Conor
On 9/5/25 5:02 PM, Rob Herring (Arm) wrote:
On Thu, 04 Sep 2025 23:01:21 +0200, Marek Vasut wrote:
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the
On 9/5/25 3:18 PM, Devarsh Thakkar wrote:
Hi Marek,
Hi,
Thanks for the patch.
On 05/09/25 02:26, Marek Vasut wrote:
Add configuration for the 5" Raspberry Pi 720x1280 DSI panel
based on ili9881. This uses 10px longer horizontal sync pulse
and 10px shorter HBP to avoid very short
Make all ILI9881C_COMMAND_INSTR() parameters consistently lowercase.
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Neil Armstrong
Cc: Rob
Rename dsi-encoder@ node to dsi@ node to follow node name pattern
in Documentation/devicetree/bindings/display/dsi-controller.yaml .
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Krzysztof Kozlowski
Cc
Document the 5" Raspberry Pi 720x1280 DSI panel based on ili9881.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Neil Armstrong
Cc: Rob Herring
Cc: Simona V
The ILI9881C is a DSI panel, which can be tied to a DSI controller
using OF graph port/endpoint. Allow the port subnode in the binding.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc
On 9/4/25 10:23 PM, Dmitry Baryshkov wrote:
[...]
@@ -80,14 +83,14 @@ required:
- resets
- ports
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
#include
#include
-dsi0: dsi-encoder@fed8 {
+dsi0: dsi@fed8 {
As yo
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the panel node is
optional. Include example binding with panel.
Signed-off-by: Marek Vasut
---
Cc: Conor
Rename dsi-encoder@ node to dsi@ node to follow node name pattern
in Documentation/devicetree/bindings/display/dsi-controller.yaml .
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Krzysztof Kozlowski
Cc
Rename dsi-encoder@ node to dsi@ node to follow node name pattern
in Documentation/devicetree/bindings/display/dsi-controller.yaml .
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Krzysztof Kozlowski
Cc
On 9/4/25 10:21 PM, Dmitry Baryshkov wrote:
[...]
+ ILI9881C_COMMAND_INSTR(0xD1, 0x52),
+ ILI9881C_COMMAND_INSTR(0xD2, 0x63),
+ ILI9881C_COMMAND_INSTR(0xD3, 0x39),
+};
Should the hex be lower-cased? Other than that LGTM.
Fixed in V2, thanks.
The other panel entries are fix
Document the 5" Raspberry Pi 720x1280 DSI panel based on ili9881.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Neil Armstrong
Cc: Rob Herring
Cc: Simona V
Rename dsi-encoder@ node to dsi@ node to follow node name pattern
in Documentation/devicetree/bindings/display/dsi-controller.yaml .
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Krzysztof Kozlowski
Cc
Rename dsi-encoder@ node to dsi@ node to follow node name pattern
in Documentation/devicetree/bindings/display/dsi-controller.yaml .
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Krzysztof Kozlowski
Cc
Rename dsi-encoder@ node to dsi@ node to follow node name pattern
in Documentation/devicetree/bindings/display/dsi-controller.yaml .
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Krzysztof Kozlowski
Cc
On 9/4/25 4:04 PM, Boris Brezillon wrote:
Hello Boris,
I suspect the extra soft reset I did before "un-halted" the GPU and
allowed it to proceed.
Hm, not quite. I mean, you still need to explicitly boot the MCU after
a reset, which is what the write to MCU_CONTROL [1] does. What the
soft-rese
On 9/4/25 4:39 PM, Alexander Stein wrote:
Hi,
Am Donnerstag, 4. September 2025, 15:52:38 CEST schrieb Marek Vasut:
On 9/4/25 8:36 AM, Alexander Stein wrote:
Hello Alexander,
Maybe the GPU remains halted because
setting the GLB_HALT stops command stream processing, and the GPU never
samples
On 3/25/25 3:52 PM, Boris Brezillon wrote:
Hello Boris,
sorry for the late reply.
Hm, that might be the cause of the fast reset issue (which is a fast
resume more than a fast reset BTW): if you re-assert the reset line on
runtime suspend, I guess this causes a full GPU reset, and the MCU ends
On 9/4/25 8:36 AM, Alexander Stein wrote:
Hello Alexander,
Maybe the GPU remains halted because
setting the GLB_HALT stops command stream processing, and the GPU never
samples the clearing of GLB_HALT and therefore remains halted forever ?
Exactly that, and that's expected.
FYI: in a new re
On 9/4/25 8:22 AM, Boris Brezillon wrote:
Hello Marek,
Hello Boris,
Can you please test the following patch (also attached) on one of your
devices, and tell me what the status is at the end . The diff sets the
GLB_HALT bit and then clears it again, which I suspect should first halt
the GPU an
On 9/4/25 11:54 AM, Peng Fan wrote:
Hello Peng,
@@ -1890,6 +1919,35 @@ netc_emdio: mdio@0,0 {
};
};
+ gpu_blk_ctrl: reset-controller@4d81 {
+ compatible = "nxp,imx95-gpu-blk-ctrl";
+ reg = <0x0 0x4d8100
On 9/1/25 11:22 AM, Tomi Valkeinen wrote:
Hello Tomi,
Would you like to pick this up via drm-misc , or shall I ?
I'll push to drm-misc. Thanks!
Thank you
--
Best regards,
Marek Vasut
is performed purely using controller register interface. Short Packet
transfer can transfer up to 2 Bytes of data, Long Packet transfer can
transfer up to 16 Bytes of data.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc
On 8/18/25 9:20 AM, Tomi Valkeinen wrote:
Hello Tomi,
If yes, then it might take
much longer until the command can be transferred.
Do you know the upper limit , is that one or two frame times ?
If using DSI video mode and the stream is on, the DSI TX has to
interleave the commands either to
On 8/14/25 7:54 AM, Tomi Valkeinen wrote:
Hello Tomi,
On 14/08/2025 00:08, Marek Vasut wrote:
Remove fixed PPI lane count setup. The R-Car DSI host is capable
of operating in 1..4 DSI lane mode. Remove the hard-coded 4-lane
configuration from PPI register settings and instead configure
the
On 8/12/25 4:36 PM, Tomi Valkeinen wrote:
Hello Tomi,
On 08/06/2025 17:24, Marek Vasut wrote:
Implement support for DSI command transfer mode. Transmission of both Short
I constantly kept reading "DSI command mode support". So I was quite
confused for a bit =). Maybe avoid the us
On 8/14/25 7:39 AM, Tomi Valkeinen wrote:
Hello Tomi,
The 1/2/3 lane mode was already implemented in the driver, except it was
broken.
If it never worked, was it broken or not implemented? How much code the
original driver must have for the feature to have the feature
"implemented, just broke
PPISETR register
DLEN bitfield. Make sure the LANECNT and DLEN bitfields are
configured to match.
Fixes: 155358310f01 ("drm: rcar-du: Add R-Car DSI driver")
Cc:
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
C
On 8/13/25 9:34 AM, Tomi Valkeinen wrote:
Hi,
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
index b3e57217ae63..cefa7e92b5b8 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesa
On 8/13/25 9:42 AM, Tomi Valkeinen wrote:
Hi,
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
index a6b276f1d6ee..b3e57217ae63 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesa
On 8/13/25 8:59 AM, Geert Uytterhoeven wrote:
On Tue, 12 Aug 2025 at 22:05, Laurent Pinchart
wrote:
On Tue, Aug 12, 2025 at 09:32:36PM +0200, Marek Vasut wrote:
On 8/12/25 3:26 PM, Tomi Valkeinen wrote:
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
b/drivers/gpu/drm
On 8/12/25 3:30 PM, Tomi Valkeinen wrote:
Hi,
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
index b3e57217ae63..cefa7e92b5b8 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesa
On 8/12/25 3:26 PM, Tomi Valkeinen wrote:
Hi,
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
index a6b276f1d6ee..b3e57217ae63 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesa
On 6/16/25 6:26 PM, Neil Armstrong wrote:
On 16/06/2025 18:05, Marek Vasut wrote:
On 6/16/25 1:45 PM, Neil Armstrong wrote:
On 13/06/2025 12:54, Marek Vasut wrote:
On 6/13/25 11:29 AM, Neil Armstrong wrote:
On 12/06/2025 01:49, Marek Vasut wrote:
Use u8 to hold lane count in struct
On 6/16/25 1:45 PM, Neil Armstrong wrote:
On 13/06/2025 12:54, Marek Vasut wrote:
On 6/13/25 11:29 AM, Neil Armstrong wrote:
On 12/06/2025 01:49, Marek Vasut wrote:
Use u8 to hold lane count in struct ili9881c_desc {} to avoid
alignment gap between default_address_mode and lanes members.
The
On 6/13/25 11:29 AM, Neil Armstrong wrote:
On 12/06/2025 01:49, Marek Vasut wrote:
Use u8 to hold lane count in struct ili9881c_desc {} to avoid
alignment gap between default_address_mode and lanes members.
The ili9881c controller can only operate up to 4 DSI lanes, so
there is no chance this
Uytterhoeven
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Jessica Zhang
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Neil Armstrong
Cc: Simona Vetter
Cc: Thomas Zimmermann
Cc: dri-devel@lists.freedesktop.org
Cc: linux-renesas-...@vger.kernel.org
---
drivers/gpu/drm/panel
Not all panels use all 4 data lanes, so allow configuration based
on the compatible string.
Signed-off-by: Marek Vasut
---
Based on https://github.com/raspberrypi/linux 0d7ac78a3dd9 ("Extending ili9881c
driver support for nwe080 panel")
by Dave Stevenson and others
---
Cc: Conor
Document the 7" Raspberry Pi 720x1280 DSI panel based on ili9881.
Signed-off-by: Marek Vasut
---
Cc: Conor Dooley
Cc: Dave Stevenson
Cc: David Airlie
Cc: Jessica Zhang
Cc: Krzysztof Kozlowski
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Neil Armstrong
Cc: Rob Herring
Cc: Simona V
Convert register bits to BIT() macro where applicable. This is done
automatically using regex 's@(1 << \([0-9]\+\))@BIT(\1)', except for
two BPP_18 macros which are not bits, but bitfields, and which are
not modified.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert
The R-Car DSI host is capable of operating in 1..4 DSI lane mode.
Remove hard-coded 4-lane configuration from PPI register settings
and instead configure the PPI lane count according to lane count
information already obtained by this driver instance.
Signed-off-by: Marek Vasut
---
Cc: David
Use BIT() macro. Clean up lane count handling for non-4-lane panels.
Implement support for DSI command transfer mode using register based
access, with maximum payload length of 16 Bytes in Long Packet.
Marek Vasut (4):
drm/rcar-du: dsi: Convert register bits to BIT() macro
drm/rcar-du: dsi
transfer is
performed purely using controller register interface. Short Packet transfer
can transfer up to 2 Bytes of data, Long Packet transfer can transfer up to
16 Bytes of data.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc
Add configuration for the 7" Raspberry Pi 720x1280 DSI panel
based on ili9881.
Signed-off-by: Marek Vasut
---
Based on https://github.com/raspberrypi/linux 0d7ac78a3dd9 ("Extending ili9881c
driver support for nwe080 panel")
by Dave Stevenson and others
---
Cc: Conor Dooley
Cc:
the LANECNT and DLEN
bitfields are configured to match.
Signed-off-by: Marek Vasut
---
Cc: David Airlie
Cc: Geert Uytterhoeven
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Magnus Damm
Cc: Maxime Ripard
Cc: Simona Vetter
Cc: Thomas Zimmermann
Cc: Tomi Valkeinen
Cc
On 3/25/25 3:35 PM, Boris Brezillon wrote:
On Tue, 25 Mar 2025 14:50:32 +0100
Marek Vasut wrote:
On 3/25/25 8:43 AM, Boris Brezillon wrote:
On Tue, 25 Mar 2025 00:37:59 +0100
Marek Vasut wrote:
On 3/24/25 9:43 AM, Boris Brezillon wrote:
[...]
@@ -563,6 +585,7 @@ int
On 3/3/25 1:42 PM, Boris Brezillon wrote:
Hi,
This looks like it has been part of a R50 release of the DDK, which is recent
enough to consider it up-to-date. The issues you're seeing with fast resume are
probably due to some integration issues or other quirks.
Boris has the most recent experie
On 3/25/25 3:12 PM, Philipp Zabel wrote:
On Mo, 2025-03-24 at 20:05 +0100, Marek Vasut wrote:
On 3/24/25 9:43 AM, Boris Brezillon wrote:
[...]
@@ -563,6 +585,7 @@ int panthor_device_suspend(struct device *dev)
panthor_devfreq_suspend(ptdev);
+ reset_control_assert(ptdev->res
On 3/25/25 8:43 AM, Boris Brezillon wrote:
On Tue, 25 Mar 2025 00:37:59 +0100
Marek Vasut wrote:
On 3/24/25 9:43 AM, Boris Brezillon wrote:
[...]
@@ -563,6 +585,7 @@ int panthor_device_suspend(struct device *dev)
panthor_devfreq_suspend(ptdev);
+ reset_control_assert(ptdev
On 3/24/25 9:43 AM, Boris Brezillon wrote:
[...]
@@ -563,6 +585,7 @@ int panthor_device_suspend(struct device *dev)
panthor_devfreq_suspend(ptdev);
+ reset_control_assert(ptdev->resets);
Hm, that might be the cause of the fast reset issue (which is a fast
resume more than a fast rese
On 3/24/25 8:02 AM, Alexander Stein wrote:
Hi,
@@ -1890,6 +1919,35 @@ netc_emdio: mdio@0,0 {
};
};
+ gpu_blk_ctrl: reset-controller@4d81 {
+ compatible = "nxp,imx95-gpu-blk-ctrl";
+ reg = <0x0 0x4d81000
On 3/24/25 9:43 AM, Boris Brezillon wrote:
[...]
@@ -563,6 +585,7 @@ int panthor_device_suspend(struct device *dev)
panthor_devfreq_suspend(ptdev);
+ reset_control_assert(ptdev->resets);
Hm, that might be the cause of the fast reset issue (which is a fast
resume more than a fast rese
The instance of the GPU populated in Freescale i.MX95 does require
release from reset by writing into a single GPUMIX block controller
GPURESET register bit 0. Document support for this reset register.
Signed-off-by: Marek Vasut
---
Cc: Boris Brezillon
Cc: Conor Dooley
Cc: David Airlie
Cc
is useful on Freescale i.MX95 which
does have two power domains.
Signed-off-by: Marek Vasut
---
Cc: Boris Brezillon
Cc: Conor Dooley
Cc: David Airlie
Cc: Fabio Estevam
Cc: Krzysztof Kozlowski
Cc: Liviu Dudau
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Pengutronix Kernel Team
Cc: Philipp
The instance of the GPU populated in Freescale i.MX95 does require
release from reset by writing into a single GPUMIX block controller
GPURESET register bit 0. Document support for one optional reset.
Acked-by: Rob Herring (Arm)
Reviewed-by: Frank Li
Signed-off-by: Marek Vasut
---
Cc: Boris
The instance of the GPU populated in i.MX95 is the G310.
Add support for the GPUMIX reset via simple-reset driver,
add reset and multiple power domains support into panthor
GPU driver, add iMX95 GPU support into panthor driver and
describe the iMX95 GPU in imx95.dtsi DT.
Marek Vasut (9):
dt
The instance of the GPU populated in Freescale i.MX95 does require
release from reset by writing into a single GPUMIX block controller
GPURESET register bit 0. Implement support for one optional reset.
Signed-off-by: Marek Vasut
---
Cc: Boris Brezillon
Cc: Conor Dooley
Cc: David Airlie
Cc
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