llection series [1].
[1]:
https://lore.kernel.org/linux-arm-msm/20230521-drm-panels-sony-v1-0-541c341d6...@somainline.org/
---
Marijn Suijten (15):
arm64: dts: qcom: sm6125: Sort spmi_bus node numerically by reg
dt-bindings: clock: qcom,dispcc-sm6125: Remove unused GCC_DISP_AHB_CLK
On 2023-06-23 13:34:06, Abhinav Kumar wrote:
>
>
> On 6/23/2023 1:14 PM, Marijn Suijten wrote:
> > On 2023-06-23 10:29:51, Abhinav Kumar wrote:
> >
> >> The concept is quite simple
> >>
> >> one pixel per clock for uncompresssed without widebub
On 2023-06-17 03:48:33, Dmitry Baryshkov wrote:
> On 17/06/2023 01:12, Marijn Suijten wrote:
> > On 2023-06-16 13:03:15, Dmitry Baryshkov wrote:
> >> To simplify making changes to the hardware block definitions, expand
> >> corresponding macros. This way making all t
On 2023-06-23 14:37:12, Dmitry Baryshkov wrote:
> > In fact I asked to make it 0xf00 + 0x10 or 0xf80 + 0x10 to also cover
> > the CTL registers, but that change didn't make it through. 0x29c is an
> > arbitrary number that I have no clue what it was based on.
>
> This should have been NAKed. or
On 2023-06-23 12:36:06, Abhinav Kumar wrote:
>
>
> On 6/22/2023 11:57 PM, Marijn Suijten wrote:
> > On 2023-06-23 08:54:39, Marijn Suijten wrote:
> >> On 2023-06-22 22:47:04, Abhinav Kumar wrote:
> >>> On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
> >&g
On 2023-06-23 14:32:55, Neil Armstrong wrote:
> Document the optional displayport controller subnode of the SM8550 MDSS.
>
> Acked-by: Rob Herring
> Signed-off-by: Neil Armstrong
Reviewed-by: Marijn Suijten
> ---
> .../devicetree/bindings/display/msm/qcom,sm8550-mds
On 2023-06-23 14:32:54, Neil Armstrong wrote:
> Document the optional displayport controller subnode of the SM8450 MDSS.
>
> Acked-by: Rob Herring
> Signed-off-by: Neil Armstrong
Reviewed-by: Marijn Suijten
> ---
> .../devicetree/bindings/display/msm/qcom,sm8450-mds
On 2023-06-23 14:32:53, Neil Armstrong wrote:
> Document the optional displayport controller subnode of the SM8350 MDSS.
>
> Acked-by: Rob Herring
> Signed-off-by: Neil Armstrong
Reviewed-by: Marijn Suijten
> ---
> Documentation/devicetree/bindings/display/msm/qcom,sm
On 2023-06-23 23:10:56, Dmitry Baryshkov wrote:
> >> There is no confusion between what was said earlier and now.
> >>
> >> This line is calculating the number of pclks needed to transmit one line
> >> of the compressed data:
> >>
> >> hdisplay =
On 2023-06-23 10:29:51, Abhinav Kumar wrote:
> The concept is quite simple
>
> one pixel per clock for uncompresssed without widebubus
>
> 2 pixels per clock for uncompressed with widebus (only enabled for DP
> not DSI)
>
> 3 bytes worth of data for compressed without widebus
>
> 6 bytes
On 2023-06-23 12:54:17, Abhinav Kumar wrote:
>
>
> On 6/23/2023 12:26 AM, Marijn Suijten wrote:
> > On 2023-06-22 17:32:17, Abhinav Kumar wrote:
> >>
> >>
> >> On 6/22/2023 5:17 PM, Dmitry Baryshkov wrote:
> >>> On 23/06/2023 03:14, Abhinav
On 2023-06-21 11:26:25, Neil Armstrong wrote:
> Document the optional document displayport controller subnode
document the optional *document*? Same in the other patches IIRC.
- Marijn
> of the SM8350 MDSS.
>
> Signed-off-by: Neil Armstrong
> ---
>
On 2023-06-22 17:32:17, Abhinav Kumar wrote:
>
>
> On 6/22/2023 5:17 PM, Dmitry Baryshkov wrote:
> > On 23/06/2023 03:14, Abhinav Kumar wrote:
> >>
> >>
> >> On 6/19/2023 2:06 PM, Dmitry Baryshkov wrote:
> >>> Provide actual documentation for the pclk and hdisplay calculations in
> >>> the case
On 2023-06-22 17:01:34, Abhinav Kumar wrote:
> > More interesting would be a link to the Mesa MR upstreaming this
> > bitfield to dsi.xml [2] (which I have not found on my own yet).
> >
> > [2]:
> > https://gitlab.freedesktop.org/mesa/mesa/-/blame/main/src/freedreno/registers/dsi/dsi.xml
> >
>
It is nice if cover letters also include the subsystem:
drm/msm: Add support to print DPU sub-block registers
On 2023-06-22 16:48:52, Ryan McCann wrote:
> The purpose of this patch series is to add support to print the registers
> of sub blocks in the dpu hardware catalog and fix the order in
.
>
> Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant
> chipsets")
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
On 2023-06-22 16:04:30, Abhinav Kumar wrote:
> >> Is widebus applicable only to the CMD mode, or video mode can employ it
> >> too?
> >
> > The patch description states that it was not tested on video-mode yet,
> > so I assume it will. But this should also be highlighted with a comment
> >
On 2023-06-23 08:54:39, Marijn Suijten wrote:
> On 2023-06-22 22:47:04, Abhinav Kumar wrote:
> > On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
> > > All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
> > > This includes the common block itself, e
On 2023-06-22 22:47:04, Abhinav Kumar wrote:
> On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
> > All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
> > This includes the common block itself, enc subblocks and some empty
> > space around. Change that to pass 0x4 instead, the
Hi!
On 2023-01-18 17:16:21, Bryan O'Donoghue wrote:
> Each compatible has a different set of clocks which are associated with it.
> Add in the list of clocks for each compatible.
So if each set of compatibles have their own unique set of clocks, is
there a reason to have so many duplicate then:
On 2023-06-21 09:18:16, Kuogee Hsieh wrote:
> moving retrieving struct drm_dsc_cofnig from setup_display to
> atomic_enable() and delete struct drm_dsc_config from
> struct msm_display_info.
Abhinav suggested to reword this for clarity in v3, but none of that
seems to have made it through?
-
On 2023-06-20 17:27:46, Dmitry Baryshkov wrote:
> On 20/06/2023 15:05, Marijn Suijten wrote:
> > On 2023-06-20 00:06:47, Dmitry Baryshkov wrote:
> >> Provide actual documentation for the pclk and hdisplay calculations in
> >> the case of DSC compression being used.
>
On 2023-06-21 19:36:37, Dmitry Baryshkov wrote:
> On 21/06/2023 18:17, Marijn Suijten wrote:
> > On 2023-06-20 14:38:34, Jessica Zhang wrote:
> >
> >>>>>>> + if (phys_enc->hw_intf->ops.enable_widebus)
> >>>>>>
On 2023-06-20 14:38:34, Jessica Zhang wrote:
> > + if (phys_enc->hw_intf->ops.enable_widebus)
> > + phys_enc->hw_intf->ops.enable_widebus(phys_enc->hw_intf);
>
> No. Please provide a single function which takes necessary
> configuration, including compression and
On 2023-06-20 00:06:47, Dmitry Baryshkov wrote:
> Provide actual documentation for the pclk and hdisplay calculations in
> the case of DSC compression being used.
>
> Signed-off-by: Dmitry Baryshkov
> ---
>
> Changes since v1:
> - Converted dsi_adjust_pclk_for_compression() into kerneldoc
On 2023-06-19 23:57:22, Dmitry Baryshkov wrote:
> On 16/06/2023 15:25, Marijn Suijten wrote:
> > On 2023-06-16 12:41:52, Dmitry Baryshkov wrote:
> >> Provide actual documentation for the pclk and hdisplay calculations in
> >> the case of DSC compression being used.
>
e various PP_BLK_* macros
> drm/msm/dpu: inline WB_BLK macros
> drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
Not sure if I'm ready to manually review all the inline patches before
the weekend, so for now this should do:
Tested-by: Marijn Suijten
(On SM8350 and SDM845 for now)
Th
On 2023-06-16 13:03:17, Dmitry Baryshkov wrote:
> The INTF_SDM845_MASK features mask is zero. Drop it completely.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4
> drivers/gpu/drm/msm
On 2023-06-16 13:03:16, Dmitry Baryshkov wrote:
> The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 3 ---
> drivers/gpu
On 2023-06-16 13:03:06, Dmitry Baryshkov wrote:
> Drop useless zero assignments to the dpu_ctl_cfg::features field.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 3 ---
> drivers/gpu/drm/msm
On 2023-06-16 13:03:11, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Signed-off-by: Dmitry Baryshkov
> ---
>
On 2023-06-16 13:03:05, Dmitry Baryshkov wrote:
> Drop useless zero assignments to the dpu_mdp_cfg::features field.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 -
> drivers/gpu/drm/msm
On 2023-06-16 13:03:04, Dmitry Baryshkov wrote:
> Use more standard initialisation for .clk_ctrls definitions. Define a
> single .clk_ctrls field and use array init inside.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> .../msm/disp/dpu1/catalog
On 2023-06-16 13:03:03, Dmitry Baryshkov wrote:
> Since there is always just a single MDP_TOP instance, drop the enum
> dpu_mdp and corresponding index value.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_
On 2023-06-17 00:41:40, Marijn Suijten wrote:
> > - cfg = _top_offset(idx, m, addr, >hw);
> > - if (IS_ERR_OR_NULL(cfg)) {
> > - kfree(mdp);
> > - return ERR_PTR(-EINVAL);
> > - }
> > + mdp->hw.blk_addr = addr + m->mdp->b
On 2023-06-16 13:03:02, Dmitry Baryshkov wrote:
> There is always a single MDP TOP block. Drop the mdp_count field and
> stop declaring dpu_mdp_cfg instances as arrays.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 ++---
>
hkov
Reviewed-by: Marijn Suijten
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 46 +++---
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 46 +++---
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 63 +--
> .../msm/disp/dpu1/ca
On 2023-06-16 13:03:15, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Signed-off-by: Dmitry Baryshkov
Looks good but I am not sure how
On 2023-06-16 13:03:00, Dmitry Baryshkov wrote:
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 8da424eaee6a..8fa9d83a539d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++
On 2023-06-16 14:06:47, Abhinav Kumar wrote:
> On 6/14/2023 3:49 PM, Marijn Suijten wrote:
> > On 2023-06-14 14:23:38, Marijn Suijten wrote:
> >
> >> Tested this on SM8350 which actually has DSI 2.5, and it is also
> >> corrupted with this series so so
On 2023-06-16 14:13:22, Abhinav Kumar wrote:
> > As I've asked many times before, we should inline these masks (not just
> > the macros) (disclaimer: haven't reviewed if Dmitry's series actually
> > does so!).
> >
>
> Yes it does inline it. I am halfway through that rework got stuck in one
>
On 2023-06-16 14:18:39, Abhinav Kumar wrote:
>
>
> On 6/14/2023 12:56 AM, Dmitry Baryshkov wrote:
> > On 14/06/2023 04:57, Jessica Zhang wrote:
> >> Add a DPU INTF op to set the DATABUS_WIDEN register to enable the
> >> databus-widen mode datapath.
> >>
> >> Signed-off-by: Jessica Zhang
> >>
On 2023-06-16 12:49:29, Dmitry Baryshkov wrote:
> On 16/06/2023 01:26, Marijn Suijten wrote:
> > On 2023-06-13 03:09:42, Dmitry Baryshkov wrote:
> >> sm6115 and qcm2290 do not have INTF_0. Drop corresponding interface
> >> definitions.
> >
> > As Abhinav
On 2023-06-16 12:41:52, Dmitry Baryshkov wrote:
> Provide actual documentation for the pclk and hdisplay calculations in
> the case of DSC compression being used.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 35 --
> 1 file
and
maybe another error code is more fitting?
> + if (j < 0 || j < i)
> continue;
>
> - if (!_dpu_rm_check_lm_peer(rm, i, j)) {
> - DPU_DEBUG("lm %d not peer of lm %d\n", LM_
On 2023-06-15 14:31:22, Dmitry Baryshkov wrote:
>
> On Tue, 13 Jun 2023 03:09:39 +0300, Dmitry Baryshkov wrote:
> > Having a macro with 10 arguments doesn't seem like a good idea. It makes
> > it inherently harder to compare the actual structure values. Also this
> > leads to adding macros
re missing from this series.
For the rest:
Reviewed-by: Marijn Suijten
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++--
> driver
On 2023-06-13 03:09:43, Dmitry Baryshkov wrote:
> Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration.
>
> Signed-off-by: Dmitry Baryshkov
Nice, that'll be cleaner.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/msm_drv.h | 8 +++-
> 1 file cha
upts.c and
dpu_hw_intf.c entirely! Is that your plan?
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> drivers/gpu/d
, and that patch wasn't even introducing the register writes -
this only happened in commit 9ffd0e8569937 ("drm/msm/dpu: setup merge
modes in merge_3d block").
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
> 1 file changed, 1 insertion(
out looking at hardware support at all.
Reviewed-by: Marijn Suijten
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 ++--
> .../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 16
> 2 files changed, 18 insertions(+), 6 deletions(-)
>
> d
On 2023-06-13 03:09:39, Dmitry Baryshkov wrote:
> Having a macro with 10 arguments doesn't seem like a good idea. It makes
> it inherently harder to compare the actual structure values. Also this
> leads to adding macros covering varieties of the block.
>
> As it was previously discussed, inline
On 2023-06-13 03:09:56, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Signed-off-by: Dmitry Baryshkov
> ---
>
On 2023-06-15 14:31:26, Dmitry Baryshkov wrote:
>
> On Fri, 09 Jun 2023 15:57:12 -0700, Jessica Zhang wrote:
> > This is a series of changes for DSI to enable command mode support
> > for DSC v1.2.
> >
> > This includes:
> >
> > 1) Rounding up `hdisplay / 3` in dsc_timing_setup()
> > 2)
sense to split this out instead of faking a
_configure(false) with a return right at the top and "bogus" pointers.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
&
On 2023-06-15 01:44:01, Dmitry Baryshkov wrote:
> Several source clocks are not used anymore, so stop handling them.
>
> Signed-off-by: Dmitry Baryshkov
Indeed, we were not using these parent clocks for anything.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/
On 2023-06-14 14:23:38, Marijn Suijten wrote:
> Tested this on SM8350 which actually has DSI 2.5, and it is also
> corrupted with this series so something else on this series might be
> broken.
Never mind, this was a bad conflict-resolve. Jessica's original
BURST_MODE patch wa
On 2023-06-14 13:39:57, Abhinav Kumar wrote:
> On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
> > On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
> >> On 6/14/2023 5:23 AM, Marijn Suijten wrote:
> >>> On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
> >>>&
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
> On 14/06/2023 14:42, Marijn Suijten wrote:
> > On 2023-06-13 18:57:11, Jessica Zhang wrote:
> >> DPU 5.x+ supports a databus widen mode that allows more data to be sent
> >> per pclk. Enable this feature fl
On 2023-06-13 18:57:11, Jessica Zhang wrote:
> DPU 5.x+ supports a databus widen mode that allows more data to be sent
> per pclk. Enable this feature flag on all relevant chipsets.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
>
On 2023-06-14 12:39:13, Marijn Suijten wrote:
> > > > - /* add register dump support */
> > > > - dpu_debugfs_create_regset32("src_blk", 0400,
> > > > - debugfs_root,
> > > &
On 2023-05-21 21:16:39, Marijn Suijten wrote:
> On 2023-05-21 20:12:00, Marijn Suijten wrote:
> > On 2023-05-21 20:21:46, Dmitry Baryshkov wrote:
> > > Drop SSPP-specifig debugfs register dumps in favour of using
> > > debugfs/dri/0/kms or devcoredump.
> > >
&
On 2023-06-13 18:57:10, Jessica Zhang wrote:
> DPU 5.x+ and DSI 6G 2.5.x+ support a databus-widen mode that allows for
> more compressed data to be transferred per pclk.
>
> This series adds support for enabling this feature for both DPU and DSI
> by doing the following:
>
> 1. Add a
On 2023-06-14 10:49:31, Dmitry Baryshkov wrote:
> On 14/06/2023 04:57, Jessica Zhang wrote:
> > DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> > 48 bits of compressed data per pclk instead of 24.
> >
> > For all chipsets that support this mode, enable it whenever DSC is
>
On 2023-06-13 18:57:13, Jessica Zhang wrote:
> DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> 48 bits of compressed data per pclk instead of 24.
>
> For all chipsets that support this mode, enable it whenever DSC is
> enabled as recommend by the hardware programming
On 2023-06-12 16:37:36, Jessica Zhang wrote:
> During a frame transfer in command mode, there could be frequent
> LP11 <-> HS transitions when multiple DCS commands are sent mid-frame or
> if the DSI controller is running on slow clock and is throttled. To
> minimize frame latency due to these
phys_enc->hw_pp->idx);
> +
> + if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
> + phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
It was probably not necessary to drop this after adding dsc!=0:
Reviewed-by: Marijn Suijten
&g
tended: I am able to set a color transformation of choice with a
quickly-pieced-together DRM utility:
https://github.com/MarijnS95/drm-tools
Reviewed-by: Marijn Suijten
> ---
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 21 +++
> 1 file changed, 17 inser
ock in dpu
> driver")
> Reported-by: Yongqin Liu
> Signed-off-by: Dmitry Baryshkov
Yep, this indeed makes the CTM blob property disappear from the CRTC
resource:
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 -
> 1 file changed, 4 i
On 2023-06-12 21:30:05, Dmitry Baryshkov wrote:
> On 12/06/2023 12:21, Marijn Suijten wrote:
> > On 2023-06-12 11:15:53, Marijn Suijten wrote:
> >> On 2023-06-12 06:16:16, Dmitry Baryshkov wrote:
> >>> CCF can try enabling VCO before the rate has been programmed. This
Title typo that I missed: implemenation -> implemen*T*ation :)
On 2023-06-12 11:14:41, Marijn Suijten wrote:
On 2023-06-12 10:26:39, Abhinav Kumar wrote:
>
>
> On 6/11/2023 3:03 PM, Marijn Suijten wrote:
> > On 2023-06-09 15:57:18, Jessica Zhang wrote:
> >> Add documentation comments explaining the pclk_rate and hdisplay math
> >> related to DSC.
>
On 2023-06-12 11:15:53, Marijn Suijten wrote:
> On 2023-06-12 06:16:16, Dmitry Baryshkov wrote:
> > CCF can try enabling VCO before the rate has been programmed. This can
> > cause clock lockups and/or other boot issues. Program the VCO to the
> > minimal PLL rate if
On 2023-06-12 06:16:16, Dmitry Baryshkov wrote:
> CCF can try enabling VCO before the rate has been programmed. This can
> cause clock lockups and/or other boot issues. Program the VCO to the
> minimal PLL rate if the read rate is 0 Hz.
>
> Reported-by: Degdag Mohamed
> Fixes: 1ef7c99d145c
itry Baryshkov
Thanks, this solves the following warning:
msm_dpu ae01000.display-controller:
drm_WARN_ON_ONCE(!helper->funcs->fb_dirty)
WARNING: CPU: 0 PID: 9 at drivers/gpu/drm/drm_fb_helper.c:381
drm_fb_helper_damage_work+0x1c0/0x20c
Reviewed-by: Marijn Suijten
Note t
On 2023-06-09 15:57:18, Jessica Zhang wrote:
> Add documentation comments explaining the pclk_rate and hdisplay math
> related to DSC.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
On 2023-06-08 17:56:47, Jessica Zhang wrote:
> > As discussed before we realized that this change is more-or-less a hack,
> > since downstream calculates pclk quite differently - at least for
> > command-mode panels. Do you still intend to land this patch this way,
> > or go the proper route by
On 2023-06-09 19:58:00, Dmitry Baryshkov wrote:
> On 08/06/2023 23:36, Marijn Suijten wrote:
> > Same title suggestion as earlier: s/adjust/reduce
> >
> > On 2023-05-22 18:08:56, Jessica Zhang wrote:
> >> Adjust the pclk rate to divide hdisplay by the compression
On 2023-06-08 18:09:57, Abhinav Kumar wrote:
> >> As discussed before we realized that this change is more-or-less a hack,
> >> since downstream calculates pclk quite differently - at least for
> >> command-mode panels. Do you still intend to land this patch this way,
> >> or go the proper route
Same title suggestion as earlier: s/adjust/reduce
On 2023-05-22 18:08:56, Jessica Zhang wrote:
> Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
> is enabled.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 21 ++---
> 1
et_rate().
>
> Change the "vsync_hz" type to unsigned long as well and change the
> error checking to check for zero instead of negatives. This change
> does not affect runtime at all. It's just a clean up.
>
> Signed-off-by: Dan Carpenter
Suggested-by: Marijn Suijt
Not something you have to (or can) address Kuogee, but I'll keep sending
my submissions with the changelog *below* the cut (or in the cover
letter) until someone complains.
>
> Signed-off-by: Abhinav Kumar
Reviewed-by: Marijn Suijten
- Marijn
> ---
> drivers/gpu/drm/msm/di
conflicts at dpu_5_1_sc8180x.h
>
> Changes in v16
> -- fix cherry-pick error by deleting both redundant .dsc and .dsc_count
>assignment from dpu_5_1_sc8180x.h
>
> Signed-off-by: Abhinav Kumar
> Reviewed-by: Dmitry Baryshkov
> Reviewed-by: Marijn Suijten
> ---
> drivers/gp
it title
>
> Changes in v15:
> -- fix merge conflicts at dpu_5_1_sc8180x.h
>
> Signed-off-by: Abhinav Kumar
> Reviewed-by: Dmitry Baryshkov
> Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++
> drivers/gpu/drm
ing and drop the flag completely.
>
> Suggested-by: Marijn Suijten
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
> drivers/
of unbinding and drop the flag completely.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
>
> Changes since v1:
> - Dropped != PINGPONG_NONE (Marijn)
>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
> drivers/gpu/dr
On 2023-05-30 23:14:19, Dmitry Baryshkov wrote:
> On Tue, 30 May 2023 at 20:37, Abhinav Kumar wrote:
> >
> >
> >
> > On 5/29/2023 2:36 PM, Marijn Suijten wrote:
> > > On 2023-05-24 12:18:09, Abhinav Kumar wrote:
> > >>
> > >>
> >
On 2023-05-26 14:51:59, Dan Carpenter wrote:
> Static analysis tools complain about the -EINVAL error code being
> stored in an unsigned variable. Let's change this to match
> the clk_get_rate() function which is type unsigned long and returns
> zero on error.
>
> Fixes: 25fdd5933e4c ("drm/msm:
of changes in v9
> -- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN
> -- replace drm_dsc_calculate_flatness_det_thresh() with
> drm_dsc_flatness_det_thresh()
>
> Signed-off-by: Kuogee Hsieh
> Reviewed-by: Dmitry Baryshkov
Since I have given this code adequate comments, and have finally
successful
On 2023-06-01 16:56:53, Marijn Suijten wrote:
> > +static const struct dpu_intf_cfg sm6375_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x0, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
> > + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24,
>
On 2023-05-23 09:46:19, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
Nit: The SM6350 commit doesn't use the word "basic" here: what does it
mean? Is this addition not complete (because it seems so)?
> Reviewed-by: Dmitry Baryshkov
>
On 2023-05-30 14:11:06, Dmitry Baryshkov wrote:
> On Tue, 30 May 2023 at 11:27, Marijn Suijten
> wrote:
> >
> > On 2023-05-30 01:39:10, Dmitry Baryshkov wrote:
> > > On 30/05/2023 01:37, Marijn Suijten wrote:
> > > > On 2023-05-30 01:18:40, Dmitry Baryshkov
On 2023-05-30 10:54:17, Abhinav Kumar wrote:
> > On 30/05/2023 00:07, Marijn Suijten wrote:
> >> On 2023-05-22 15:58:56, Dmitry Baryshkov wrote:
> >>> On Mon, 22 May 2023 at 12:04, Neil Armstrong
> >>> wrote:
> >>>>
> >>>> On
On 2023-05-30 01:13:12, Dmitry Baryshkov wrote:
> On Tue, 30 May 2023 at 00:46, Marijn Suijten
> wrote:
> >
> > On 2023-05-26 12:09:45, Dmitry Baryshkov wrote:
> > > Currently the driver passes the PINGPONG index to
> > > dpu_hw_intf_ops::bind_pingpong_blk(
On 2023-05-30 09:24:24, Neil Armstrong wrote:
> Hi Marijn, Dmitry, Caleb, Jessica,
>
> On 29/05/2023 23:11, Marijn Suijten wrote:
> > On 2023-05-22 04:16:20, Dmitry Baryshkov wrote:
> >
> >>> + if (ctx->dsi->dsc) {
> >>
> >> dsi->dsc i
On 2023-05-30 01:39:10, Dmitry Baryshkov wrote:
> On 30/05/2023 01:37, Marijn Suijten wrote:
> > On 2023-05-30 01:18:40, Dmitry Baryshkov wrote:
> >
> >>>>>>> +ret = mipi_dsi_dcs_set_display_on(dsi);
> >>>>>>> +if (ret < 0
On 2023-05-30 01:18:40, Dmitry Baryshkov wrote:
> > +ret = mipi_dsi_dcs_set_display_on(dsi);
> > +if (ret < 0) {
> > +dev_err(dev, "Failed to turn display on: %d\n", ret);
> > +return ret;
> > +}
>
> My usual question: should the
On 2023-05-30 01:20:17, Dmitry Baryshkov wrote:
> On 29/05/2023 23:58, Marijn Suijten wrote:
> > On 2023-05-23 01:56:46, Dmitry Baryshkov wrote:
> >> On Tue, 23 May 2023 at 01:32, Marijn Suijten
> >> wrote:
> >>>
> >>> On 2023-05-22 04:19:45,
On 2023-05-30 01:22:54, Dmitry Baryshkov wrote:
> On 30/05/2023 00:29, Konrad Dybcio wrote:
> >
> >
> > On 29.05.2023 23:21, Marijn Suijten wrote:
> >> On 2023-05-22 11:08:12, Neil Armstrong wrote:
> >>> On 22/05/2023 03:23, Dmitry Baryshkov wrote:
On 2023-05-26 12:09:45, Dmitry Baryshkov wrote:
> Currently the driver passes the PINGPONG index to
> dpu_hw_intf_ops::bind_pingpong_blk() callback and uses separate boolean
> flag to tell whether INTF should be bound or unbound. Simplify this by
> passing PINGPONG_NONE in case of unbinding and
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