0200, Andi Shyti wrote:
> > > > Hi Mauro,
> > > >
> > > > On Thu, Aug 04, 2022 at 09:37:22AM +0200, Mauro Carvalho Chehab
> > > > wrote:
> > > > > WRITE_ONCE() should happen at the original var, not on a local
> > > > > copy of it.
>
On Fri, 5 Aug 2022 10:39:44 -0400
Rodrigo Vivi wrote:
> On Fri, Aug 05, 2022 at 10:46:57AM +0200, Mauro Carvalho Chehab wrote:
> > Hi Rodrigo,
> >
> > On Thu, 4 Aug 2022 13:33:06 -0400
> > Rodrigo Vivi wrote:
> >
> > > Hi Dave and Daniel,
> >
On Fri, 5 Aug 2022 10:24:25 +0100
Tvrtko Ursulin wrote:
> On 05/08/2022 10:08, Andi Shyti wrote:
> > Hi Randy,
> >
> >>> +/**
> >>> + * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
> >>> + * @gt: GT structure
> >>
> >> In multiple places (here and below) it would be nice to
Hi Rodrigo,
On Thu, 4 Aug 2022 13:33:06 -0400
Rodrigo Vivi wrote:
> Hi Dave and Daniel,
>
> Here goes drm-intel-next-fixes-2022-08-04:
>
> - disable pci resize on 32-bit systems (Nirmoy)
> - don't leak the ccs state (Matt)
> - TLB invalidation fixes (Chris)
>
> Thanks,
> Rodrigo.
>
> The fol
/PDF;
- Remove mention for GuC, as this depends on a series that will be sent later.
Chris Wilson (1):
drm/i915/gt: Move TLB invalidation to its own file
Mauro Carvalho Chehab (2):
drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()
drm/i915/gt: document TLB cache invalidation
Add a description for the TLB cache invalidation algorithm and for
the related kAPI functions.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/3] at:
https://lore.kernel.org/all/cover
WRITE_ONCE() should happen at the original var, not on a local
copy of it.
Fixes: 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH
Wilson
Reviewed-by: Niranjana Vishwanathapura
Reviewed-by: Andi Shyti
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/3] at:
https://lore.kernel.org/all/cover.1659598090.git.mche
On Tue, 2 Aug 2022 15:30:44 -0700
Niranjana Vishwanathapura wrote:
> On Fri, Jul 29, 2022 at 09:03:55AM +0200, Mauro Carvalho Chehab wrote:
> >Add a description for the TLB cache invalidation algorithm and for
> >the related kAPI functions.
> >
> >Signed-of
On Thu, 14 Jul 2022 16:06:28 +0200
Michal Wajdeczko wrote:
> On 14.07.2022 14:06, Mauro Carvalho Chehab wrote:
> > From: Prathap Kumar Valsan
> >
> > Add routines to interface with GuC firmware for TLB invalidation.
> >
> > Signed-off-by: Prathap Kumar Va
From: Chris Wilson
Prepare for supporting more TLB invalidation scenarios by moving
the current MMIO invalidation to its own file.
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
text form and after
its conversion to HTML/PDF;
- Remove mention for GuC, as this depends on a series that will be sent later.
Chris Wilson (1):
drm/i915/gt: Move TLB invalidation to its own file
Mauro Carvalho Chehab (1):
drm/i915/gt: document TLB cache invalidation functions
Add a description for the TLB cache invalidation algorithm and for
the related kAPI functions.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 0/2] at:
https://lore.kernel.org/all/cover
https://patchwork.freedesktop.org/series/106806/
That should make easier to maintain TLB-related code and have such
functions properly documented.
Regards,
Mauro
>
> Thanks,
> Andi
>
> On Wed, Jul 27, 2022 at 02:29:50PM +0200, Mauro Carvalho Chehab wrote:
> > Doing TLB invalidation
There are more things to be added to TLB invalidation. Before doing that,
move the code to its own file, and add the relevant documentation.
Chris Wilson (1):
drm/i915/gt: Move TLB invalidation to its own file
Mauro Carvalho Chehab (1):
drm/i915/gt: document TLB cache invalidation functions
From: Chris Wilson
Prepare for supporting more TLB invalidation scenarios by moving
the current MMIO invalidation to its own file.
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
Add a description for the TLB cache invalidation algorithm and for
the related kAPI functions.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH 0/2] at:
https://lore.kernel.org/all/cover.1659011328
On Thu, 28 Jul 2022 08:32:32 +0200
Mauro Carvalho Chehab wrote:
> On Wed, 27 Jul 2022 13:56:50 +0100
> Tvrtko Ursulin wrote:
>
> > > Because vma_invalidate_tlb() basically stores a TLB seqno, but the
> > > actual invalidation is deferred to w
On Wed, 27 Jul 2022 13:56:50 +0100
Tvrtko Ursulin wrote:
> > Because vma_invalidate_tlb() basically stores a TLB seqno, but the
> > actual invalidation is deferred to when the pages are unset, at
> > __i915_gem_object_unset_pages().
> >
> > So, what happens is:
> >
> > - on VMA sync mode, the n
ilson (4):
drm/i915/gt: Ignore TLB invalidations on idle engines
drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations
drm/i915/gt: Skip TLB invalidations once wedged
drm/i915/gt: Batch TLB invalidations
Mauro Carvalho Chehab (2):
drm/i915/gt: document with_intel_gt_pm_if_awake()
d
.
Document it.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/6] at:
https://lore.kernel.org/all/cover.1658924372.git.mche...@kernel.org/
drivers/gpu/drm/i915/i915_vma_resource.c | 4
1 file
]
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing list
: Fei Yang
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Acked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/6] at:
https://lore.kernel.org/all/cover.165892437
Add a kernel-doc markup to document this new macro.
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/6] at:
https://lore.kernel.org/all/cover.1658924372.git.mche
ned-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/6] at:
https://lore.kernel.org/all/cover.1658924372.git.mche...@kernel.org/
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 10 ++
drivers/gpu/d
cked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v3 0/6] at:
https://lore.kernel.org/all/cover.1658924372.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
On Wed, 20 Jul 2022 11:49:59 +0100
Tvrtko Ursulin wrote:
> On 20/07/2022 08:13, Mauro Carvalho Chehab wrote:
> > On Mon, 18 Jul 2022 14:52:05 +0100
> > Tvrtko Ursulin wrote:
> >
> >>
> >> On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:
> >>
On Mon, 18 Jul 2022 14:52:05 +0100
Tvrtko Ursulin wrote:
>
> On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:
> > From: Chris Wilson
> >
> > Invalidate TLB in patch, in order to reduce performance regressions.
>
> "in batches"?
Yeah. Will fix it.
On Mon, 18 Jul 2022 14:45:22 +0100
Tvrtko Ursulin wrote:
> On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:
> > From: Chris Wilson
> >
> > Skip all further TLB invalidations once the device is wedged and
> > had been reset, as, on such cases, it can no longer proc
On Mon, 18 Jul 2022 14:39:17 +0100
Tvrtko Ursulin wrote:
> On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:
> > From: Chris Wilson
> >
> > Don't flush TLBs when the buffer is only used in the GGTT under full
> > control of the kernel, as there's no ri
On Mon, 18 Jul 2022 14:16:10 +0100
Tvrtko Ursulin wrote:
> On 14/07/2022 13:06, Mauro Carvalho Chehab wrote:
> > From: Chris Wilson
> >
> > Check if the device is powered down prior to any engine activity,
> > as, on such cases, all the TLBs were already invalida
On Fri, 15 Jul 2022 15:16:05 -0700
Joe Perches wrote:
> On Fri, 2022-07-15 at 17:35 -0400, Rodrigo Vivi wrote:
> > On Wed, Jul 13, 2022 at 09:12:12AM +0100, Mauro Carvalho Chehab wrote:
> > > This file is licensed with MIT license. Change its license text
c: Andrzej Hajda
Cc: Mika Kuoppala
Signed-off-by: Mauro Carvalho Chehab
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 44 +--
drivers/gpu/drm/i915/i915_utils.h | 10 +
2 files changed, 40 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/d
hing is ok.
Probably the issue was due to some badly solved merge conflict.
Thank you!
Mauro
>
> Alex
>
>
> >
> > I will double check drm-tip once more.
> >
> > Regards,
> > Christian.
> >
> > Am 14.07.22 um 14:54 schrieb Mauro Carval
On Thu, 14 Jul 2022 15:08:48 +0200
Christian König wrote:
> Hi Mauro,
>
> well the last time I checked drm-tip was clean.
>
> The revert is necessary because we had some problems with the commit
> which we couldn't fix in the 5.19 cycle.
I see. I don't have any issues with the patch itself, p
On Fri, 8 Jul 2022 03:21:24 -0700
Arunpravin Paneer Selvam wrote:
> This reverts the following commits:
> commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the C
> file")
> commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in
> amdgpu_vram_mgr_new")
> commit c9cad937c
From: Chris Wilson
Prepare for supporting more TLB invalidation scenarios by moving
the current MMIO invalidation to its own file.
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
Add a description for the kAPI functions inside intel_tlb.c.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org
can only do so when
the connection to the GuC is awake.
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Cc: Andi Shyti
Cc: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
From: Prathap Kumar Valsan
Add support for selective TLB invalidation, which is a platform
feature supported on XeHP.
Signed-off-by: Prathap Kumar Valsan
Cc: Niranjana Vishwanathapura
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing
Add documentation to the TLB field inside
struct drm_i915_gem_object.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche
Add a kernel-doc markup to document this new macro.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org/
drivers/gpu
ff-by: Prathap Kumar Valsan
Cc: Niranjana Vishwanathapura
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche...@kerne
From: Prathap Kumar Valsan
Add routines to interface with GuC firmware for TLB invalidation.
Signed-off-by: Prathap Kumar Valsan
Cc: Bruce Chang
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: Chris Wilson
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of
Add documentation for the 3 new members of struct intel_guc
that are used to handle TLB cache invalidation logic.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https
drm/i915/gt: Batch TLB invalidations
drm/i915/gt: Move TLB invalidation to its own file
drm/i915: Invalidate the TLBs on each GT
Mauro Carvalho Chehab (8):
drm/i915/gt: document with_intel_gt_pm_if_awake()
drm/i915/gt: describe the new tlb parameter at i915_vma_resource
drm/i915/guc: use k
erformance regression introduced by TLB
invalidate logic.
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Cc: Andi Shyti
Acked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
To
]
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing list
From: Chris Wilson
With multi-GT devices, the object may have been bound on each GT.
Invalidate the TLBs across all GT before releasing the pages
back to the system.
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of
i Yang
Cc: Andi Shyti
Acked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org/
drivers/gpu/d
Yang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++
drivers
From: Prathap Kumar Valsan
Add routines to interface with GuC firmware for selective TLB invalidation
supported on XeHP.
Signed-off-by: Prathap Kumar Valsan
Cc: Matthew Brost
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C
Add a description for intel_guc_tlb_invalidation_type enum.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org
Transform the comments for intel_guc_tlb_inval_mode into a
kernel-doc markup.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche
Add documentation for the kAPI functions that do TLB cache
invalidation via GuC.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche
From: Piotr Piórkowski
Add a new way to invalidate TLB via GuC using actions 0x7002
(TLB_INVALIDATION_ALL).
Those actions will be used on upcoming patches.
Signed-off-by: Piotr Piórkowski
Cc: Michal Wajdeczko
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number
ed by TLB
invalidate logic.
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Cc: Andi Shyti
Acked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a
.
Document it.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/21] at:
https://lore.kernel.org/all/cover.1657800199.git.mche...@kernel.org/
drivers/gpu/drm/i915/i915_vma_resource.c | 4
1
Add safe_conversion_gem_bug_on() macro and remove temporal
> SAFE_CONVERSION() macro.
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: Chris Wilson
> Cc: Matthew Auld
> Cc: Thomas Hellström
> Reviewed-by: Nirmoy Das
LGTM.
Reviewed-by: Mauro Carvalho Chehab
> ---
> dr
gt; Signed-off-by: Gwan-gyeong Mun
> Cc: Tvrtko Ursulin
> Cc: Matthew Auld
> Cc: Thomas Hellström
> Reviewed-by: Nirmoy Das
LGTM, so:
> Reviewed-by: Mauro Carvalho Chehab
Yet, it would make sense to have some patch adding kernel-doc
markups to the kAPI functions declared at the
dify overflows_type() macro to consider signed data types (Mauro)
> Fix the problem that safe_conversion() macro always returns true
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: Thomas Hellström
> Cc: Matthew Auld
> Cc: Nirmoy Das
> Cc: Jani Nikula
LGTM.
Reviewed-by: Ma
On Wed, 13 Jul 2022 18:07:44 -0400
Rodrigo Vivi wrote:
> On Wed, Jul 13, 2022 at 09:11:54AM +0100, Mauro Carvalho Chehab wrote:
> > There are several trivial warnings there, due to trivial things:
> > - lack of function name at the kerneldoc markup;
> > - undocumente
On Wed, 13 Jul 2022 18:05:06 -0400
Rodrigo Vivi wrote:
> On Wed, Jul 13, 2022 at 09:11:53AM +0100, Mauro Carvalho Chehab wrote:
> > There are a couple of issues at i915 display kernel-doc markups:
> >
> > drivers/gpu/drm/i915/display/intel_display_debugfs.c:2238: w
On Wed, 13 Jul 2022 18:00:59 -0400
Rodrigo Vivi wrote:
> On Wed, Jul 13, 2022 at 05:54:44PM -0400, Rodrigo Vivi wrote:
> > On Wed, Jul 13, 2022 at 09:11:49AM +0100, Mauro Carvalho Chehab wrote:
> > > From: Jiapeng Chong
> > >
> > > Fix the following W=1 k
Add a description for the kAPI functions inside intel_tlb.c.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/intel_tlb.c | 36 +
1 file changed, 36
From: Chris Wilson
With multi-GT devices, the object may have been bound on each GT.
Invalidate the TLBs across all GT before releasing the pages
back to the system.
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https
]
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.165770392
From: Prathap Kumar Valsan
Add routines to interface with GuC firmware for TLB invalidation.
Signed-off-by: Prathap Kumar Valsan
Cc: Bruce Chang
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: Chris Wilson
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org
Add documentation for the kAPI functions that do TLB cache
invalidation via GuC.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 52 ++
1 file
t TLB invalidations
drm/i915/gt: Only invalidate TLBs exposed to user manipulation
drm/i915/gt: Skip TLB invalidations once wedged
drm/i915/gt: Batch TLB invalidations
drm/i915/gt: Move TLB invalidation to its own file
drm/i915: Invalidate the TLBs on each GT
Mauro Carvalho Chehab (8):
.
Document it.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/i915_vma_resource.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_vma_resource.c
b/drivers/gpu
From: Piotr Piórkowski
Add a new way to invalidate TLB via GuC using actions 0x7002
(TLB_INVALIDATION_ALL).
Those actions will be used on upcoming patches.
Signed-off-by: Piotr Piórkowski
Cc: Michal Wajdeczko
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https
erformance regression introduced by TLB
invalidate logic.
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Cc: Andi Shyti
Acked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
Add a description for intel_guc_tlb_invalidation_type enum.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 12
1 file changed, 12 insertions
Add documentation to the TLB field inside
struct drm_i915_gem_object.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
1 file changed, 1 insertion
Yang
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++
drivers/gpu/drm/i915/gt/intel_tlb.c | 78 -
drivers/gpu/drm/i915/gt
From: Prathap Kumar Valsan
Add routines to interface with GuC firmware for selective TLB invalidation
supported on XeHP.
Signed-off-by: Prathap Kumar Valsan
Cc: Matthew Brost
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926
From: Chris Wilson
Prepare for supporting more TLB invalidation scenarios by moving
the current MMIO invalidation to its own file.
Signed-off-by: Chris Wilson
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche
From: Prathap Kumar Valsan
Add support for selective TLB invalidation, which is a platform
feature supported on XeHP.
Signed-off-by: Prathap Kumar Valsan
Cc: Niranjana Vishwanathapura
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover
ff-by: Prathap Kumar Valsan
Cc: Niranjana Vishwanathapura
Cc: Fei Yang
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c
can only do so when
the connection to the GuC is awake.
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Cc: Andi Shyti
Cc: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
See [P
Add documentation for the 3 new members of struct intel_guc
that are used to handle TLB cache invalidation logic.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 14
ed by TLB
invalidate logic.
Cc: sta...@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Cc: Andi Shyti
Acked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://
Transform the comments for intel_guc_tlb_inval_mode into a
kernel-doc markup.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 11 +++
1 file changed
i Yang
Cc: Andi Shyti
Acked-by: Thomas Hellström
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/intel_gt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/d
Add a kernel-doc markup to document this new macro.
Signed-off-by: Mauro Carvalho Chehab
---
See [PATCH 00/21] at:
https://lore.kernel.org/all/cover.1657703926.git.mche...@kernel.org/
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu
drm/i915/gt/uc/intel_guc_hwconfig.c:113: warning: Function
parameter or member 'gt' not described in 'guc_hwconfig_init'
drivers/gpu/drm/i915/gt/intel_engine_types.h:276: warning: Function
parameter or member 'preempt_hang' not described in 'intel_engine_execlists'
Two new fields were added to __i915_gem_ttm_object_init() without
their corresponding documentation.
Document them.
Fixes: 9b78b5dade2d ("drm/i915: add i915_gem_object_create_region_at()")
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, on
The DOC: tag waits for a one-line short title for the doc
section. Using multiple lines will produce a weird output.
So, add a shorter description for the title, while keeping
the current content below it.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people
gpu/drm/i915/gem/i915_gem_wait.c:130: warning: This comment
starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
Caused by:
- lack of function name at the kernel-doc markup;
- renamed parameters.
Address them.
Signed-of
The intel_gt_pm.h file contains some convenient macros to be used
in GT code in order to get/put runtime PM references and for
checking them.
Add descriptions based on the ones at intel_wakeref.h and
intel_runtime_pm.c.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large
The return codes for i915_gem_wait_ioctl() have identation issues,
and will be displayed on a very confusing way. Use lists to improve
its output.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2
Prevent this Sphinx warning:
Documentation/foo/i915:728: ./drivers/gpu/drm/i915/i915_gem.c:447:
WARNING: Inline emphasis start-string without end-string.
By using @data to identify the data field, as expected by kernel-doc.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid
Both intel_runtime_pm.h and intel_pm.c contains kAPI for
runtime PM. So, add them to the documentation.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/39] at:
https://lore.kernel.org/all
This is a large struct used to describe gem objects. It is
currently partially documented. Finish its documentation, filling
the gaps from git logs.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH
fi; done >aaa
Add them to i915.rst as well.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/39] at:
https://lore.kernel.org/all/cover.1657699522.git.mche...
i915_gem_ttm_pm.c:199: warning: Excess
function parameter 'allow_gpu' description in 'i915_ttm_restore_region'
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/39] at:
https://
for intel_alloc_vgpu_resource(). Prototype was for
intel_vgpu_alloc_resource() instead.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
Acked-by: Zhenyu Wang
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the
-string without end-string.
That's because @foo evaluates into **foo**, and placing anything
after it without spaces cause Sphinx to warn and do the wrong
thing.. So, replace them by a different Sphinx-compatible tag.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large numb
warn and do the wrong
thing.. So, replace them by a different Sphinx-compatible tag.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the cover.
See [PATCH v2 00/39] at:
https://lore.kernel.org/all/cover.1657699522.git
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