combinations, and sent as an RFC to encourage discussion.
Signed-off-by: Zhang Yuhao
Signed-off-by: Mingcong Bai
Tested-by: Mingcong Bai
---
drivers/gpu/drm/amd/amdkfd/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig
b/drivers/gp
From: Mingcong Bai
As this component hooks into userspace API, it should be assumed that it
will play well with non-4KiB/64KiB pages.
Use `PAGE_SIZE' as the final reference for page alignment instead.
Cc: sta...@vger.kernel.org
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver
From: Mingcong Bai
Similar to the preceding patch for GuC (and with the same references),
Intel GPUs expects command buffers to align to 4KiB boundaries.
Current code uses `PAGE_SIZE' as an assumed alignment reference but 4KiB
kernel page sizes is by no means a guarantee. On 16KiB-paged ke
From: Mingcong Bai
The bo/ttm interfaces with kernel memory mapping from dedicated GPU
memory. It is not correct to assume that SZ_4K would suffice for page
alignment as there are a few hardware platforms that commonly uses non-
4KiB pages - for instance, 16KiB is the most commonly used kernel
hat's strange... I have just resent the series.
Best Regards,
Mingcong Bai
From: Mingcong Bai
Per the "Firmware" chapter in "drm/xe Intel GFX Driver", as well as
"Volume 8: Command Stream Programming" in "Intel® Arc™ A-Series Graphics
and Intel Data Center GPU Flex Series Open-Source Programmer's Reference
Manual For the discrete
Shang Yatsen <429839...@qq.com>
Signed-off-by: Shang Yatsen <429839...@qq.com>
Signed-off-by: Mingcong Bai
---
Mingcong Bai (5):
drm/xe/bo: fix alignment with non-4KiB kernel page sizes
drm/xe/guc: use GUC_SIZE (SZ_4K) for alignment
drm/xe/regs: fix RING_CTL_SIZE(size)
From: Mingcong Bai
It appears that the xe_res_cursor also assumes 4KiB alignment.
Current implementation uses `PAGE_SIZE' as an assumed alignment reference,
but 4KiB kernel page sizes is by no means a guarantee. On 16KiB-paged
kernels, this causes driver failures during boot up:
[ 23.2
Shang Yatsen <429839...@qq.com>
Signed-off-by: Shang Yatsen <429839...@qq.com>
Signed-off-by: Mingcong Bai
---
Mingcong Bai (5):
drm/xe/bo: fix alignment with non-4KiB kernel page sizes
drm/xe/guc: use GUC_SIZE (SZ_4K) for alignment
drm/xe/regs: fix RING_CTL_SIZE(size)
From: Mingcong Bai
Per the "Firmware" chapter in "drm/xe Intel GFX Driver", as well as
"Volume 8: Command Stream Programming" in "Intel® Arc™ A-Series Graphics
and Intel Data Center GPU Flex Series Open-Source Programmer's Reference
Manual For the discrete
From: Mingcong Bai
It appears that the xe_res_cursor also assumes 4KiB alignment.
Current implementation uses `PAGE_SIZE' as an assumed alignment reference,
but 4KiB kernel page sizes is by no means a guarantee. On 16KiB-paged
kernels, this causes driver failures during boot up:
[ 23.2
From: Mingcong Bai
Similar to the preceding patch for GuC (and with the same references),
Intel GPUs expects command buffers to align to 4KiB boundaries.
Current code uses `PAGE_SIZE' as an assumed alignment reference but 4KiB
kernel page sizes is by no means a guarantee. On 16KiB-paged ke
From: Mingcong Bai
As this component hooks into userspace API, it should be assumed that it
will play well with non-4KiB/64KiB pages.
Use `PAGE_SIZE' as the final reference for page alignment instead.
Cc: sta...@vger.kernel.org
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver
From: Mingcong Bai
The bo/ttm interfaces with kernel memory mapping from dedicated GPU
memory. It is not correct to assume that SZ_4K would suffice for page
alignment as there are a few hardware platforms that commonly uses non-
4KiB pages - for instance, 16KiB is the most commonly used kernel
Hi Matt,
在 2025/2/26 12:43, Matthew Brost 写道:
On Wed, Feb 26, 2025 at 10:00:22AM +0800, Mingcong Bai via B4 Relay wrote:
From: Mingcong Bai
As this component hooks into userspace API, it should be assumed that it
will play well with non-4K/64K pages.
Use `PAGE_SIZE' as the final refe
Bai via B4 Relay wrote:
From: Mingcong Bai
The bo/ttm interfaces with kernel memory mapping from dedicated GPU
memory. It is not correct to assume that SZ_4K would suffice for page
alignment as there are a few hardware platforms that commonly uses non-4K
pages - for instance, currently, Loongson
在 2025/2/26 12:43, Matthew Brost 写道:
On Wed, Feb 26, 2025 at 10:00:22AM +0800, Mingcong Bai via B4 Relay wrote:
From: Mingcong Bai
As this component hooks into userspace API, it should be assumed that it
will play well with non-4K/64K pages.
Use `PAGE_SIZE' as the final reference for
Hi Matt,
在 2025/2/26 12:18, Matthew Brost 写道:
On Tue, Feb 25, 2025 at 09:13:09PM -0600, Lucas De Marchi wrote:
On Wed, Feb 26, 2025 at 10:00:18AM +0800, Mingcong Bai via B4 Relay wrote:
From: Mingcong Bai
The bo/ttm interfaces with kernel memory mapping from dedicated GPU
memory. It is not
From: Mingcong Bai
It appears that the xe_res_cursor also assumes 4K alignment.
Current code uses `PAGE_SIZE' as an assumed alignment reference but 4K
kernel page sizes is by no means a guarantee. On 16K-paged kernels, this
causes driver failures during boot up:
[ 23.2
From: Mingcong Bai
Similar to the preceding patch for GuC (and with the same references),
Intel DG1 and DG2 GPUs expects command buffers to align to 4K boundaries.
Current code uses `PAGE_SIZE' as an assumed alignment reference but 4K
kernel page sizes is by no means a guarantee. On 16K-
From: Mingcong Bai
Per the "Firmware" chapter in "drm/xe Intel GFX Driver", as well as
"Volume 8: Command Stream Programming" in "Intel® Arc™ A-Series Graphics
and Intel Data Center GPU Flex Series Open-Source Programmer's Reference
Manual For the discrete
From: Mingcong Bai
As this component hooks into userspace API, it should be assumed that it
will play well with non-4K/64K pages.
Use `PAGE_SIZE' as the final reference for page alignment instead.
Cc: sta...@vger.kernel.org
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver
From: Mingcong Bai
The bo/ttm interfaces with kernel memory mapping from dedicated GPU
memory. It is not correct to assume that SZ_4K would suffice for page
alignment as there are a few hardware platforms that commonly uses non-4K
pages - for instance, currently, Loongson 3A5000/6000 devices (of
ream,
https://github.com/AOSC-Tracking/linux/tree/aosc/v6.13.3
[^3]: Delicious hot pot!
https://repo.aosc.io/ahvl/sample-videos-20250223.tar.zst
Suggested-by: Kexy Biscuit
Co-developed-by: Shang Yatsen <429839...@qq.com>
Signed-off-by: Shang Yatsen <429839...@qq.com>
S
ream,
https://github.com/AOSC-Tracking/linux/tree/aosc/v6.13.3
[^3]: Delicious hot pot!
https://repo.aosc.io/ahvl/sample-videos-20250223.tar.zst
Suggested-by: Kexy Biscuit
Co-developed-by: Shang Yatsen <429839...@qq.com>
Signed-off-by: Shang Yatsen <429839...@qq.com>
S
6.8-rc1.
While this is harmless as the definitions did not change, so no compiler
warning was observed.
Drop this line anyway for the sake of correctness.
Cc: # v6.8-rc1+
Fixes: b79e8fd954c4 ("drm/xe: Remove dependency on intel_engine_regs.h")
Signed-off-by: Mingcong Bai
---
drivers/gp
Hi all,
在 2025/2/25 15:18, Mingcong Bai 写道:
Commit b79e8fd954c4 ("drm/xe: Remove dependency on intel_engine_regs.h")
introduced an internal set of engine registers, however, as part of this
change, it has also introduced two duplicate `define' lines for
`RING_CTL_SIZE(size)&#x
6.8-rc1.
While this is harmless as the definitions did not change, so no compiler
warning was observed.
Drop this line anyway for the sake of correctness.
Cc: # v6.8-rc1+
Fixes: b79e8fd954c4 ("drm/xe: Remove dependency on intel_engine_regs.h")
Signed-off-by: Mingcong Bai
---
drivers/gp
intainers may have a better idea on this).
Reported-By: Yang Wu
Tested-by: Yang Wu
Suggested-by: Mingcong Bai
looking at (and as distro maintainers, what we should be looking out
for).
Alex, would you care to elaborate?
Best Regards,
Mingcong Bai
Regards,
Dave.
drm-fixes-2024-11-17:
drm/amdgpu regression fix for 6.12-rc8
amdgpu:
- revert patch to fix swsmu regression
The following changes si
&bo->tbo.base);
+ ttm_bo_get(&bo->tbo);
return bo;
}
void radeon_bo_unref(struct radeon_bo **bo)
{
+ struct ttm_buffer_object *tbo;
+
if ((*bo) == NULL)
return;
- drm_gem_object_put(&(*bo)->tbo.base);
+ tbo = &((*bo)->tbo);
+ ttm_bo_put(tbo);
*bo = NULL;
}
Best Regards,
Mingcong Bai
31 matches
Mail list logo
