On 02-04-24, 13:31, Paul Cercueil wrote:
> Hi Vinod,
>
> Le jeudi 28 mars 2024 à 11:53 +0530, Vinod Koul a écrit :
> > On 10-03-24, 13:48, Paul Cercueil wrote:
> > > This function can be used to initiate a scatter-gather DMA
> > > transfer,
> > >
On 06-03-24, 11:16, Alexander Stein wrote:
> From: Sandor Yu
>
> Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort or HDMI PHY mode is configured in the driver.
>
ucture added to the generic union.
> >
> > The parameters added here are based on HDMI PHY
> > implementation practices. The current set of parameters
> > should cover the potential users.
> >
> > Signed-off-by: Sandor Yu
> > Reviewed-by: Dmitry Baryshko
with a new "flags"
> parameter to the function?
>
> v7:
> - Renamed *device_prep_slave_dma_vec() -> device_prep_peripheral_dma_vec();
> - Added a new flag parameter to the function as agreed between Paul
> and Vinod. I renamed the first parameter to prep_flags as it's s
qcom-qmp-combo: fix drm bridge registration
commit: d2d7b8e88023b75320662c2305d61779ff060950
[6/6] phy: qcom-qmp-combo: fix type-c switch registration
commit: 47b412c1ea77112f1148b4edd71700a388c7c80f
Best regards,
--
~Vinod
nks!
[1/1] phy: constify of_phandle_args in xlate
commit: 00ca8a15dafa990d391abc37f2b8256ddf909b35
Best regards,
--
~Vinod
orked to address this (i.e. by
> separating initialisation and registration of the PHY).
Acked-by: Vinod Koul
--
~Vinod
.
>
> Note that PHY creation can in theory also trigger a probe deferral when
> a 'phy' supply is used. This does not seem to affect the QMP PHY driver
> but the PHY subsystem should be reworked to address this (i.e. by
> separating initialisation and registration of the PHY).
Acked-by: Vinod Koul
--
~Vinod
gt; compatible PHY are configured in D-PHY mode.
>
> [...]
Applied, thanks!
[2/2] phy: mtk-mipi-csi: add driver for CSI phy
commit: 673d70cb3c652ad6d97594e03225bbdf20226216
Best regards,
--
~Vinod
On 11-01-24, 11:14, Julien Stephan wrote:
> Adding a new driver for the MIPI CSI CD-PHY module v 0.5 embedded in
> some Mediatek soc, such as the MT8365
You would want to fix the way you send patches, the series is disjoint.
I had to apply them manually, but please fix your process
--
~Vinod
> + return NULL;
> +
> + return chan->device->device_prep_slave_dma_vec(chan, vecs, nents,
> +dir, flags);
> +}
> +
> static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
> struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
> enum dma_transfer_direction dir, unsigned long flags)
> --
> 2.43.0
--
~Vinod
Hi Adam,
On 06-01-24, 16:19, Adam Ford wrote:
> From: Lucas Stach
>
> This adds the driver for the Samsung HDMI PHY found on the
> i.MX8MP SoC.
>
> Signed-off-by: Lucas Stach
> Signed-off-by: Adam Ford
> ---
> V2: Fixed some whitespace found from checkpatch
> Change error handling when
Hi Paul,
On 08-01-24, 13:20, Paul Cercueil wrote:
> Hi Vinod,
>
> Le jeudi 21 décembre 2023 à 20:44 +0530, Vinod Koul a écrit :
> > On 19-12-23, 18:50, Paul Cercueil wrote:
> > > This function can be used to initiate a scatter-gather DMA
> > > transfer,
> &g
dir, unsigned long flags)
> +{
> + if (!chan || !chan->device || !chan->device->device_prep_slave_dma_vec)
> + return NULL;
> +
> + return chan->device->device_prep_slave_dma_vec(chan, vecs, nents,
> +dir, flags);
> +}
> +
> static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
> struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
> enum dma_transfer_direction dir, unsigned long flags)
> --
> 2.43.0
--
~Vinod
forward by just adding new
> compatibles and add the correct DSI nodes to the SoC dtsi.
>
> [...]
Applied, thanks!
[2/4] dt-bindings: phy: add compatible for Mediatek MT8195
commit: fa50920b4f82993941e0aac349eb8081ce11e38f
Best regards,
--
~Vinod
parent syscon and drop example
commit: 130601d488fa06447283767e447909ce9e975e43
[04/12] dt-bindings: phy: amlogic,g12a-mipi-dphy-analog: drop unneeded reg
property and example
commit: 5f4a9a66f8a7582e90311fa8251da33a8d2111d7
Best regards,
--
~Vinod
the first place.
>
> [...]
Applied, thanks!
[08/31] phy: rockchip-inno-usb2: Split ID interrupt phy registers
commit: 2fda59099462ee700e424ba3ac928d13ad6389a8
[09/31] phy: phy-rockchip-inno-usb2: Add RK3128 support
commit: 62ff41017e147472b07de6125c3be82ce02a8dd7
Best regards,
--
~Vinod
uencies. Fix the minimal clamping value.
>
>
Applied, thanks!
[1/1] phy: mediatek: mipi: mt8183: fix minimal supported frequency
commit: 06f76e464ac81c6915430b7155769ea4ef16efe4
Best regards,
--
~Vinod
On 21-09-23, 16:01, Vinod Koul wrote:
> On 22-08-23, 20:22, Dmitry Baryshkov wrote:
> > On 22/08/2023 16:54, Vinod Koul wrote:
> > > On 17-08-23, 13:05, Dmitry Baryshkov wrote:
> > >> On 08/08/2023 11:32, Sandor Yu wrote:
> > >>> Allow H
cccd
[6/7] phy: freescale: Add DisplayPort PHY driver for i.MX8MQ
commit: a2717f1d7c64660679441c407b96103abb7c4a8c
[7/7] phy: freescale: Add HDMI PHY driver for i.MX8MQ
commit: 8e36091a94d2d28e8dccb9bfda081b2e42e951ae
Best regards,
--
~Vinod
river for i.MX8MQ
commit: 8e36091a94d2d28e8dccb9bfda081b2e42e951ae
Best regards,
--
~Vinod
On 22-08-23, 20:22, Dmitry Baryshkov wrote:
> On 22/08/2023 16:54, Vinod Koul wrote:
> > On 17-08-23, 13:05, Dmitry Baryshkov wrote:
> >> On 08/08/2023 11:32, Sandor Yu wrote:
> >>> Allow HDMI PHYs to be configured through the generic
> >>> functions throu
rising and falling edge variants.
> It's required as preparation to support RK312x's Innosilicon usb2 phy as
> well in this driver and matches pretty much to what the vendor does, so I'm
> not expecting issues for other SoCs with that change.
This fails to apply for phy/next
--
~Vinod
; > 2 files changed, 30 insertions(+), 1 deletion(-)
> > create mode 100644 include/linux/phy/phy-hdmi.h
>
> I think this looks good now, thank you!
>
> Reviewed-by: Dmitry Baryshkov
Should this go thru drm or phy...?
>
> --
> With best wishes
> Dmitry
--
~Vinod
On 17-08-23, 17:55, Dmitry Baryshkov wrote:
> Switch to using the new DRM_AUX_BRIDGE helper to create the
> transparent DRM bridge device instead of handcoding corresponding
> functionality.
Acked-by: Vinod Koul
--
~Vinod
wer up */
> + ret = hdptx_dp_phy_power_up(cdns_phy);
> +
> + return ret;
> +}
> +
> +static const struct phy_ops cdns_hdptx_dp_phy_ops = {
> + .init = cdns_hdptx_dp_phy_init,
> + .configure = cdns_hdptx_dp_configure,
> + .power_on = cdns_hdptx_dp_phy_on,
> + .power_off = cdns_hdptx_dp_phy_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int cdns_hdptx_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_dp_phy *cdns_phy;
> + struct device *dev = >dev;
> + struct device_node *node = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
> + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
> + if (!cdns_phy)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, cdns_phy);
> + cdns_phy->dev = dev;
> + mutex_init(_phy->mbox_mutex);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
> + cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
> + if (IS_ERR(cdns_phy->regs))
> + return PTR_ERR(cdns_phy->regs);
> +
> + phy = devm_phy_create(dev, node, _hdptx_dp_phy_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + phy->attrs.mode = PHY_MODE_DP;
> + cdns_phy->phy = phy;
> + phy_set_drvdata(phy, cdns_phy);
> +
> + ret = hdptx_dp_clk_enable(cdns_phy);
> + if (ret) {
> + dev_err(dev, "Init clk fail\n");
> + return -EINVAL;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + ret = PTR_ERR(phy_provider);
> + goto clk_disable;
> + }
> +
> + return 0;
> +
> +clk_disable:
> + hdptx_dp_clk_disable(cdns_phy);
> +
> + return -EINVAL;
> +}
> +
> +static int cdns_hdptx_dp_phy_remove(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_dp_phy *cdns_phy = platform_get_drvdata(pdev);
> +
> + hdptx_dp_clk_disable(cdns_phy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id cdns_hdptx_dp_phy_of_match[] = {
> + {.compatible = "fsl,imx8mq-dp-phy" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, cdns_hdptx_dp_phy_of_match);
> +
> +static struct platform_driver cdns_hdptx_dp_phy_driver = {
> + .probe = cdns_hdptx_dp_phy_probe,
> + .remove = cdns_hdptx_dp_phy_remove,
> + .driver = {
> + .name = "cdns-hdptx-dp-phy",
> + .of_match_table = cdns_hdptx_dp_phy_of_match,
> + }
> +};
> +module_platform_driver(cdns_hdptx_dp_phy_driver);
> +
> +MODULE_AUTHOR("Sandor Yu ");
> +MODULE_DESCRIPTION("Cadence HDP-TX DisplayPort PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
--
~Vinod
citly include the correct includes.
>
> [...]
Applied, thanks!
[1/1] phy: Explicitly include correct DT includes
commit: 7559e7572c03e433efec7734af6a674fdd83dd68
Best regards,
--
~Vinod
tch (phy_type) {
> + case PHY_TYPE_DPHY:
> + port->type = DPHY;
> + break;
> + default:
> + dev_err(dev, "Unsupported PHY type: %i\n", phy_type);
> + return -EINVAL;
> + }
> + } else {
> + port->type = CDPHY;
> + }
> +
> + phy = devm_phy_create(dev, NULL, _cdphy_ops);
> + if (IS_ERR(phy)) {
> + dev_err(dev, "Failed to create PHY: %ld\n", PTR_ERR(phy));
> + return PTR_ERR(phy);
> + }
> +
> + port->phy = phy;
> + phy_set_drvdata(phy, port);
> +
> + phy_provider = devm_of_phy_provider_register(dev, mtk_mipi_cdphy_xlate);
> + if (IS_ERR(phy_provider)) {
> + dev_err(dev, "Failed to register PHY provider: %ld\n",
> + PTR_ERR(phy_provider));
> + return PTR_ERR(phy_provider);
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_mipi_cdphy_of_match[] = {
> + { .compatible = "mediatek,mt8365-csi-rx" },
> + { /* sentinel */},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_mipi_cdphy_of_match);
> +
> +static struct platform_driver mipi_cdphy_pdrv = {
> + .probe = mtk_mipi_cdphy_probe,
> + .driver = {
> + .name = "mtk-mipi-csi-0-5",
> + .of_match_table = mtk_mipi_cdphy_of_match,
> + },
> +};
> +module_platform_driver(mipi_cdphy_pdrv);
> +
> +MODULE_DESCRIPTION("MediaTek MIPI CSI CD-PHY v0.5 Driver");
> +MODULE_AUTHOR("Louis Kuo ");
> +MODULE_LICENSE("GPL");
> --
> 2.41.0
--
~Vinod
ster clk_hw
commit: b1a34e7d196646a8fc0a6f91c2bf98943f3d440a
[2/3] phy: mediatek: mipi-dsi: Use devm variant for of_clk_add_hw_provider()
commit: e812c5b62a978ae67d23c5eb237959596734a86e
[3/3] phy: mediatek: mipi-dsi: Compress of_device_id match entries
commit: 5d295c1a20c747425c27dd9212ff091528136e55
Best regards,
--
~Vinod
1/1] phy: mediatek: hdmi: mt8195: fix prediv bad upper limit test
commit: 059c78ebf1e94a825e27cc3ef8a9d77cef06827e
Best regards,
--
~Vinod
On Tue, 11 Jul 2023 09:13:25 +0300, Dan Carpenter wrote:
> Negative -EINVAL was intended instead of positive EINVAL.
>
>
Applied, thanks!
[1/1] phy: phy-mtk-dp: Fix an error code in probe()
commit: 03966c3950d36d6b671158be3794eb7211434faa
Best regards,
--
~Vinod
if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) {
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_SVS_MODE_CLK_SEL, 1);
> + integloop_gain <<= 1;
> + } else {
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_SVS_MODE_CLK_SEL, 2);
> + integloop_gain <<= 2;
> + }
> +
> + integloop_gain = min_t(u32, integloop_gain, 2046);
> +
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_BG_TRIM, 0x0f);
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_PLL_IVCO, 0x0f);
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_VCO_TUNE_CTRL, 0);
> +
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_BG_CTRL, 0x06);
> +
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_CLK_SELECT, 0x30);
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_HSCLK_SEL, 0x20 | pd.hsclk_divsel);
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_LOCK_CMP_EN, 0x0);
> +
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_DEC_START_MODE0, dec_start);
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_DIV_FRAC_START1_MODE0,
> +frac_start & 0xff);
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_DIV_FRAC_START2_MODE0,
> +(frac_start >> 8) & 0xff);
> + hdmi_pll_write(hdmi_phy, QSERDES_COM_DIV_FRAC_START3_MODE0,
> +(frac_start >> 16) & 0xf);
FIELD_{PREP|GET} please
> +static int qmp_hdmi_8996_phy_power_on(struct phy *phy)
> +{
> + struct qmp_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
> + u32 status;
> + int i, ret = 0;
superfluous init for ret
--
~Vinod
/net/mediatek-dwmac.yaml | 2 +-
> .../bindings/perf/amlogic,g12-ddr-pmu.yaml | 4 ++--
> .../bindings/phy/mediatek,dsi-phy.yaml | 2 +-
Acked-by: Vinod Koul
--
~Vinod
fore HDMI PHY init */
> + ret = hdptx_phy_check_alive(cdns_phy);
> + if (ret == false) {
> + dev_err(cdns_phy->dev, "NO HDMI FW running\n");
> + return -ENXIO;
> + }
> +
> + /* Configure PHY */
> + if (hdptx_hdmi_phy_cfg(cdns_phy, cdns_phy->pixel_clk_rate) < 0) {
> + dev_err(cdns_phy->dev, "failed to set phy pclock\n");
> + return -EINVAL;
> + }
> +
> + ret = hdptx_hdmi_phy_power_up(cdns_phy);
> + if (ret < 0)
> + return ret;
> +
> + hdptx_hdmi_phy_set_vswing(cdns_phy);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops cdns_hdptx_hdmi_phy_ops = {
> + .init = cdns_hdptx_hdmi_phy_init,
> + .configure = cdns_hdptx_hdmi_configure,
> + .power_on = cdns_hdptx_hdmi_phy_on,
> + .power_off = cdns_hdptx_hdmi_phy_off,
> + .validate = cdns_hdptx_hdmi_phy_valid,
> + .owner = THIS_MODULE,
> +};
> +
> +static int cdns_hdptx_hdmi_phy_probe(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_hdmi_phy *cdns_phy;
> + struct device *dev = >dev;
> + struct device_node *node = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
> + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
> + if (!cdns_phy)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, cdns_phy);
> + cdns_phy->dev = dev;
> + mutex_init(_phy->mbox_mutex);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
> + cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
> + if (IS_ERR(cdns_phy->regs))
> + return PTR_ERR(cdns_phy->regs);
> +
> + phy = devm_phy_create(dev, node, _hdptx_hdmi_phy_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + phy->attrs.mode = PHY_MODE_HDMI;
> +
> + cdns_phy->phy = phy;
> + phy_set_drvdata(phy, cdns_phy);
> +
> + ret = hdptx_hdmi_clk_enable(cdns_phy);
> + if (ret) {
> + dev_err(dev, "Init clk fail\n");
> + return -EINVAL;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + ret = PTR_ERR(phy_provider);
> + goto clk_disable;
> + }
> +
> + dev_dbg(dev, "probe success!\n");
> +
> + return 0;
> +
> +clk_disable:
> + hdptx_hdmi_clk_disable(cdns_phy);
> +
> + return -EINVAL;
> +}
> +
> +static int cdns_hdptx_hdmi_phy_remove(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_hdmi_phy *cdns_phy = platform_get_drvdata(pdev);
> +
> + hdptx_hdmi_clk_disable(cdns_phy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id cdns_hdptx_hdmi_phy_of_match[] = {
> + {.compatible = "fsl,imx8mq-hdmi-phy" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, cdns_hdptx_hdmi_phy_of_match);
> +
> +static struct platform_driver cdns_hdptx_hdmi_phy_driver = {
> + .probe = cdns_hdptx_hdmi_phy_probe,
> + .remove = cdns_hdptx_hdmi_phy_remove,
> + .driver = {
> + .name = "cdns-hdptx-hdmi-phy",
> + .of_match_table = cdns_hdptx_hdmi_phy_of_match,
> + }
> +};
> +module_platform_driver(cdns_hdptx_hdmi_phy_driver);
> +
> +MODULE_AUTHOR("Sandor Yu ");
> +MODULE_DESCRIPTION("Cadence HDP-TX HDMI PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
--
~Vinod
> +
> + /* PHY power up */
> + ret = hdptx_dp_phy_power_up(cdns_phy);
> +
> + return ret;
> +}
> +
> +static const struct phy_ops cdns_hdptx_dp_phy_ops = {
> + .init = cdns_hdptx_dp_phy_init,
> + .configure = cdns_hdptx_dp_configure,
> + .power_on = cdns_hdptx_dp_phy_on,
> + .power_off = cdns_hdptx_dp_phy_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int cdns_hdptx_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_dp_phy *cdns_phy;
> + struct device *dev = >dev;
> + struct device_node *node = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
> + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
> + if (!cdns_phy)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, cdns_phy);
> + cdns_phy->dev = dev;
> + mutex_init(_phy->mbox_mutex);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
> + cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
> + if (IS_ERR(cdns_phy->regs))
> + return PTR_ERR(cdns_phy->regs);
> +
> + phy = devm_phy_create(dev, node, _hdptx_dp_phy_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + phy->attrs.mode = PHY_MODE_DP;
> + cdns_phy->phy = phy;
> + phy_set_drvdata(phy, cdns_phy);
> +
> + ret = hdptx_dp_clk_enable(cdns_phy);
> + if (ret) {
> + dev_err(dev, "Init clk fail\n");
> + return -EINVAL;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + ret = PTR_ERR(phy_provider);
> + goto clk_disable;
> + }
> +
> + return 0;
> +
> +clk_disable:
> + hdptx_dp_clk_disable(cdns_phy);
> +
> + return -EINVAL;
> +}
> +
> +static int cdns_hdptx_dp_phy_remove(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_dp_phy *cdns_phy = platform_get_drvdata(pdev);
> +
> + hdptx_dp_clk_disable(cdns_phy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id cdns_hdptx_dp_phy_of_match[] = {
> + {.compatible = "fsl,imx8mq-dp-phy" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, cdns_hdptx_dp_phy_of_match);
> +
> +static struct platform_driver cdns_hdptx_dp_phy_driver = {
> + .probe = cdns_hdptx_dp_phy_probe,
> + .remove = cdns_hdptx_dp_phy_remove,
> + .driver = {
> + .name = "cdns-hdptx-dp-phy",
> + .of_match_table = cdns_hdptx_dp_phy_of_match,
> + }
> +};
> +module_platform_driver(cdns_hdptx_dp_phy_driver);
> +
> +MODULE_AUTHOR("Sandor Yu ");
> +MODULE_DESCRIPTION("Cadence HDP-TX DisplayPort PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
--
~Vinod
et applicable for phys supporting
> + * the HDMI phy mode.
> */
> union phy_configure_opts {
> struct phy_configure_opts_mipi_dphy mipi_dphy;
> struct phy_configure_opts_dpdp;
> struct phy_configure_opts_lvds lvds;
> + struct phy_configure_opts_hdmi hdmi;
> };
>
> /**
> --
> 2.34.1
--
~Vinod
oint types
> 240 | else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA)
>
> Floating point should not be used, so rework the floating point comparisons
> to fixed point.
Applied, thanks
--
~Vinod
On 12-05-23, 15:11, Neil Armstrong wrote:
> Use the same CNTL2_DIF_TX_CTL0 value used by the vendor, it was reported
> fixing timings issues.
Applied to phy/fixes, thanks
--
~Vinod
On 08-05-23, 10:24, Matthias Brugger wrote:
>
>
> On 08/05/2023 09:48, Vinod Koul wrote:
> > On 05-05-23, 17:37, Matthias Brugger wrote:
> > >
> > >
> > > On 05/05/2023 11:28, Vinod Koul wrote:
> > > > On 14-04-23, 08:22, Tom Rix wrote:
On 05-05-23, 17:37, Matthias Brugger wrote:
>
>
> On 05/05/2023 11:28, Vinod Koul wrote:
> > On 14-04-23, 08:22, Tom Rix wrote:
> > > clang reports
> > > drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
> > >'ret' is uninitializ
tk_hdmi_pll_set_hw.
I have applied "phy: mediatek: hdmi: mt8195: fix uninitialized variable
usage in pll_calc"
--
~Vinod
oved to div_u64.
Applied both, thanks
--
~Vinod
alc") in phy/next and
should be in Linus's tree shortly
--
~Vinod
nb, dir, flags);
> +}
> +
> static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
> struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
> enum dma_transfer_direction dir, unsigned long flags)
> --
> 2.39.2
--
~Vinod
> On Fri, 31 Mar 2023 at 16:59, Vinod Polimera
> wrote:
> >
> > While in virtual terminal mode with PSR enabled, there will be
> > no atomic commits triggered without dirty_fb being set. This
> > will create a notion of no screen update. Allow atomic commit
> &g
> On Fri, 31 Mar 2023 at 16:59, Vinod Polimera
> wrote:
> >
> > In certain CPU stress conditions, there can be a delay in scheduling commit
> > work and it was observed that PSR commit from a different work queue
> was
> > scheduled. Avoid these commits
In certain CPU stress conditions, there can be a delay in scheduling commit
work and it was observed that PSR commit from a different work queue was
scheduled. Avoid these commits as display is already in PSR mode.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/msm_atomic.c | 3 +++
1
Certain flags like dirty_fb will be updated into the plane state
during crtc atomic_check. Allow those updates during PSR commit.
Reported-by: Bjorn Andersson
Link: https://lore.kernel.org/all/20230326162723.3lo6pnsfdwzsvbhj@ripper/
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp
-by: Bjorn Andersson
Link: https://lore.kernel.org/all/20230326162723.3lo6pnsfdwzsvbhj@ripper/
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1
already.
Vinod Polimera (3):
drm/msm/dpu: set dirty_fb flag while in self refresh mode
msm/disp/dpu: allow atomic_check in PSR usecase
msm: skip the atomic commit of self refresh while PSR running
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 -
drivers/gpu/drm/msm/msm_atomic.c
> -Original Message-
> From: Doug Anderson
> Sent: Thursday, March 30, 2023 7:54 PM
> To: Vinod Polimera
> Cc: Stephen Boyd ; Bjorn Andersson
> ; Vinod Polimera (QUIC)
> ; robdcl...@gmail.com; dri-
> de...@lists.freedesktop.org; linux-arm-...@v
> -Original Message-
> From: Stephen Boyd
> Sent: Monday, March 27, 2023 9:58 PM
> To: Bjorn Andersson ; Vinod Polimera (QUIC)
>
> Cc: dri-devel@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.ker
From: Bjorn Andersson
This panel is found in Lenovo Flex 5G laptop, so add the entry for it
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/panel/panel-edp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-edp.c
b/drivers/gpu/drm
; Note that this series depends on commit 5c5a7680e67b ("platform: Provide
> a remove callback that returns no value") which is included in v6.3-rc1.
Applied, thanks
--
~Vinod
> -Original Message-
> From: Vinod Polimera (QUIC)
> Sent: Thursday, March 2, 2023 10:03 PM
> To: dri-devel@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.kernel.org
> Cc: Vinod Polimera (QUIC) ; linux-
> k
> -Original Message-
> From: Doug Anderson
> Sent: Thursday, March 2, 2023 2:02 AM
> To: Vinod Polimera (QUIC)
> Cc: dri-devel@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.kernel.org; linux-
> ker...@vg
For the PSR to kick in, self_refresh_aware has to be set.
Initialize it based on the PSR support for the eDP interface.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/dp/dp_drm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10
,
edp_bridge_mode_valid under the eDP bridge ops.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 8
drivers/gpu/drm/msm/dp/dp_drm.c | 34 +-
2 files changed, 33
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/dr
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Daniel Vetter
---
drivers/gpu
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
Reviewed-by: Daniel Vetter
---
drivers/gpu
the series.(Dmitry)
- Drop self refresh aware disable change after psr entry.(Dmitry)
Changes in v14:
- Set self_refresh_aware for the PSR to kick in.
Vinod Polimera (14):
drm: add helper functions to retrieve old and new crtc
drm/bridge: use atomic enable/disable callbacks for panel br
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
,
edp_bridge_mode_valid under the eDP bridge ops.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 8
drivers/gpu/drm/msm/dp/dp_drm.c | 34 +-
2 files changed, 33
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/dr
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Daniel Vetter
---
drivers/gpu
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
Reviewed-by: Daniel Vetter
---
drivers/gpu
the series.(Dmitry)
- Drop self refresh aware disable change after psr entry.(Dmitry)
Vinod Polimera (13):
drm: add helper functions to retrieve old and new crtc
drm/bridge: use atomic enable/disable callbacks for panel bridge
drm/bridge: add psr support for panel bridge callbacks
drm/ms
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Tuesday, January 31, 2023 6:19 PM
> To: Vinod Polimera (QUIC) ; dri-
> de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.kernel.org
> Cc: Sanke
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Tuesday, January 31, 2023 6:29 PM
> To: Vinod Polimera (QUIC) ; dri-
> de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.kernel.org
> Cc: linux-k
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Daniel Vetter
---
drivers/gpu
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm
,
edp_bridge_mode_valid under the eDP bridge ops.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 8
drivers/gpu/drm/msm/dp/dp_drm.c | 34 +-
2 files changed, 33
From: Sankeerth Billakanti
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
Reviewed-by: Daniel Vetter
---
drivers/gpu
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm
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