On 02-04-24, 13:31, Paul Cercueil wrote:
> Hi Vinod,
>
> Le jeudi 28 mars 2024 à 11:53 +0530, Vinod Koul a écrit :
> > On 10-03-24, 13:48, Paul Cercueil wrote:
> > > This function can be used to initiate a scatter-gather DMA
> > > transfer,
> > >
On 06-03-24, 11:16, Alexander Stein wrote:
> From: Sandor Yu
>
> Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort or HDMI PHY mode is configured in the driver.
>
ucture added to the generic union.
> >
> > The parameters added here are based on HDMI PHY
> > implementation practices. The current set of parameters
> > should cover the potential users.
> >
> > Signed-off-by: Sandor Yu
> > Reviewed-by: Dmitry Baryshko
On 10-03-24, 13:48, Paul Cercueil wrote:
> This function can be used to initiate a scatter-gather DMA transfer,
> where the address and size of each segment is located in one entry of
> the dma_vec array.
>
> The major difference with dmaengine_prep_slave_sg() is that it supports
> specifying the
On Sat, 17 Feb 2024 16:02:22 +0100, Johan Hovold wrote:
> Starting with 6.8-rc1 the internal display sometimes fails to come up on
> machines like the Lenovo ThinkPad X13s and the logs indicate that this
> is due to a regression in the DRM subsystem [1].
>
> This series fixes a race in the
On Sat, 17 Feb 2024 10:39:37 +0100, Krzysztof Kozlowski wrote:
> The xlate callbacks are supposed to translate of_phandle_args to proper
> provider without modifying the of_phandle_args. Make the argument
> pointer to const for code safety and readability.
>
>
Applied, thanks!
[1/1] phy:
orked to address this (i.e. by
> separating initialisation and registration of the PHY).
Acked-by: Vinod Koul
--
~Vinod
.
>
> Note that PHY creation can in theory also trigger a probe deferral when
> a 'phy' supply is used. This does not seem to affect the QMP PHY driver
> but the PHY subsystem should be reworked to address this (i.e. by
> separating initialisation and registration of the PHY).
Acked-by: Vinod Koul
--
~Vinod
On Thu, 11 Jan 2024 11:17:30 +0100, Julien Stephan wrote:
> This is a new driver that supports the MIPI CSI CD-PHY version 0.5
>
> The number of PHYs depend on the SoC.
> Each PHY can support D-PHY only or CD-PHY configuration.
> The driver supports only D-PHY mode, so CD-PHY
> compatible PHY
On 11-01-24, 11:14, Julien Stephan wrote:
> Adding a new driver for the MIPI CSI CD-PHY module v 0.5 embedded in
> some Mediatek soc, such as the MT8365
You would want to fix the way you send patches, the series is disjoint.
I had to apply them manually, but please fix your process
--
~Vinod
On 29-01-24, 18:01, Paul Cercueil wrote:
> This function can be used to initiate a scatter-gather DMA transfer,
> where the address and size of each segment is located in one entry of
> the dma_vec array.
>
> The major difference with dmaengine_prep_slave_sg() is that it supports
> specifying the
Hi Adam,
On 06-01-24, 16:19, Adam Ford wrote:
> From: Lucas Stach
>
> This adds the driver for the Samsung HDMI PHY found on the
> i.MX8MP SoC.
>
> Signed-off-by: Lucas Stach
> Signed-off-by: Adam Ford
> ---
> V2: Fixed some whitespace found from checkpatch
> Change error handling when
Hi Paul,
On 08-01-24, 13:20, Paul Cercueil wrote:
> Hi Vinod,
>
> Le jeudi 21 décembre 2023 à 20:44 +0530, Vinod Koul a écrit :
> > On 19-12-23, 18:50, Paul Cercueil wrote:
> > > This function can be used to initiate a scatter-gather DMA
> > > transfer,
> &g
On 19-12-23, 18:50, Paul Cercueil wrote:
> This function can be used to initiate a scatter-gather DMA transfer,
> where the address and size of each segment is located in one entry of
> the dma_vec array.
>
> The major difference with dmaengine_prep_slave_sg() is that it supports
> specifying the
On Thu, 23 Nov 2023 14:37:45 +0100, Michael Walle wrote:
> Add support for a DSI output on VDOSYS0. Luckily, there is a new
> feature to support dynamic selections of the output (connector).
> Use it to add support for a DSI output.
>
> Apart from that, this is pretty straghtforward by just
On Fri, 24 Nov 2023 09:41:11 +0100, Neil Armstrong wrote:
> The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
> (ver 1.21a),
> with a custom glue managing the IP resets, clock and data input similar to
> the DW-HDMI
> glue on the same Amlogic SoCs.
>
> This is a
On Tue, 29 Aug 2023 19:16:16 +0200, Alex Bee wrote:
> this series fixes some issues I found when testing my "new" RK3128 board
> with the mainline kernel and adds some core functionality like SMP bringup,
> usb and networking.
>
> The propably most distinctive change is the split up of the DTs
On Thu, 23 Nov 2023 12:02:02 +0100, Michael Walle wrote:
> The lowest supported clock frequency of the PHY is 125MHz (see also
> mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the
> wrong minimal value, which will make the .enable() op return -EINVAL on
> low frequencies. Fix
On 21-09-23, 16:01, Vinod Koul wrote:
> On 22-08-23, 20:22, Dmitry Baryshkov wrote:
> > On 22/08/2023 16:54, Vinod Koul wrote:
> > > On 17-08-23, 13:05, Dmitry Baryshkov wrote:
> > >> On 08/08/2023 11:32, Sandor Yu wrote:
> > >>> Allow H
On Thu, 07 Sep 2023 09:05:27 +0800, Sandor Yu wrote:
> The patch set initial support Cadence MHDP8501(HDMI/DP) DRM bridge
> drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for Freescale i.MX8MQ.
>
> The patch set compose of DRM bridge drivers and PHY drivers.
>
> Both of them need the followed
On Thu, 15 Jun 2023 09:38:10 +0800, Sandor Yu wrote:
> The patch set initial support for Cadence MHDP8501(HDMI/DP) DRM bridge
> drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for Freescale i.MX8MQ.
>
> The patch set compose of DRM bridge drivers and PHY drivers.
>
> Both of them need the
On 22-08-23, 20:22, Dmitry Baryshkov wrote:
> On 22/08/2023 16:54, Vinod Koul wrote:
> > On 17-08-23, 13:05, Dmitry Baryshkov wrote:
> >> On 08/08/2023 11:32, Sandor Yu wrote:
> >>> Allow HDMI PHYs to be configured through the generic
> >>> functions throu
On 29-08-23, 19:16, Alex Bee wrote:
> Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID
> detection interrupt registers. However the current implementation assumes
> that falling and rising edge interrupt are always enabled in registers
> spaning over subsequent bits.
> That
On 17-08-23, 13:05, Dmitry Baryshkov wrote:
> On 08/08/2023 11:32, Sandor Yu wrote:
> > Allow HDMI PHYs to be configured through the generic
> > functions through a custom structure added to the generic union.
> >
> > The parameters added here are based on HDMI PHY
> > implementation practices.
On 17-08-23, 17:55, Dmitry Baryshkov wrote:
> Switch to using the new DRM_AUX_BRIDGE helper to create the
> transparent DRM bridge device instead of handcoding corresponding
> functionality.
Acked-by: Vinod Koul
--
~Vinod
On 17-07-23, 16:03, Sandor Yu wrote:
> Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort PHY mode is configurated in the driver.
>
> Signed-off-by: Sandor Yu
> ---
>
On Fri, 14 Jul 2023 11:48:35 -0600, Rob Herring wrote:
> The DT of_device.h and of_platform.h date back to the separate
> of_platform_bus_type before it as merged into the regular platform bus.
> As part of that merge prepping Arm DT support 13 years ago, they
> "temporarily" include each other.
On 20-06-23, 14:18, Julien Stephan wrote:
> From: Phi-bang Nguyen
>
> This is a new driver that supports the MIPI CSI CD-PHY version 0.5
>
> The number of PHYs depend on the SoC.
> Each PHY can support D-PHY only or CD-PHY configuration.
> The driver supports only D-PHY mode, so CD-PHY
>
On Thu, 25 May 2023 13:52:55 +0200, AngeloGioacchino Del Regno wrote:
> This series performs some cleanups to the MediaTek mipi-dsi PHY, used in
> various MediaTek SoCs; in particular, it's migrating this driver to
> register its clock as clk_hw provider instead and makes use of the devm
>
On Tue, 30 May 2023 10:43:07 +0200, Guillaume Ranquet wrote:
> The pll prediv calculus searchs for the smallest prediv that gets
> the ns_hdmipll_ck in the range of 5 GHz to 12 GHz.
>
> A typo in the upper bound test was testing for 5Ghz to 1Ghz
>
>
Applied, thanks!
[1/1] phy: mediatek:
On Tue, 11 Jul 2023 09:13:25 +0300, Dan Carpenter wrote:
> Negative -EINVAL was intended instead of positive EINVAL.
>
>
Applied, thanks!
[1/1] phy: phy-mtk-dp: Fix an error code in probe()
commit: 03966c3950d36d6b671158be3794eb7211434faa
Best regards,
--
~Vinod
On 23-05-23, 15:14, Dmitry Baryshkov wrote:
> Port Qualcomm QMP HDMI PHY to the generic PHY framework. Split the
> generic part and the msm8996 part. When adding support for msm8992/4 and
> msm8998 (which also employ QMP for HDMI PHY), one will have to provide
> the PLL programming part only.
>
>
/net/mediatek-dwmac.yaml | 2 +-
> .../bindings/perf/amlogic,g12-ddr-pmu.yaml | 4 ++--
> .../bindings/phy/mediatek,dsi-phy.yaml | 2 +-
Acked-by: Vinod Koul
--
~Vinod
On 15-06-23, 09:38, Sandor Yu wrote:
> Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> HDMI PHY mode is configurated in the driver.
>
> Signed-off-by: Sandor Yu
> ---
>
On 15-06-23, 09:38, Sandor Yu wrote:
> Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort PHY mode is configurated in the driver.
>
> Signed-off-by: Sandor Yu
> ---
>
On 15-06-23, 09:38, Sandor Yu wrote:
> Allow HDMI PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
>
> The parameters added here are based on HDMI PHY
> implementation practices. The current set of parameters
> should cover the
On 02-05-23, 10:50, Tom Rix wrote:
> gcc on aarch64 reports
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function
> ‘mtk_hdmi_pll_set_rate’:
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error:
> ‘-mgeneral-regs-only’
> is incompatible with the use of floating-point types
> 240 |
On 12-05-23, 15:11, Neil Armstrong wrote:
> Use the same CNTL2_DIF_TX_CTL0 value used by the vendor, it was reported
> fixing timings issues.
Applied to phy/fixes, thanks
--
~Vinod
On 08-05-23, 10:24, Matthias Brugger wrote:
>
>
> On 08/05/2023 09:48, Vinod Koul wrote:
> > On 05-05-23, 17:37, Matthias Brugger wrote:
> > >
> > >
> > > On 05/05/2023 11:28, Vinod Koul wrote:
> > > > On 14-04-23, 08:22, Tom Rix wrote:
On 05-05-23, 17:37, Matthias Brugger wrote:
>
>
> On 05/05/2023 11:28, Vinod Koul wrote:
> > On 14-04-23, 08:22, Tom Rix wrote:
> > > clang reports
> > > drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
> > >'ret' is uninitializ
On 14-04-23, 08:22, Tom Rix wrote:
> clang reports
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
> 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
> if (ret)
> ^~~
> ret should have been set by the preceding call to mtk_hdmi_pll_set_hw.
On 13-04-23, 14:46, Guillaume Ranquet wrote:
> I've received a report from kernel test report [1] that a variable was used
> unitialized in the mtk8195 hdmi phy code.
>
> I've upon fixing that issue found out that the clock rate calculation
> was erroneous since the calculus was moved to div_u64.
On 04-05-23, 17:19, Palmer Dabbelt wrote:
> From: Palmer Dabbelt
>
> This trips up a maybe-uninitialized warning, but it's actually just not
> used.
Thanks but this is already fixed by 714dd3c29a22 ("phy: mediatek: hdmi:
mt8195: fix uninitialized variable usage in pll_calc") in phy/next and
On 03-04-23, 17:47, Paul Cercueil wrote:
> This function can be used to initiate a scatter-gather DMA transfer
> where the DMA addresses and lengths are located inside arrays.
>
> The major difference with dmaengine_prep_slave_sg() is that it supports
> specifying the lengths of each DMA
From: Bjorn Andersson
This panel is found in Lenovo Flex 5G laptop, so add the entry for it
Signed-off-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/panel/panel-edp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-edp.c
b/drivers/gpu/drm
On 07-03-23, 12:58, Uwe Kleine-König wrote:
> Hello,
>
> this patch series adapts the platform drivers below drivers/phy to use the
> .remove_new() callback. Compared to the traditional .remove() callback
> .remove_new() returns no value. This is a good thing because the driver core
> doesn't
On 02-10-22, 08:45, Michael Trimarchi wrote:
> The function is used to avoid to enable clock on the hardware
> if the mode requested is invalid
>
> Signed-off-by: Michael Trimarchi
> ---
> .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 19 +++
> 1 file changed, 19 insertions(+)
On 08-11-22, 21:00, Sandor Yu wrote:
> Add Cadence HDP-TX DisplayPort PHY driver.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort PHY mode is configurated in the driver.
>
> Signed-off-by: Sandor Yu
> ---
>
On 08-11-22, 21:00, Sandor Yu wrote:
> Allow HDMI PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
>
> The parameters added here are based on HDMI PHY
> implementation practices. The current set of parameters
> should cover the
On 04-11-22, 15:09, Guillaume Ranquet wrote:
> Add basic support for the mediatek hdmi phy on MT8195 SoC
Are phy patches in this series dependent upon changes in drm/, if not
consider splitting them up!
>
> Signed-off-by: Guillaume Ranquet
> ---
> drivers/phy/mediatek/Makefile |
On 04-11-22, 16:13, Dmitry Baryshkov wrote:
> Enable MDSS/DPU/DSI0 on SM8450-HDK device. Note, there is no panel
> configuration (yet).
>
> Signed-off-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git
efully the last time to
> fix these.
>
> Fix the indentation in intel,phy-thunderbay-emmc while we're here.
Acked-By: Vinod Koul
--
~Vinod
, hence the choice has been
> made to cover up for this while packing the value into a smaller field
> instead.
Thanks for fixing these. I dont have my pixel3 availble but changes lgtm
Reviewed-by: Vinod Koul
> Altogether this series is responsible for solving _all_ Display Strea
On 29-09-22, 14:01, Colin Ian King wrote:
> Don't populate the read-only array driving_params on the stack but instead
> make it static const. Also makes the object code a little smaller.
Applied, thanks
--
~Vinod
On 20-09-22, 17:00, Chunfeng Yun wrote:
> No need to define new macros to generate bits, mask and bitfield, use
> common ones instead, e.g. BIT, GENMASK and FIELD_PREP etc.
> Due to common register access helpers are defined for MediaTek's phy
> drivers, the similar helpers defined by ufs, hdmi
On 22-09-22, 14:30, Dmitry Baryshkov wrote:
> This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
Tested this on DM8450-HDK with HDMI and it works for me.
For whole series:
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
>
> Dmitry Baryshkov (5):
> drm/
On 07-07-22, 21:53, Yang Yingliang wrote:
> mtk_dp_phy_driver is only used in phy-mtk-dp.c now, change it to static.
Applied, thanks
--
~Vinod
On 05-07-22, 09:29, Kuogee Hsieh wrote:
> 0) rebase on
> https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git tree
> 1) add regulator_set_load() to eDP phy
> 2) add regulator_set_load() to DP phy
> 3) remove vdda related function out of eDP/DP controller
Applied, thanks
--
~Vinod
On 05-07-22, 22:52, Conor Dooley wrote:
> From: Conor Dooley
>
> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> controller, but according to the documentation & devicetree it has 6
> interrupts rather than the standard one. Support the 6 interrupt
> configuration by
On 01-07-22, 20:22, Conor Dooley wrote:
> From: Conor Dooley
>
> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> controller, but according to the documentation & devicetree it has 6
> interrupts rather than the standard one. Support the 6 interrupt
> configuration by
On 04-07-22, 19:11, Dmitry Baryshkov wrote:
> As the QMP HDMI PHY is a clock provider, add constant #clock-cells
> property. For the compatibility with older DTs the property is not
> marked as required. Also add the XO clock to the list of the clocks used
> by the driver.
Acked-By
On 17-06-22, 13:36, Dmitry Baryshkov wrote:
> As the QMP HDMI PHY is a clock provider, add constant #clock-cells
> property. For the compatibility with older DTs the property is not
> marked as required.
Acked-By: Vinod Koul
--
~Vinod
On 24-06-22, 14:27, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann
>
> This is a new driver that supports the integrated DisplayPort phy for
> mediatek SoCs, especially the mt8195. The phy is integrated into the
> DisplayPort controller and will be created by the mtk-dp driver. This
>
On 21-06-22, 10:01, Kuogee Hsieh wrote:
> This patch add regulator_set_load() before enable regulator at
> DP phy driver.
>
> Signed-off-by: Kuogee Hsieh
> Reviewed-by: Stephen Boyd
> Reviewed-by: Douglas Anderson
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 43
>
the new flag.
Acked-By: Vinod Koul
--
~Vinod
On 20-06-22, 13:43, Kuogee Hsieh wrote:
>
> On 6/20/2022 1:07 PM, Kuogee Hsieh wrote:
> >
> > On 6/16/2022 5:02 PM, Vinod Koul wrote:
> > > On 25-05-22, 14:02, Kuogee Hsieh wrote:
> > > > 1) add regulator_set_load() to eDP phy
> > > > 2) add re
On 13-06-22, 15:26, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann
>
> This is a new driver that supports the integrated DisplayPort phy for
> mediatek SoCs, especially the mt8195. The phy is integrated into the
> DisplayPort controller and will be created by the mtk-dp driver. This
>
On 16-06-22, 08:35, Doug Anderson wrote:
> Hi,
>
> On Mon, Apr 25, 2022 at 2:07 PM Douglas Anderson
> wrote:
> >
> > We're supposed to list the supplies in the dt bindings but there are
> > none in the eDP PHY bindings.
> >
> > Looking at the driver in Linux, I can see that there seem to be two
On 25-05-22, 14:02, Kuogee Hsieh wrote:
> 1) add regulator_set_load() to eDP phy
> 2) add regulator_set_load() to DP phy
> 3) remove vdda related function out of eDP/DP controller
>
> Kuogee Hsieh (3):
> phy: qcom-edp: add regulator_set_load to edp phy
> phy: qcom-qmp: add regulator_set_load
On 23-05-22, 12:47, Guillaume Ranquet wrote:
> From: Markus Schneider-Pargmann
>
> This is a new driver that supports the integrated DisplayPort phy for
> mediatek SoCs, especially the mt8195. The phy is integrated into the
> DisplayPort controller and will be created by the mtk-dp driver. This
y: kernel test robot
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
changes in v2:
- add r-b from Dmitry & Abhinav
- fix typo for superfluous
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/msm
l test robot
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 51f24ba68375..388125c8bda1 100644
--- a/drivers/gpu/drm/msm/dis
On 18-05-22, 14:36, Kuogee Hsieh wrote:
> This patch add regulator_set_load() before enable regulator at
> DP phy driver.
sigh! still wrong tags!
>
> Signed-off-by: Kuogee Hsieh
> Reviewed-by: Stephen Boyd
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 12
> 1 file changed, 12
On 17-05-22, 10:25, Kuogee Hsieh wrote:
pls use the correct subsystem tag, "phy: xxx" in this case
> This patch add regulator_set_load() to both eDP and DP phy driver
> to have totally control regulators.
Can you explain what is meant by "totally control regulators"
>
> Signed-off-by: Kuogee
On 06-05-22, 20:10, Lucas Stach wrote:
> This adds the driver for the Samsung HDMI PHY found on the
> i.MX8MP SoC.
>
> Signed-off-by: Lucas Stach
> ---
> drivers/phy/freescale/Kconfig|6 +
> drivers/phy/freescale/Makefile |1 +
>
On 02-05-22, 10:43, Marijn Suijten wrote:
> On 2022-05-02 01:44:20, Dmitry Baryshkov wrote:
> that require DSC for the screen to work. I've been told the series
> didn't result in positive screen output way back in its infancy, but
I would be intrested to hear about that. I have only pixel3 at
On 01-05-22, 22:41, Marijn Suijten wrote:
> On 2022-04-30 22:28:42, Dmitry Baryshkov wrote:
> > On 30/04/2022 21:58, Marijn Suijten wrote:
> > > On 2022-04-30 20:55:33, Dmitry Baryshkov wrote:
> > >> The downstream uses read-modify-write for updating command mode
> > >> compression registers.
On 30-04-22, 22:28, Dmitry Baryshkov wrote:
> On 30/04/2022 21:58, Marijn Suijten wrote:
> > On 2022-04-30 20:55:33, Dmitry Baryshkov wrote:
> > > The downstream uses read-modify-write for updating command mode
> > > compression registers. Let's follow this approach. This also fixes the
> > >
'reg_ctrl' set
> but not used [-Wunused-but-set-variable]
Reviewed-by: Vinod Koul
Tested on pixel3:
Tested-by: Vinod Koul
--
~Vinod
ost_device. This way MIPI DSI host
> driver receives DSC data during attach callback without additional
> lookups.
Reviewed-by: Vinod Koul
I tested this on my pixel3 and had to change how panel driver handles
this, with that it worked just fine
Tested-by: Vinod Koul
--
~Vinod
s' or 'maxItems' with the
> same size as the list is redundant and can be dropped. Note that is DT
> schema specific behavior and not standard json-schema behavior. The tooling
> will fixup the final schema adding any unspecified minItems/maxItems.
For phy:
Acked-By: Vinod Koul
--
~Vinod
On 19-04-22, 15:37, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The legacy interface for omap-dma is only used on OMAP1, and the
> same is true for the non-DT case. Make both of these conditional on
> CONFIG_ARCH_OMAP1 being set to simplify the dependency.
Acked-By: Vinod Koul
--
~Vinod
On 19-04-22, 09:08, Liu Ying wrote:
> Hi,
>
> This is the v8 series to add i.MX8qxp LVDS PHY mode support for the Mixel
> PHY in the Freescale i.MX8qxp SoC.
>
> The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either
> MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled
this looks good to me:
Reviewed-by: Vinod Koul
--
~Vinod
On 13-04-22, 20:39, Liu Ying wrote:
> On Wed, 2022-04-13 at 16:19 +0530, Vinod Koul wrote:
> > On 13-04-22, 18:04, Liu Ying wrote:
> > > Hi Vinod,
> > >
> > > On Wed, 2022-04-13 at 11:41 +0530, Vinod Koul wrote:
> > > > On 02-04-22, 13:24, Liu Y
On 13-04-22, 18:04, Liu Ying wrote:
> Hi Vinod,
>
> On Wed, 2022-04-13 at 11:41 +0530, Vinod Koul wrote:
> > On 02-04-22, 13:24, Liu Ying wrote:
> > > This patch allows LVDS PHYs to be configured through
> > > the generic functions and through a custom structure
On 28-03-22, 16:52, AngeloGioacchino Del Regno wrote:
> Use the dev_err_probe() helper to simplify error handling during probe.
Applied, thanks
--
~Vinod
On 28-03-22, 13:10, AngeloGioacchino Del Regno wrote:
> Use the dev_err_probe() helper to simplify error handling during probe.
Applied, thanks
--
~Vinod
qxp Mixel combo PHY, i.e., the MIPI DPHY mode is yet to be
> supported, so for now error would be returned from ->set_mode() if MIPI
> DPHY mode is passed over to it for the combo PHY.
>
> Cc: Guido Günther
> Cc: Robert Chiras
> Cc: Kishon Vijay Abraham I
> Cc: Vinod
arameters
> should cover all potential users.
>
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: NXP Linux Team
> Signed-off-by: Liu Ying
> ---
> v5->v6:
> * Rebase upon v5.17-rc1.
>
> v4->v5:
> * Align kernel-doc style to include/linux/phy/phy.h. (V
-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 98 +-
1 file changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index eb0be34add45..f3ed6c40b9e1 100644
Update headers from mesa commit:
commit 28ae397be111c37c6ced397e12d453a7695701bd
Author: Vinod Koul
Date: Fri Apr 1 16:53:04 2022 +0530
freedreno/registers: update dsi registers to support dsc
Display Stream compression (DSC) compresses the display stream in
host
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi.h
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +
drivers/gpu/drm/msm/disp/dpu1
.
The panel has been tested only with 2,2,1 configuration, so for
now we blindly create 2,2,1 topology when DSC is enabled
Co-developed-by: Abhinav Kumar
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13
Somehow documentation for num_dspp was missed, so add that
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4 +++-
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
1 - 100 of 379 matches
Mail list logo
