Hi Christian,
On 2023-08-21 07:03, Christian König wrote:
> Am 20.08.23 um 11:51 schrieb Christophe JAILLET:
>> This serie simplifies amdgpu_bo_list_create() and usage of the 'struct
>> amdgpu_bo_list'.
> Oh, yes please. That's something I always wanted to cleanup as well.
>
>> It is compile
On 2023-05-10 10:19, Luben Tuikov wrote:
> On 2023-05-10 09:51, vitaly.pros...@amd.com wrote:
>> From: Vitaly Prosyak
>>
>> During an IGT GPU reset test we see again oops despite of
>> commit 0c8c901aaaebc9 (drm/sched: Check scheduler ready before calling
>>
On 2021-09-23 9:40 a.m., Harry Wentland wrote:
On 2021-09-23 04:01, Pekka Paalanen wrote:
On Wed, 22 Sep 2021 11:06:53 -0400
Harry Wentland wrote:
On 2021-09-20 20:14, Harry Wentland wrote:
On 2021-09-15 10:01, Pekka Paalanen wrote:> On Fri, 30 Jul 2021 16:41:29 -0400
Harry Wentland
On 2021-05-17 12:48 p.m., Sebastian Wick wrote:
On 2021-05-17 10:57, Pekka Paalanen wrote:
On Fri, 14 May 2021 17:05:11 -0400
Harry Wentland wrote:
On 2021-04-27 10:50 a.m., Pekka Paalanen wrote:
> On Mon, 26 Apr 2021 13:38:49 -0400
> Harry Wentland wrote:
...
>> ## Mastering
On 2020-10-21 10:35 a.m., Ville Syrjälä wrote:
On Tue, Oct 20, 2020 at 09:46:30PM -0400, Vitaly Prosyak wrote:
On 2020-10-20 11:04 a.m., Ville Syrjälä wrote:
On Mon, Oct 19, 2020 at 11:08:27PM -0400, Vitaly Prosyak wrote:
On 2020-10-19 3:49 a.m., Pekka Paalanen wrote:
On Fri, 16 Oct 2020 16
On 2020-10-20 11:04 a.m., Ville Syrjälä wrote:
On Mon, Oct 19, 2020 at 11:08:27PM -0400, Vitaly Prosyak wrote:
On 2020-10-19 3:49 a.m., Pekka Paalanen wrote:
On Fri, 16 Oct 2020 16:50:16 +0300
Ville Syrjälä wrote:
On Mon, Oct 12, 2020 at 10:11:01AM +0300, Pekka Paalanen wrote:
On Fri, 9
On 2020-10-19 3:49 a.m., Pekka Paalanen wrote:
On Fri, 16 Oct 2020 16:50:16 +0300
Ville Syrjälä wrote:
On Mon, Oct 12, 2020 at 10:11:01AM +0300, Pekka Paalanen wrote:
On Fri, 9 Oct 2020 17:20:18 +0300
Ville Syrjälä wrote:
On Fri, Oct 09, 2020 at 04:56:51PM +0300, Pekka Paalanen wrote:
On 2020-09-10 2:07 p.m., Vitaly Prosyak wrote:
On 2020-09-10 1:51 p.m., Laurent Pinchart wrote:
Hi Vitaly,
On Thu, Sep 10, 2020 at 01:09:03PM -0400, Vitaly Prosyak wrote:
On 2020-09-10 6:56 a.m., Laurent Pinchart wrote:
On Thu, Sep 10, 2020 at 01:28:03PM +0300, Pekka Paalanen wrote
On 2020-09-10 1:51 p.m., Laurent Pinchart wrote:
Hi Vitaly,
On Thu, Sep 10, 2020 at 01:09:03PM -0400, Vitaly Prosyak wrote:
On 2020-09-10 6:56 a.m., Laurent Pinchart wrote:
On Thu, Sep 10, 2020 at 01:28:03PM +0300, Pekka Paalanen wrote:
On Thu, 10 Sep 2020 12:30:09 +0300 Laurentiu Palcu
On 2020-09-10 6:56 a.m., Laurent Pinchart wrote:
Hi Pekka,
On Thu, Sep 10, 2020 at 01:28:03PM +0300, Pekka Paalanen wrote:
On Thu, 10 Sep 2020 12:30:09 +0300 Laurentiu Palcu wrote:
On Thu, Sep 10, 2020 at 11:50:26AM +0300, Pekka Paalanen wrote:
On Thu, 10 Sep 2020 09:52:26 +0200 Daniel
Do calculation of vsync and hsync from range limits
EDID block according to the spec. EDID 1.4.
Signed-off-by: Vitaly Prosyak
---
drivers/gpu/drm/drm_edid.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm
Cache in drm connector the edid range limits properties:
min/max vertical refresh rates and max pixel clock.
It would be used when enter to drr mode.
Signed-off-by: Vitaly Prosyak
---
drivers/gpu/drm/drm_edid.c | 11 +++
include/drm/drm_crtc.h | 5 +
2 files changed, 16
12 matches
Mail list logo
