Hi Lucas,
Am Mittwoch, 6. April 2022, 18:01:22 CEST schrieb Lucas Stach:
> This adds the DT nodes for all the peripherals that make up the
> HDMI display pipeline.
>
> Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 80 +++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 6b7b5ba32b48..a41da99e9537 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1087,6 +1087,86 @@ irqsteer_hdmi: interrupt-controller@32fc2000 {
> clock-names = "ipg";
> power-domains = <&hdmi_blk_ctrl
IMX8MP_HDMIBLK_PD_IRQSTEER>;
> };
> +
> + hdmi_pvi: display-bridge@32fc4000 {
> + compatible = "fsl,imx8mp-hdmi-
pvi";
> + reg = <0x32fc4000 0x40>;
> + power-domains = <&hdmi_blk_ctrl
IMX8MP_HDMIBLK_PD_PVI>;
This should be disabled by default as well. Unless 'hdmi_tx: hdmi@32fd8000' is
enabled, this results in the warning:
imx-hdmi-pvi: probe of 32fc4000.display-bridge failed with error -22
Best regards
Alexander
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
pvi_from_lcdif3: endpoint {
> +
remote-endpoint = <&lcdif3_to_pvi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
pvi_to_hdmi_tx: endpoint {
> +
remote-endpoint = <&hdmi_tx_from_pvi>;
> + };
> + };
> + };
> + };
> +
> + lcdif3: display-controller@32fc6000 {
> + compatible = "fsl,imx8mp-lcdif";
> + reg = <0x32fc6000 0x238>;
> + interrupts = <8
IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent =
<&irqsteer_hdmi>;
> + clocks = <&hdmi_tx_phy>,
> + <&clk
IMX8MP_CLK_HDMI_APB>,
> + <&clk
IMX8MP_CLK_HDMI_ROOT>;
> + clock-names = "pix", "axi",
"disp_axi";
> + power-domains = <&hdmi_blk_ctrl
IMX8MP_HDMIBLK_PD_LCDIF>;
> +
> + port {
> + lcdif3_to_pvi: endpoint
{
> + remote-
endpoint = <&pvi_from_lcdif3>;
> + };
> + };
> + };
> +
> + hdmi_tx: hdmi@32fd8000 {
> + compatible = "fsl,imx8mp-hdmi";
> + reg = <0x32fd8000 0x7eff>;
> + interrupts = <0
IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent =
<&irqsteer_hdmi>;
> + clocks = <&clk
IMX8MP_CLK_HDMI_APB>,
> + <&clk
IMX8MP_CLK_HDMI_REF_266M>,
> + <&clk IMX8MP_CLK_32K>,
> + <&hdmi_tx_phy>;
> + clock-names = "iahb", "isfr",
"cec", "pix";
> + assigned-clocks = <&clk
IMX8MP_CLK_HDMI_REF_266M>;
> + assigned-clock-parents = <&clk
IMX8MP_SYS_PLL1_266M>;
> + power-domains = <&hdmi_blk_ctrl
IMX8MP_HDMIBLK_PD_HDMI_TX>;
> + reg-io-width = <1>;
> + status = "disabled";
> +
> + port {
> + hdmi_tx_from_pvi:
endpoint {
> + remote-
endpoint = <&pvi_to_hdmi_tx>;
> + };
> + };
> + };
> +
> + hdmi_tx_phy: phy@32fdff00 {
> + compatible = "fsl,imx8mp-hdmi-
phy";
> + reg = <0x32fdff00 0x100>;
> + clocks = <&clk
IMX8MP_CLK_HDMI_APB>,
> + <&clk
IMX8MP_CLK_HDMI_24M>;
> + clock-names = "apb", "ref";
> + assigned-clocks = <&clk
IMX8MP_CLK_HDMI_24M>;
> + assigned-clock-parents = <&clk
IMX8MP_CLK_24M>;
> + power-domains = <&hdmi_blk_ctrl
IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> };
>
> gpu3d: gpu@38000000 {
