Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-04 Thread Vinod Koul
On 02-05-22, 10:43, Marijn Suijten wrote: > On 2022-05-02 01:44:20, Dmitry Baryshkov wrote: > that require DSC for the screen to work. I've been told the series > didn't result in positive screen output way back in its infancy, but I would be intrested to hear about that. I have only pixel3 at

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-04 Thread Vinod Koul
On 30-04-22, 20:55, Dmitry Baryshkov wrote: > The downstream uses read-modify-write for updating command mode > compression registers. Let's follow this approach. This also fixes the > following warning: > > drivers/gpu/drm/msm/dsi/dsi_host.c:918:23: warning: variable 'reg_ctrl' set > but not

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-02 Thread Marijn Suijten
On 2022-05-02 13:02:09, Dmitry Baryshkov wrote: > [snip] > > How would you represent this in XML? I was hoping for a method that > > allows to construct the value in a generic way, without register names, > > and then simply have a "register macro" that moves (and perhaps masks) > > the

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-02 Thread Dmitry Baryshkov
On 02/05/2022 11:34, Marijn Suijten wrote: On 2022-05-01 16:56:45, Abhinav Kumar wrote: [snip] Wouln't this macro already make sure that 'reg' doesnt have anything in the top 16 bits? Its doing a & with 0x3f00 Like I said, it is unlikely that this happens, only if someone starts changing

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-02 Thread Marijn Suijten
On 2022-05-01 16:56:45, Abhinav Kumar wrote: > [snip] > Wouln't this macro already make sure that 'reg' doesnt have anything in > the top 16 bits? Its doing a & with 0x3f00 Like I said, it is unlikely that this happens, only if someone starts changing the code that assigns to `reg` which is

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-02 Thread Dmitry Baryshkov
On Mon, 2 May 2022 at 02:56, Abhinav Kumar wrote: > > > > On 5/1/2022 1:06 PM, Marijn Suijten wrote: > > On 2022-04-30 12:25:57, Abhinav Kumar wrote: > >> > >> > >> On 4/30/2022 11:58 AM, Marijn Suijten wrote: > >>> On 2022-04-30 20:55:33, Dmitry Baryshkov wrote: > The downstream uses

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-01 Thread Abhinav Kumar
On 5/1/2022 1:06 PM, Marijn Suijten wrote: On 2022-04-30 12:25:57, Abhinav Kumar wrote: On 4/30/2022 11:58 AM, Marijn Suijten wrote: On 2022-04-30 20:55:33, Dmitry Baryshkov wrote: The downstream uses read-modify-write for updating command mode compression registers. Let's follow this

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-05-01 Thread Marijn Suijten
On 2022-04-30 12:25:57, Abhinav Kumar wrote: > > > On 4/30/2022 11:58 AM, Marijn Suijten wrote: > > On 2022-04-30 20:55:33, Dmitry Baryshkov wrote: > >> The downstream uses read-modify-write for updating command mode > >> compression registers. Let's follow this approach. This also fixes the >

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing

2022-04-30 Thread Abhinav Kumar
On 4/30/2022 11:58 AM, Marijn Suijten wrote: On 2022-04-30 20:55:33, Dmitry Baryshkov wrote: The downstream uses read-modify-write for updating command mode compression registers. Let's follow this approach. This also fixes the following warning: drivers/gpu/drm/msm/dsi/dsi_host.c:918:23: