Re: [Intel-gfx] [PATCH v4 2/3] drm/i915: use pat_index instead of cache_level

On 03/05/2023 21:39, Yang, Fei wrote: [...] diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index 8c70a0ec7d2f..27c948350b5b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -54,6

RE: [Intel-gfx] [PATCH v4 2/3] drm/i915: use pat_index instead of cache_level

[...] >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c >> b/drivers/gpu/drm/i915/gem/i915_gem_object.c >> index 8c70a0ec7d2f..27c948350b5b 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c >> @@ -54,6 +54,25 @@ unsigned int i9

Re: [Intel-gfx] [PATCH v4 2/3] drm/i915: use pat_index instead of cache_level

On 02/05/2023 05:11, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. I