On 28/09/16 14:43, Bartosz Golaszewski wrote:
> how far is far enough to emit a warning? On da850 the requested rate
> is 22800 Hz, while the calculated divider is 6, which results in
> the real rate of 22500 Hz. This is less than 1% difference -
> should we take this value as reference?
Hi,
On 27/09/16 18:29, Bartosz Golaszewski wrote:
> Some architectures don't use the common clock framework and don't
> implement all the clk interfaces for every clock. This is the case
> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
>
> Trying to set the clock rate for the
On 09/27/16 18:29, Bartosz Golaszewski wrote:
> Some architectures don't use the common clock framework and don't
> implement all the clk interfaces for every clock. This is the case
> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
>
> Trying to set the clock rate for the LCDC
+ Sekhar
2016-09-28 13:19 GMT+02:00 Tomi Valkeinen :
> Hi,
>
> On 27/09/16 18:29, Bartosz Golaszewski wrote:
>> Some architectures don't use the common clock framework and don't
>> implement all the clk interfaces for every clock. This is the case
>> for da850-lcdk where clk_set_rate() only works
Some architectures don't use the common clock framework and don't
implement all the clk interfaces for every clock. This is the case
for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
Trying to set the clock rate for the LCDC clock results in -EINVAL
being returned.
As a
