Hi Laurent,
there are a few things currently in-flight for DU on my side:
- non-DPLL channel clock source selction
- ESCR/OTAR handling for non-DPLL channel
Before taking those two functional changes series into account,
could you include these three cosmetic changes in your tree?
Patches based on your drm/du/next branch, with the following patch applied on
top:
'01449a9779b8 (" drm: rcar-du: Rework clock configuration based on hardware
limits")'
Tested on Salvator-X M3-W with kms-modes-tests.py: no functional changes
Thanks
j
Jacopo Mondi (3):
drm: rcar-du: Rename and document dpll_ch field
drm: rcar-du: Write ESCR register per channel
drm: rcar-du: Write OTAR register per channel
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 7 +++----
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 6 +++---
drivers/gpu/drm/rcar-du/rcar_du_drv.h | 3 ++-
drivers/gpu/drm/rcar-du/rcar_du_regs.h | 8 ++++----
4 files changed, 12 insertions(+), 12 deletions(-)
--
2.7.4
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