[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-10-08 Thread Peter De Schrijver
On Mon, Sep 22, 2014 at 12:11:54PM +0200, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Mon, Sep 22, 2014 at 11:00:56AM +0200, Lucas Stach wrote: > > Am Freitag, den 19.09.2014, 15:53 -0400 schrieb Sean Paul: > > > Per NVidia, this clock rate should be around 70MHz in > > > order

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-10-08 Thread Sean Paul
On Wed, Oct 8, 2014 at 8:11 AM, Peter De Schrijver wrote: > On Mon, Sep 22, 2014 at 12:11:54PM +0200, Thierry Reding wrote: >> * PGP Signed by an unknown key >> >> On Mon, Sep 22, 2014 at 11:00:56AM +0200, Lucas Stach wrote: >> > Am Freitag, den 19.09.2014, 15:53 -0400 schrieb Sean Paul: >> > >

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-29 Thread Thierry Reding
On Sat, Sep 27, 2014 at 01:05:32PM -0700, Mike Turquette wrote: > Quoting Thierry Reding (2014-09-23 00:22:05) > > On Mon, Sep 22, 2014 at 06:46:52PM +0100, Mark Rutland wrote: > > > On Fri, Sep 19, 2014 at 08:53:48PM +0100, Sean Paul wrote: > > > > Per NVidia, this clock rate should be around

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-27 Thread Mike Turquette
Quoting Thierry Reding (2014-09-23 00:22:05) > On Mon, Sep 22, 2014 at 06:46:52PM +0100, Mark Rutland wrote: > > On Fri, Sep 19, 2014 at 08:53:48PM +0100, Sean Paul wrote: > > > Per NVidia, this clock rate should be around 70MHz in > > > order to properly sample reads on data lane 0. In order > >

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-23 Thread Thierry Reding
On Mon, Sep 22, 2014 at 06:46:52PM +0100, Mark Rutland wrote: > On Fri, Sep 19, 2014 at 08:53:48PM +0100, Sean Paul wrote: > > Per NVidia, this clock rate should be around 70MHz in > > order to properly sample reads on data lane 0. In order > > to achieve this rate, we need to reparent the clock

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-22 Thread Mark Rutland
On Fri, Sep 19, 2014 at 08:53:48PM +0100, Sean Paul wrote: > Per NVidia, this clock rate should be around 70MHz in > order to properly sample reads on data lane 0. In order > to achieve this rate, we need to reparent the clock from > clk_m which can only achieve 12MHz. Add parent_lp to the > dts

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-22 Thread Thierry Reding
On Mon, Sep 22, 2014 at 11:00:56AM +0200, Lucas Stach wrote: > Am Freitag, den 19.09.2014, 15:53 -0400 schrieb Sean Paul: > > Per NVidia, this clock rate should be around 70MHz in > > order to properly sample reads on data lane 0. In order > > to achieve this rate, we need to reparent the clock

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-22 Thread Thierry Reding
On Fri, Sep 19, 2014 at 03:53:48PM -0400, Sean Paul wrote: > Per NVidia, this clock rate should be around 70MHz in > order to properly sample reads on data lane 0. Can you point out where you get 70 MHz from? I only see the TRM mention 72 MHz that are needed for calibration. Also, what's the

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-22 Thread Lucas Stach
Am Freitag, den 19.09.2014, 15:53 -0400 schrieb Sean Paul: > Per NVidia, this clock rate should be around 70MHz in > order to properly sample reads on data lane 0. In order > to achieve this rate, we need to reparent the clock from > clk_m which can only achieve 12MHz. Add parent_lp to the > dts

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-22 Thread Andrzej Hajda
Hi Sean, On 09/19/2014 09:53 PM, Sean Paul wrote: > Per NVidia, this clock rate should be around 70MHz in > order to properly sample reads on data lane 0. In order > to achieve this rate, we need to reparent the clock from > clk_m which can only achieve 12MHz. Add parent_lp to the > dts bindings

[PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate

2014-09-19 Thread Sean Paul
Per NVidia, this clock rate should be around 70MHz in order to properly sample reads on data lane 0. In order to achieve this rate, we need to reparent the clock from clk_m which can only achieve 12MHz. Add parent_lp to the dts bindings and set the parent & rate on init. Signed-off-by: Sean Paul