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Brandi B Gulbin
On Tue, Apr 25, 2017 at 03:01:35PM +0200, Christian König wrote:
> Am 12.04.2017 um 18:55 schrieb Bjorn Helgaas:
> >[SNIP]
> >>>I think the specs would envision this being done via an ACPI _SRS
> >>>method on the PNP0A03 host bridge device. That would be a more
> >>>generic path that would work on
On Tue, Apr 25, 2017 at 4:19 PM, Christian König
wrote:
> From: Christian König
>
> Most BIOS don't enable this because of compatibility reasons.
>
> Manually enable a 64bit BAR of 64GB size so that we have
> enough room for PCI devices.
> +static void pci_amd_enable_64bit_bar(struct pci_dev *de
On Tue, Apr 25, 2017 at 9:19 AM, Christian König
wrote:
> From: Christian König
>
> Most BIOS don't enable this because of compatibility reasons.
>
> Manually enable a 64bit BAR of 64GB size so that we have
> enough room for PCI devices.
>
> v2: style cleanups, increase size, add resource name, s
From: Christian König
Most BIOS don't enable this because of compatibility reasons.
Manually enable a 64bit BAR of 64GB size so that we have
enough room for PCI devices.
v2: style cleanups, increase size, add resource name, set correct flags,
print message that windows was added
Signed-off
Am 12.04.2017 um 18:55 schrieb Bjorn Helgaas:
[SNIP]
I think the specs would envision this being done via an ACPI _SRS
method on the PNP0A03 host bridge device. That would be a more
generic path that would work on any host bridge. Did you explore that
possibility? I would prefer to avoid addi
On Tue, Apr 11, 2017 at 05:48:25PM +0200, Christian König wrote:
> Am 24.03.2017 um 16:47 schrieb Bjorn Helgaas:
> >On Mon, Mar 13, 2017 at 01:41:35PM +0100, Christian König wrote:
> >>From: Christian König
> >>
> >>Most BIOS don't enable this because of compatibility reasons.
> >Can you give any
Am 24.03.2017 um 16:47 schrieb Bjorn Helgaas:
On Mon, Mar 13, 2017 at 01:41:35PM +0100, Christian König wrote:
From: Christian König
Most BIOS don't enable this because of compatibility reasons.
Can you give any more details here? Without more hints, it's hard to
know whether any of the comp
Am 13.03.2017 um 17:49 schrieb Andy Shevchenko:
On Mon, Mar 13, 2017 at 2:41 PM, Christian König
wrote:
Most BIOS don't enable this because of compatibility reasons.
Manually enable a 64bit BAR of 64GB size so that we have
enough room for PCI devices.
+static void pci_amd_enable_64bit_bar(str
On Mon, Mar 13, 2017 at 01:41:35PM +0100, Christian König wrote:
> From: Christian König
>
> Most BIOS don't enable this because of compatibility reasons.
Can you give any more details here? Without more hints, it's hard to
know whether any of the compatibility reasons might apply to Linux as
w
Hi Christian,
[auto build test WARNING on pci/next]
[also build test WARNING on v4.11-rc2 next-20170310]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Christian-K-nig/PCI-add-resizeable-BAR-inf
On Mon, Mar 13, 2017 at 2:41 PM, Christian König
wrote:
> Most BIOS don't enable this because of compatibility reasons.
>
> Manually enable a 64bit BAR of 64GB size so that we have
> enough room for PCI devices.
> +static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
> +{
> + const ui
From: Christian König
Most BIOS don't enable this because of compatibility reasons.
Manually enable a 64bit BAR of 64GB size so that we have
enough room for PCI devices.
Signed-off-by: Christian König
---
arch/x86/pci/fixup.c | 53
1 file c
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