It requires i915 changes to add end_cpu_access().
Signed-off-by: Tiago Vignatti <tiago.vignatti at intel.com>
---
tests/kms_mmap_write_crc.c | 63 ++++++++++++++++++++++++++++++++++++++++------
1 file changed, 55 insertions(+), 8 deletions(-)
diff --git a/tests/kms_mmap_write_crc.c b/tests/kms_mmap_write_crc.c
index e24d535..59ac9e7 100644
--- a/tests/kms_mmap_write_crc.c
+++ b/tests/kms_mmap_write_crc.c
@@ -67,6 +67,24 @@ static char *dmabuf_mmap_framebuffer(int drm_fd, struct
igt_fb *fb)
return ptr;
}
+static void dmabuf_sync_start(void)
+{
+ struct dma_buf_sync sync_start;
+
+ memset(&sync_start, 0, sizeof(sync_start));
+ sync_start.flags = DMA_BUF_SYNC_START | DMA_BUF_SYNC_RW;
+ do_ioctl(dma_buf_fd, DMA_BUF_IOCTL_SYNC, &sync_start);
+}
+
+static void dmabuf_sync_end(void)
+{
+ struct dma_buf_sync sync_end;
+
+ memset(&sync_end, 0, sizeof(sync_end));
+ sync_end.flags = DMA_BUF_SYNC_END | DMA_BUF_SYNC_RW;
+ do_ioctl(dma_buf_fd, DMA_BUF_IOCTL_SYNC, &sync_end);
+}
+
static void test_begin_access(data_t *data)
{
igt_display_t *display = &data->display;
@@ -103,14 +121,11 @@ static void test_begin_access(data_t *data)
caching = gem_get_caching(data->drm_fd, fb->gem_handle);
igt_assert(caching == I915_CACHING_NONE || caching ==
I915_CACHING_DISPLAY);
- // Uncomment the following for flush and the crc check next passes. It
- // requires the kernel counter-part of it implemented obviously.
- // {
- // struct dma_buf_sync sync_start;
- // memset(&sync_start, 0, sizeof(sync_start));
- // sync_start.flags = DMA_BUF_SYNC_START | DMA_BUF_SYNC_RW;
- // do_ioctl(dma_buf_fd, DMA_BUF_IOCTL_SYNC, &sync_start);
- // }
+ /*
+ * firstly demonstrate the need for DMA_BUF_SYNC_START
("begin_cpu_access")
+ */
+
+ dmabuf_sync_start();
/* use dmabuf pointer to make the other fb all white too */
buf = malloc(fb->size);
@@ -126,6 +141,38 @@ static void test_begin_access(data_t *data)
/* check that the crc is as expected, which requires that caches got
flushed */
igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
igt_assert_crc_equal(&crc, &data->ref_crc);
+
+ /*
+ * now demonstrates the need for DMA_BUF_SYNC_END ("end_cpu_access")
+ */
+
+ /* start over, writing non-white to the fb again and flip to it to make
it
+ * fully flushed */
+ cr = igt_get_cairo_ctx(data->drm_fd, fb);
+ igt_paint_test_pattern(cr, fb->width, fb->height);
+ cairo_destroy(cr);
+
+ igt_plane_set_fb(data->primary, fb);
+ igt_display_commit(display);
+
+ /* sync start, to move to CPU domain */
+ dmabuf_sync_start();
+
+ /* use dmabuf pointer in the same fb to make it all white */
+ buf = malloc(fb->size);
+ igt_assert(buf != NULL);
+ memset(buf, 0xff, fb->size);
+ memcpy(ptr, buf, fb->size);
+ free(buf);
+
+ /* there's an implicit flush in set_fb() as well (to set to the GTT
domain),
+ * so if we don't do it and instead write directly into the fb as it is
the
+ * scanout, that should demonstrate the need for end_cpu_access */
+ dmabuf_sync_end();
+
+ /* check that the crc is as expected, which requires that caches got
flushed */
+ igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
+ igt_assert_crc_equal(&crc, &data->ref_crc);
}
static bool prepare_crtc(data_t *data)
--
2.1.0
