Ah Thanks for the great feedback!
@Lucas or @Matt, could you please chime in?
Michael Cheng
On 2022-03-02 11:10 a.m., Robin Murphy wrote:
On 2022-03-02 15:55, Michael Cheng wrote:
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to
understand
On 2022-03-02 15:55, Michael Cheng wrote:
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to
understand how ARM flushes a range of dcache for device drivers, and not
an equal to x86 clflush.
I believe the concern is if the CPU writes an
On Wed, Mar 2, 2022 at 10:55 AM Michael Cheng wrote:
>
> Thanks for the feedback Robin!
>
> Sorry my choices of word weren't that great, but what I meant is to
> understand how ARM flushes a range of dcache for device drivers, and not
> an equal to x86 clflush.
>
> I believe the concern is if the
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to
understand how ARM flushes a range of dcache for device drivers, and not
an equal to x86 clflush.
I believe the concern is if the CPU writes an update, that update might
only be sitting in the
On 2022-02-25 19:27, Michael Cheng wrote:
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good
thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them
in sooner.
Why does i915 need to ensure the CPU's instruction
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good
thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them
in sooner.
Why does i915 need to ensure the CPU's instruction cache is coherent
with its data cache? Is it
On Fri, Feb 25, 2022 at 06:42:37PM +, Tvrtko Ursulin wrote:
> Matthew, what do you think fix for this build warning on h8300 and s390
> should be? Or perhaps a build environment issue with kernel test robot?
I'd suggest this should do the job:
+++ b/include/linux/cacheflush.h
@@ -4,6 +4,8
On 25/02/2022 18:23, Michael Cheng wrote:
These seem to be pretty old arch and are day0 warnings, please refer to
[1] to see the warnings. Also I am not sure why my patch series didn't
append to the old one.
[1] https://patchwork.freedesktop.org/patch/475829/?series=99450=11
[ +arm64 maintainers for their awareness, which would have been a good
thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
performs a flush by first performing a clean, follow by an invalidation
operation.
These seem to be pretty old arch and are day0 warnings, please refer to
[1] to see the warnings. Also I am not sure why my patch series didn't
append to the old one.
[1] https://patchwork.freedesktop.org/patch/475829/?series=99450=11
2022-02-25 10:19 a.m., Tvrtko Ursulin wrote:
On
On 25/02/2022 17:40, Michael Cheng wrote:
Ah, thanks for pointing that out, when I do include it though, it causes
a few warning other systems such as h8300 and s390.
Errors look like? I haven't heard that kernel code is not allowed to
include something from linux/ on some arch yet.
Since
Ah, thanks for pointing that out, when I do include it though, it causes
a few warning other systems such as h8300 and s390.
Since it is already pulled is, would it be OK to leave it out for this
case? Or we could use something like !IS_H8300 and !IS_S390
around the header file?
On
On 25/02/2022 16:52, Michael Cheng wrote:
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or
x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \
./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or
x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \
./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \
./.drm_cache.o.cmd:920: include/asm-generic/cacheflush.h \
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache. Thanks Tvrtko for the suggestion.
v3
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