From: Jernej Skrabec
Some SoCs with DW HDMI have multiple possible clock parents, like A64
and R40.
Expand HDMI PHY clock driver to support second clock parent.
Signed-off-by: Jernej Skrabec
Signed-off-by: Jagan Teki
---
Changes for v2:
- new patch
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
Hi, guys,
On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
From: Jernej Skrabec
Some SoCs with DW HDMI have multiple possible clock parents, like A64
and R40.
Hi, Jernej,
On 05/18/2018 06:15 PM, Jernej Škrabec wrote:
Hi,
Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
Hi, guys,
On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
On Fri, May 18, 2018 at 03:1
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is highly unlikely this will be higher than
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is highly unlikely this will be higher than
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> > From: Jernej Skrabec
> >
> > Some SoCs with DW HDMI have multiple possible clock parents, like A64
> > and R40.
> >
> > Expand HDMI PHY clock driver to sup
Hi,
Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
> Hi, guys,
>
> On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> >> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> >>> Fro
On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > lookup pll-2 either.
>
> It is highly unlikely this will be higher than 2, at least for this HDMI PHY,
> since it has only 1 bit reserved for parent select
On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> From: Jernej Skrabec
>
> Some SoCs with DW HDMI have multiple possible clock parents, like A64
> and R40.
>
> Expand HDMI PHY clock driver to support second clock parent.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Jagan Teki