On Thu, Nov 19, 2020 at 11:14:50AM +, Dave Stevenson wrote:
> Hi Maxime
>
> Thanks for the rewording :-)
>
> On Thu, 29 Oct 2020 at 12:25, Maxime Ripard wrote:
> >
> > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > per clock cycle, and cannot deal with odd timin
Hi Maxime
Thanks for the rewording :-)
On Thu, 29 Oct 2020 at 12:25, Maxime Ripard wrote:
>
> The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> per clock cycle, and cannot deal with odd timings.
>
> Let's reject any mode with such timings.
>
> Signed-off-by: Maxime Ripar
The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
per clock cycle, and cannot deal with odd timings.
Let's reject any mode with such timings.
Signed-off-by: Maxime Ripard
---
Changes from v1:
- s/broken/unsupported/
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 12
