[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

Dear Daniel, On Wed, 18 Mar 2015 09:52:33 + Daniel Stone wrote: > Hi, > > On 18 March 2015 at 08:16, Hyungwon Hwang > wrote: > > +#define REG(dsi, reg) ((dsi)->reg_base + > > dsi->driver_data->regs[(reg)]) > > This seems like a good change in general, but please split it up: it > makes b

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

Dear Andrej, On Mon, 23 Mar 2015 10:31:58 +0100 Andrzej Hajda wrote: > On 03/20/2015 06:15 AM, Hyungwon Hwang wrote: > > Dear Andrej, > > > > On Thu, 19 Mar 2015 10:32:10 +0100 > > Andrzej Hajda wrote: > > > >> On 03/19/2015 02:18 AM, Hyungwon Hwang wrote: > >>> Dear Daniel, > >>> > >>> On Thu,

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

On 03/20/2015 06:15 AM, Hyungwon Hwang wrote: > Dear Andrej, > > On Thu, 19 Mar 2015 10:32:10 +0100 > Andrzej Hajda wrote: > >> On 03/19/2015 02:18 AM, Hyungwon Hwang wrote: >>> Dear Daniel, >>> >>> On Thu, 19 Mar 2015 01:13:21 + >>> Daniel Stone wrote: >>> Hi Hyungwon, On 19 M

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

Dear Andrej, On Thu, 19 Mar 2015 10:32:10 +0100 Andrzej Hajda wrote: > On 03/19/2015 02:18 AM, Hyungwon Hwang wrote: > > Dear Daniel, > > > > On Thu, 19 Mar 2015 01:13:21 + > > Daniel Stone wrote: > > > >> Hi Hyungwon, > >> > >> On 19 March 2015 at 01:02, Hyungwon Hwang > >> wrote: > >>>

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

On 03/19/2015 02:18 AM, Hyungwon Hwang wrote: > Dear Daniel, > > On Thu, 19 Mar 2015 01:13:21 + > Daniel Stone wrote: > >> Hi Hyungwon, >> >> On 19 March 2015 at 01:02, Hyungwon Hwang >> >> wrote: > + /* > +* The input PLL clock for MIPI DSI in Exynos5433 seems >

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

On 03/19/2015 02:18 AM, Hyungwon Hwang wrote: > Dear Daniel, > > On Thu, 19 Mar 2015 01:13:21 + > Daniel Stone wrote: > >> Hi Hyungwon, >> >> On 19 March 2015 at 01:02, Hyungwon Hwang >> >> wrote: > + /* > +* The input PLL clock for MIPI DSI in Exynos5433 seems

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

Dear Daniel, On Thu, 19 Mar 2015 01:13:21 + Daniel Stone wrote: > Hi Hyungwon, > > On 19 March 2015 at 01:02, Hyungwon Hwang > wrote: > >> > + /* > >> > +* The input PLL clock for MIPI DSI in Exynos5433 seems > >> > to be fixed > >> > +* by OSC CLK. > >> > +*/

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

Dear Daniel, On Wed, 18 Mar 2015 09:52:33 + Daniel Stone wrote: > Hi, > > On 18 March 2015 at 08:16, Hyungwon Hwang > wrote: > > +#define REG(dsi, reg) ((dsi)->reg_base + > > dsi->driver_data->regs[(reg)]) > > This seems like a good change in general, but please split it up: it > makes b

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

Hi Hyungwon, On 19 March 2015 at 01:02, Hyungwon Hwang wrote: >> > + /* >> > +* The input PLL clock for MIPI DSI in Exynos5433 seems to >> > be fixed >> > +* by OSC CLK. >> > +*/ >> > + fin = 24 * MHZ; >> >> Er, is this always true on other platforms as well? S

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

This patch adds support for Exynos5433. The goal is achieved by 1. Getting the address of registers from driver data 2. Getting the fixed value for registers from driver data 3. Getting different number of clocks using driver data 4. Getting max frequency of pixel clock from driver data Signed-off

[PATCH v2 4/6] drm/exynos: dsi: add support for Exynos5433 SoC

Hi, On 18 March 2015 at 08:16, Hyungwon Hwang wrote: > +#define REG(dsi, reg) ((dsi)->reg_base + dsi->driver_data->regs[(reg)]) This seems like a good change in general, but please split it up: it makes bisection much easier if you have one patch which adds no functionality and should have exac