On Wed, 3 Jun 2020 at 19:53, Marek Olšák wrote:
> TMZ is more complicated. If there is a TMZ buffer used by a command buffer,
> then all other used buffers must also be TMZ or read only. If no TMZ buffers
> are used by a command buffer, then TMZ is disabled. If a context is not
> secure, TMZ is
TMZ is more complicated. If there is a TMZ buffer used by a command buffer,
then all other used buffers must also be TMZ or read only. If no TMZ
buffers are used by a command buffer, then TMZ is disabled. If a context is
not secure, TMZ is also disabled. A context can switch between secure and
non-
Hi Alex,
On Mon, 1 Jun 2020 at 15:25, Alex Deucher wrote:
> On Fri, May 29, 2020 at 11:03 AM Daniel Stone wrote:
> > What Weston _does_ know, however, is that display controller can work
> > with modifier set A, and the GPU can work with modifier set B, and if
> > the client can pick something f
On Fri, May 29, 2020 at 11:03 AM Daniel Stone wrote:
>
> On Fri, 29 May 2020 at 15:36, Alex Deucher wrote:
> > On Fri, May 29, 2020 at 10:32 AM Daniel Stone wrote:
> > > On Fri, 29 May 2020 at 15:29, Alex Deucher wrote:
> > > > Maybe I'm over thinking this. I just don't want to get into a
> >
On 29/05/2020 15:56, Daniel Stone wrote:
> Hi Alex,
>
> On Fri, 29 May 2020 at 14:29, Alex Deucher wrote:
>> On Fri, May 29, 2020 at 4:59 AM Simon Ser wrote:
>>> OK. In this case I think it's fine to make the DMA-BUF import fail, as
>>> we've suggested on IRC. The more-or-less planned fix for th
Sorry for commenting on the obsolete v1 - that'll teach me for reading
my backlog chronologically.
On Thu, May 28, 2020 at 02:38:36PM +, Simon Ser wrote:
> There have suggestions to bake pitch alignment, address alignement,
> contiguous memory or other placement (hidden VRAM, GTT/BAR, etc)
> c
On 2020-05-29 5:01 p.m., Daniel Stone wrote:
> On Fri, 29 May 2020 at 15:36, Alex Deucher wrote:
>> On Fri, May 29, 2020 at 10:32 AM Daniel Stone wrote:
>>> On Fri, 29 May 2020 at 15:29, Alex Deucher wrote:
Maybe I'm over thinking this. I just don't want to get into a
situation where
On Fri, May 29, 2020 at 11:03 AM Daniel Stone wrote:
>
> On Fri, 29 May 2020 at 15:36, Alex Deucher wrote:
> > On Fri, May 29, 2020 at 10:32 AM Daniel Stone wrote:
> > > On Fri, 29 May 2020 at 15:29, Alex Deucher wrote:
> > > > Maybe I'm over thinking this. I just don't want to get into a
> >
On Fri, 29 May 2020 at 15:36, Alex Deucher wrote:
> On Fri, May 29, 2020 at 10:32 AM Daniel Stone wrote:
> > On Fri, 29 May 2020 at 15:29, Alex Deucher wrote:
> > > Maybe I'm over thinking this. I just don't want to get into a
> > > situation where we go through a lot of effort to add modifier
On Fri, May 29, 2020 at 10:32 AM Daniel Stone wrote:
>
> On Fri, 29 May 2020 at 15:29, Alex Deucher wrote:
> > Maybe I'm over thinking this. I just don't want to get into a
> > situation where we go through a lot of effort to add modifier support
> > and then performance ends up being worse than
On Fri, 29 May 2020 at 15:29, Alex Deucher wrote:
> Maybe I'm over thinking this. I just don't want to get into a
> situation where we go through a lot of effort to add modifier support
> and then performance ends up being worse than it is today in a lot of
> cases.
I'm genuinely curious: what d
On Fri, May 29, 2020 at 9:58 AM Daniel Stone wrote:
>
> Hi Alex,
>
> On Fri, 29 May 2020 at 14:29, Alex Deucher wrote:
> > On Fri, May 29, 2020 at 4:59 AM Simon Ser wrote:
> > > OK. In this case I think it's fine to make the DMA-BUF import fail, as
> > > we've suggested on IRC. The more-or-less
Hi Alex,
On Fri, 29 May 2020 at 14:29, Alex Deucher wrote:
> On Fri, May 29, 2020 at 4:59 AM Simon Ser wrote:
> > OK. In this case I think it's fine to make the DMA-BUF import fail, as
> > we've suggested on IRC. The more-or-less planned fix for these buffer
> > sharing issues is to revive the b
On Fri, May 29, 2020 at 3:29 PM Alex Deucher wrote:
>
> On Fri, May 29, 2020 at 4:59 AM Simon Ser wrote:
> >
> > On Thursday, May 28, 2020 5:49 PM, Marek Olšák wrote:
> >
> > > On most hardware, there is a minimum pitch alignment for linear and
> > > any greater multiple of the alignment is fine
On Fri, May 29, 2020 at 4:59 AM Simon Ser wrote:
>
> On Thursday, May 28, 2020 5:49 PM, Marek Olšák wrote:
>
> > On most hardware, there is a minimum pitch alignment for linear and
> > any greater multiple of the alignment is fine.
> >
> > On Navi, the pitch in bytes for linear must be
> > align(
On Thursday, May 28, 2020 5:49 PM, Marek Olšák wrote:
> On most hardware, there is a minimum pitch alignment for linear and
> any greater multiple of the alignment is fine.
>
> On Navi, the pitch in bytes for linear must be
> align(width * bpp / 8, 256). That's because the hw computes the pitch
>
On most hardware, there is a minimum pitch alignment for linear and any
greater multiple of the alignment is fine.
On Navi, the pitch in bytes for linear must be align(width * bpp / 8, 256).
That's because the hw computes the pitch from the width and doesn't allow
setting a custom pitch. For that
There have suggestions to bake pitch alignment, address alignement,
contiguous memory or other placement (hidden VRAM, GTT/BAR, etc)
constraints into modifiers. Last time this was brought up it seemed
like the consensus was to not allow this. Document this in drm_fourcc.h.
There are several reason
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