From: Thierry Reding <tred...@nvidia.com>

The polarities of the V- and H-sync signals are encoded as flags in the
display mode, so use the existing information to setup the signals for
the RGB interface.

Signed-off-by: Thierry Reding <tred...@nvidia.com>
Cc: Thierry Reding <thierry.red...@gmail.com>
[tomi.valkei...@ideasonboard.com: default to positive sync]
Reviewed-by: Peter Ujfalusi <peter.ujfal...@gmail.com>
Signed-off-by: Tomi Valkeinen <tomi.valkei...@ideasonboard.com>
---
 drivers/gpu/drm/tegra/rgb.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index 79566c9ea8ff..fc66bbd913b2 100644
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -99,6 +99,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder 
*encoder)
 
 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
 {
+       struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
        struct tegra_output *output = encoder_to_output(encoder);
        struct tegra_rgb *rgb = to_rgb(output);
        u32 value;
@@ -108,10 +109,19 @@ static void tegra_rgb_encoder_enable(struct drm_encoder 
*encoder)
        value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
        tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
 
-       /* XXX: parameterize? */
+       /* configure H- and V-sync signal polarities */
        value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
-       value &= ~LVS_OUTPUT_POLARITY_LOW;
-       value &= ~LHS_OUTPUT_POLARITY_LOW;
+
+       if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+               value |= LHS_OUTPUT_POLARITY_LOW;
+       else
+               value &= ~LHS_OUTPUT_POLARITY_LOW;
+
+       if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+               value |= LVS_OUTPUT_POLARITY_LOW;
+       else
+               value &= ~LVS_OUTPUT_POLARITY_LOW;
+
        tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
 
        /* XXX: parameterize? */

-- 
2.34.1

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