Now that non-masked registers are already read before programming the
context reads, the additional read became redudant, so remove it.
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0a9c3be4817c..b07f84c3fa21 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -637,10 +637,7 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
struct i915_wa_list *wal)
{
/* Wa_1406697149 (WaDisableBankHangMode:icl) */
- wa_write(wal,
- GEN8_L3CNTLREG,
- intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
- GEN8_ERRDETBCTRL);
+ wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
/* WaForceEnableNonCoherent:icl
* This is not the same workaround as in early Gen9 platforms, where
--
2.40.1
