On Thu, Mar 21, 2019 at 07:40:32PM +0530, Jagan Teki wrote:
> On Tue, Mar 19, 2019 at 4:23 PM Maxime Ripard
> wrote:
> >
> > On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
> > > On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard
> > > wrote:
> > > >
> > > > On Mon, Mar 11, 2019 at
Hi Maxime,
On Thu, Mar 21, 2019 at 7:40 PM Jagan Teki wrote:
>
> On Tue, Mar 19, 2019 at 4:23 PM Maxime Ripard
> wrote:
> >
> > On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
> > > On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard
> > > wrote:
> > > >
> > > > On Mon, Mar 11, 2019 at
Hi Sergey,
On Tue, Mar 19, 2019 at 5:47 PM Sergey Suloev wrote:
>
> Hi, guys,
>
> On 3/19/19 1:53 PM, Maxime Ripard wrote:
>
> On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
>
> On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard
> wrote:
>
> On Mon, Mar 11, 2019 at 07:06:24PM +0530,
On Tue, Mar 19, 2019 at 4:23 PM Maxime Ripard wrote:
>
> On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
> > On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard
> > wrote:
> > >
> > > On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
> > > > pll-video => pll-mipi => tcon0 =>
Hi, guys,
On 3/19/19 1:53 PM, Maxime Ripard wrote:
On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard wrote:
On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
On Mon, Mar 11, 2019 at 09:36:27PM +0530, Jagan Teki wrote:
> On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard
> wrote:
> >
> > On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
> > > pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
> > > MIPI clock topology in Allwinner
On Mon, Mar 11, 2019 at 9:36 PM Jagan Teki wrote:
>
> On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard
> wrote:
> >
> > On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
> > > pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
> > > MIPI clock topology in Allwinner DSI
On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard wrote:
>
> On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
> > pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
> > MIPI clock topology in Allwinner DSI controller.
> >
> > TCON dotclock driver is computing the desired
On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
> pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
> MIPI clock topology in Allwinner DSI controller.
>
> TCON dotclock driver is computing the desired DCLK divider based on
> panel pixel clock along with input DCLK
pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
MIPI clock topology in Allwinner DSI controller.
TCON dotclock driver is computing the desired DCLK divider based on
panel pixel clock along with input DCLK min, max divider values from
tcon driver and that would eventually set
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