On Wed, Sep 13, 2023 at 02:43:43PM -0700, Jessica Zhang wrote:
> Hi John,
>
> Just curious, what do you mean by these registers being mostly unknown?
>
> I do see them specified in the online specs -- some even seem to map to
> existing MIPI_DCS_* enums (ex. 0x01 to MIPI_DCS_SOFT_RESET, and 0x04
On 9/13/2023 9:12 PM, John Watts wrote:
On Wed, Sep 13, 2023 at 02:43:43PM -0700, Jessica Zhang wrote:
Hi John,
Just curious, what do you mean by these registers being mostly unknown?
I do see them specified in the online specs -- some even seem to map to
existing MIPI_DCS_* enums (ex.
On 9/11/2023 2:01 AM, John Watts wrote:
Many of these registers have a known name in the public datasheet.
Document them as comments for reference.
Signed-off-by: John Watts
---
.../gpu/drm/panel/panel-newvision-nv3052c.c | 261 +-
1 file changed, 132 insertions(+), 129
Many of these registers have a known name in the public datasheet.
Document them as comments for reference.
Signed-off-by: John Watts
---
.../gpu/drm/panel/panel-newvision-nv3052c.c | 261 +-
1 file changed, 132 insertions(+), 129 deletions(-)
diff --git
