Hi Laurent,
On Fri, 2019-11-08 at 09:13:25 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> (CC'ing Daniel, with a question for him below)
>
> On Fri, Sep 27, 2019 at 05:04:57PM -0700, Hyun Kwon wrote:
> > On Wed, 2019-09-25 at 16:55:42 -0700, Laurent Pinchart wrote:
> > > From: Hyun Kwon
> > >
Hi Hyun,
(CC'ing Daniel, with a question for him below)
On Fri, Sep 27, 2019 at 05:04:57PM -0700, Hyun Kwon wrote:
> On Wed, 2019-09-25 at 16:55:42 -0700, Laurent Pinchart wrote:
> > From: Hyun Kwon
> >
> > The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort
> > Subsystem.
Hi Laurent,
Thanks for the patch.
On Wed, 2019-09-25 at 16:55:42 -0700, Laurent Pinchart wrote:
> From: Hyun Kwon
>
> The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort
> Subsystem. It includes a buffer manager, a video pipeline renderer
> (blender), an audio mixer and a
