13.10.2014, 21:50, "Alex Deucher" :
> On Fri, Oct 10, 2014 at 12:00 PM, Alex Deucher
> wrote:
>> ?I think I'd prefer to just switch the test to use gart memory since
>> ?this code is shared by different asics thay may not all implement hdp
>> ?flush the same way. ?We can just reserve a couple of
On Fri, Oct 10, 2014 at 12:00 PM, Alex Deucher wrote:
> On Thu, Oct 9, 2014 at 3:10 PM, Alexander Fyodorov wrote:
>> 09.10.2014, 22:32, "Christian K?nig" :
>>> Am 09.10.2014 um 20:15 schrieb Alexander Fyodorov:
09.10.2014, 21:42, "Christian K?nig" :
> For VRAM it is true that we have
Am 10.10.2014 um 18:02 schrieb Alex Deucher:
> On Fri, Oct 10, 2014 at 12:00 PM, Alex Deucher
> wrote:
>> On Thu, Oct 9, 2014 at 3:10 PM, Alexander Fyodorov
>> wrote:
>>> 09.10.2014, 22:32, "Christian K?nig" :
Am 09.10.2014 um 20:15 schrieb Alexander Fyodorov:
> 09.10.2014, 21:42,
On Fri, Oct 10, 2014 at 12:00 PM, Alex Deucher wrote:
> On Thu, Oct 9, 2014 at 3:10 PM, Alexander Fyodorov wrote:
>> 09.10.2014, 22:32, "Christian K?nig" :
>>> Am 09.10.2014 um 20:15 schrieb Alexander Fyodorov:
09.10.2014, 21:42, "Christian K?nig" :
> For VRAM it is true that we have
On Thu, Oct 9, 2014 at 3:10 PM, Alexander Fyodorov wrote:
> 09.10.2014, 22:32, "Christian K?nig" :
>> Am 09.10.2014 um 20:15 schrieb Alexander Fyodorov:
>>> 09.10.2014, 21:42, "Christian K?nig" :
For VRAM it is true that we have a couple of different caches between
the CPU and the
09.10.2014, 22:32, "Christian K?nig" :
> Am 09.10.2014 um 20:15 schrieb Alexander Fyodorov:
>> ?09.10.2014, 21:42, "Christian K?nig" :
>>> ?For VRAM it is true that we have a couple of different caches between
>>> ?the CPU and the actually memory, which need to be flushed explicitly if
>>> ?you
09.10.2014, 21:42, "Christian K?nig" :
> Hi Alexander,
>
> in the ring test we write the value 0xDEADBEEF and 0xCAFEDEAD into
> registers, not VRAM.
>
> And the register bar shouldn't be accessed write combined, cause that
> could lead to a couple of ordering problems. Why do you think the access
Am 09.10.2014 um 20:15 schrieb Alexander Fyodorov:
> 09.10.2014, 21:42, "Christian K?nig" :
>> Hi Alexander,
>>
>> in the ring test we write the value 0xDEADBEEF and 0xCAFEDEAD into
>> registers, not VRAM.
>>
>> And the register bar shouldn't be accessed write combined, cause that
>> could lead to
Hi Alexander,
in the ring test we write the value 0xDEADBEEF and 0xCAFEDEAD into
registers, not VRAM.
And the register bar shouldn't be accessed write combined, cause that
could lead to a couple of ordering problems. Why do you think the access
is done write combined?
For VRAM it is true
Hi David,
I'm using 3.10.53-rt56 kernel and encounter a problem in
r600_dma_ring_test() when vram memory is mapped as write-combining:
no matter how long the polling is done, old value (0xCAFEDEAD) is read.
Looking with hardware analyzer at what actually happens in the PCI-E bus,
the memory is
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