Re: [PATCH] drm/i915: Remove redundant user_access_end() from __copy_from_user() error path
On Fri, 9 Aug 2019, Sedat Dilek wrote: > On Fri, Aug 9, 2019 at 1:03 AM Nick Desaulniers > wrote: > > > > On Thu, Aug 8, 2019 at 1:22 PM Thomas Gleixner wrote: > > > > tglx just picked up 2 other patches of mine, bumping just in case he's > > > > not picking up patches while on vacation. ;) > > > > > > I'm only half on vacation :) > > > > > > So I can pick it up. > > > > Thanks, will send half margaritas. > > > > Sends some Turkish Cay. One day, I'm going to collect all the things people promised to send or buy me in the past 15 years. That's going to be a really huge party :)
Re: [PATCH 6/6] drm: tiny: gdepaper: add driver for 2/3 color epaper displays
Hi Noralf,
thank you for your comments. I've incorporated your suggestions into my draft.
On 8/7/19 1:06 AM, Noralf Trønnes wrote:
[...]
>> +static int gdepaper_probe(struct spi_device *spi)
>> +{
>> +struct device *dev = >dev;
>> +struct device_node *np = dev->of_node;
>> +const struct of_device_id *of_id;
>> +struct drm_device *drm;
>> +struct drm_display_mode *mode;
>> +struct gdepaper *epap;
>> +const struct gdepaper_type_descriptor *type_desc;
>> +int ret;
>> +size_t bufsize;
>> +
>> +of_id = of_match_node(gdepaper_of_match, np);
>> +if (WARN_ON(of_id == NULL)) {
>> +dev_warn(dev, "dt node didn't match, aborting probe\n");
>> +return -EINVAL;
>> +}
>> +type_desc = of_id->data;
>> +
>> +dev_dbg(dev, "Probing gdepaper module\n");
>> +epap = kzalloc(sizeof(*epap), GFP_KERNEL);
>> +if (!epap)
>> +return -ENOMEM;
>> +
>> +epap->enabled = false;
>> +mutex_init(>cmdlock);
>> +epap->tx_buf = NULL;
>> +epap->spi = spi;
>> +
>> +drm = >drm;
>> +ret = devm_drm_dev_init(dev, drm, _driver);
>> +if (ret) {
>> +dev_warn(dev, "failed to init drm dev\n");
>> +goto err_free;
>> +}
>> +
>> +drm_mode_config_init(drm);
>> +
>> +epap->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>> +if (IS_ERR(epap->reset)) {
>> +dev_err(dev, "Failed to get reset GPIO\n");
>> +ret = PTR_ERR(epap->reset);
>> +goto err_free;
>> +}
>> +
>> +epap->busy = devm_gpiod_get(dev, "busy", GPIOD_IN);
>> +if (IS_ERR(epap->busy)) {
>> +dev_err(dev, "Failed to get busy GPIO\n");
>> +ret = PTR_ERR(epap->busy);
>> +goto err_free;
>> +}
>> +
>> +epap->dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
>> +if (IS_ERR(epap->dc)) {
>> +dev_err(dev, "Failed to get dc GPIO\n");
>> +ret = PTR_ERR(epap->dc);
>> +goto err_free;
>> +}
>> +
>> +epap->spi_speed_hz = 200;
>> +epap->pll_div = 1;
>> +epap->framerate_mHz = 81850;
>> +epap->rfp.vg_lv = GDEP_PWR_VGHL_16V;
>> +epap->rfp.vcom_sel = 0;
>> +epap->rfp.vdh_bw_mv = 11000; /* drive high level, b/w pixel */
>> +epap->rfp.vdh_col_mv = 4200; /* drive high level, red/yellow pixel */
>> +epap->rfp.vdl_mv = -11000; /* drive low level */
>> +epap->rfp.border_data_sel = 2; /* "vbd" */
>> +epap->rfp.data_polarity = 0; /* "ddx" */
>> +epap->rfp.vcom_dc_mv = -1000;
>> +epap->rfp.vcom_data_ivl_hsync = 10; /* hsync periods */
>> +epap->rfp.use_otp_luts_flag = 1;
>> +epap->ss_param[0] = 0x07;
>> +epap->ss_param[1] = 0x07;
>> +epap->ss_param[2] = 0x17;
>> +epap->controller_res = GDEP_CTRL_RES_320X300;
>> +
>> +ret = gdepaper_of_read_luts(epap, np, dev);
>> +if (ret) {
>> +dev_warn(dev, "can't read LUTs from dt\n");
>> +goto err_free;
>> +}
>> +
>> +of_property_read_u32(np, "controller-resolution",
>> +>controller_res);
>> +of_property_read_u32(np, "spi-speed-hz", >spi_speed_hz);
>> +epap->partial_update_en = of_property_read_bool(np, "partial-update");
>> +ret = of_property_read_u32(np, "colors", >display_colors);
>> +if (ret == -EINVAL) {
>> +if (type_desc) {
>> +epap->display_colors = type_desc->colors;
>> +
>> +} else {
>> +dev_err(dev, "colors must be set in dt\n");
>> +ret = -EINVAL;
>> +goto err_free;
>> +}
>> +} else if (ret) {
>> +dev_err(dev, "Invalid dt colors property\n");
>> +goto err_free;
>> +}
>> +if (epap->display_colors < 0 ||
>> +epap->display_colors >= GDEPAPER_COL_END) {
>> +dev_err(dev, "invalid colors value\n");
>> +ret = -EINVAL;
>> +goto err_free;
>> +}
>> +epap->mirror_x = of_property_read_bool(np, "mirror-x");
>> +epap->mirror_y = of_property_read_bool(np, "mirror-y");
>> +of_property_read_u32(np, "pll-div", >pll_div);
>> +of_property_read_u32(np, "fps-millihertz", >framerate_mHz);
>> +of_property_read_u32(np, "vghl-level", >rfp.vg_lv);
>> +epap->vds_en = !of_property_read_bool(np, "vds-external");
>> +epap->vdg_en = !of_property_read_bool(np, "vdg-external");
>> +of_property_read_u32(np, "vcom", >rfp.vcom_sel);
>> +of_property_read_u32(np, "vdh-bw-millivolts", >rfp.vdh_bw_mv);
>> +of_property_read_u32(np, "vdh-color-millivolts", >rfp.vdh_col_mv);
>> +of_property_read_u32(np, "vdl-millivolts", >rfp.vdl_mv);
>> +of_property_read_u32(np, "border-data", >rfp.border_data_sel);
>> +of_property_read_u32(np, "data-polarity", >rfp.data_polarity);
>> +ret = of_property_read_u8_array(np, "boost-soft-start",
>> +(u8 *)>ss_param, sizeof(epap->ss_param));
>> +if (ret && ret !=
[PATCH libdrm v2] meson.build: enable static build
Use meson library instead of shared_library to enable static build.
Signed-off-by: Peter Seiderer
---
Changes v1 -> v2:
- no changes, resend (old submission [1])
[1] https://lists.freedesktop.org/archives/dri-devel/2018-July/183886.html
---
amdgpu/meson.build| 2 +-
etnaviv/meson.build | 2 +-
exynos/meson.build| 2 +-
freedreno/meson.build | 2 +-
intel/meson.build | 2 +-
libkms/meson.build| 2 +-
meson.build | 2 +-
nouveau/meson.build | 2 +-
omap/meson.build | 2 +-
radeon/meson.build| 2 +-
tegra/meson.build | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/amdgpu/meson.build b/amdgpu/meson.build
index 7c8ccc7..195cf53 100644
--- a/amdgpu/meson.build
+++ b/amdgpu/meson.build
@@ -21,7 +21,7 @@
datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'),
'libdrm')
-libdrm_amdgpu = shared_library(
+libdrm_amdgpu = library(
'drm_amdgpu',
[
files(
diff --git a/etnaviv/meson.build b/etnaviv/meson.build
index 515a4ed..dde3cb9 100644
--- a/etnaviv/meson.build
+++ b/etnaviv/meson.build
@@ -19,7 +19,7 @@
# SOFTWARE.
-libdrm_etnaviv = shared_library(
+libdrm_etnaviv = library(
'drm_etnaviv',
[
files(
diff --git a/exynos/meson.build b/exynos/meson.build
index bdfc3fc..d92210f 100644
--- a/exynos/meson.build
+++ b/exynos/meson.build
@@ -18,7 +18,7 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
-libdrm_exynos = shared_library(
+libdrm_exynos = library(
'drm_exynos',
[files('exynos_drm.c', 'exynos_fimg2d.c'), config_file],
c_args : libdrm_c_args,
diff --git a/freedreno/meson.build b/freedreno/meson.build
index c9aba06..787e284 100644
--- a/freedreno/meson.build
+++ b/freedreno/meson.build
@@ -39,7 +39,7 @@ if with_freedreno_kgsl
)
endif
-libdrm_freedreno = shared_library(
+libdrm_freedreno = library(
'drm_freedreno',
[files_freedreno, config_file],
c_args : libdrm_c_args,
diff --git a/intel/meson.build b/intel/meson.build
index 3d6bbac..7af0a7a 100644
--- a/intel/meson.build
+++ b/intel/meson.build
@@ -18,7 +18,7 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
-libdrm_intel = shared_library(
+libdrm_intel = library(
'drm_intel',
[
files(
diff --git a/libkms/meson.build b/libkms/meson.build
index dc93160..4104dfe 100644
--- a/libkms/meson.build
+++ b/libkms/meson.build
@@ -41,7 +41,7 @@ if with_exynos
libkms_include += include_directories('../exynos')
endif
-libkms = shared_library(
+libkms = library(
'kms',
[files_libkms, config_file],
c_args : libdrm_c_args,
diff --git a/meson.build b/meson.build
index 087780b..adaaf22 100644
--- a/meson.build
+++ b/meson.build
@@ -282,7 +282,7 @@ add_project_arguments('-include', 'config.h', language :
'c')
inc_root = include_directories('.')
inc_drm = include_directories('include/drm')
-libdrm = shared_library(
+libdrm = library(
'drm',
[files(
'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c',
diff --git a/nouveau/meson.build b/nouveau/meson.build
index 0c1498d..edd7025 100644
--- a/nouveau/meson.build
+++ b/nouveau/meson.build
@@ -19,7 +19,7 @@
# SOFTWARE.
-libdrm_nouveau = shared_library(
+libdrm_nouveau = library(
'drm_nouveau',
[files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file],
c_args : libdrm_c_args,
diff --git a/omap/meson.build b/omap/meson.build
index 54698c6..1d34927 100644
--- a/omap/meson.build
+++ b/omap/meson.build
@@ -18,7 +18,7 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
-libdrm_omap = shared_library(
+libdrm_omap = library(
'drm_omap',
[files('omap_drm.c'), config_file],
include_directories : [inc_root, inc_drm],
diff --git a/radeon/meson.build b/radeon/meson.build
index 1fc5282..23acbd7 100644
--- a/radeon/meson.build
+++ b/radeon/meson.build
@@ -19,7 +19,7 @@
# SOFTWARE.
-libdrm_radeon = shared_library(
+libdrm_radeon = library(
'drm_radeon',
[
files(
diff --git a/tegra/meson.build b/tegra/meson.build
index 4bc454b..ee7aab4 100644
--- a/tegra/meson.build
+++ b/tegra/meson.build
@@ -18,7 +18,7 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
-libdrm_tegra = shared_library(
+libdrm_tegra = library(
'drm_tegra',
[files('tegra.c'), config_file],
include_directories : [inc_root, inc_drm],
--
2.22.0
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[PATCH libdrm v2] meson.build: fix intel atomics detection
Use the stronger compiler.link() test (instead of the weaker
compiler.compile()) to fix the intel atomics detection.
Fixes false positive in case of sparc compile (buildroot toolchain).
Signed-off-by: Peter Seiderer
---
Changes v1 -> v2:
- no changes, resend (old submission [1])
[1] https://lists.freedesktop.org/archives/dri-devel/2018-July/183885.html
---
meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index e292554..087780b 100644
--- a/meson.build
+++ b/meson.build
@@ -49,9 +49,10 @@ intel_atomics = false
lib_atomics = false
dep_atomic_ops = dependency('atomic_ops', required : false)
-if cc.compiles('''
+if cc.links('''
int atomic_add(int *i) { return __sync_add_and_fetch (i, 1); }
int atomic_cmpxchg(int *i, int j, int k) { return
__sync_val_compare_and_swap (i, j, k); }
+int main() { }
''',
name : 'Intel Atomics')
intel_atomics = true
--
2.22.0
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[PATCH libdrm v1] meson: fix libdl/shared library support detection for nouveau tests
Some toolchains (e.g. br-arm-cortex-m4-full) provide empty libdl
libraries. This fools the dynamic/static detection for tests/nouveau,
so explicit check for library type instead.
Fixes:
../tests/nouveau/threaded.c:24:10: fatal error: dlfcn.h: No such file or
directory
Signed-off-by: Peter Seiderer
---
meson.build | 1 +
tests/meson.build | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index adaaf22..b78d9e5 100644
--- a/meson.build
+++ b/meson.build
@@ -168,6 +168,7 @@ endif
# Among others FreeBSD does not have a separate dl library.
if not cc.has_function('dlsym')
+ # fooled in case empty libdl provided, e.g. toolchain br-arm-cortex-m4-full
dep_dl = cc.find_library('dl', required : with_nouveau)
else
dep_dl = []
diff --git a/tests/meson.build b/tests/meson.build
index 6c8ddd9..f7cb5f0 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -44,8 +44,11 @@ endif
if with_etnaviv
subdir('etnaviv')
endif
+lib_type = get_option('default_library')
if with_nouveau
- subdir('nouveau')
+ if lib_type != 'static'
+subdir('nouveau')
+ endif
endif
drmsl = executable(
--
2.22.0
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Re: [PATCH] drm/panfrost: Add errata descriptions from kbase
On Fri, Aug 9, 2019 at 3:09 PM Alyssa Rosenzweig wrote: > > While newer kbase include only the numbers of errata, older kbase > releases included one-line descriptions for each errata, which is useful > for those working on the driver. Import these descriptions. Most are > from kbase verbatim; a few I edited for clarity. > > v2: Wrote a description for the workaround of an issue whose cause is > still unknown (Stephen). Errata which pertain to newer models > unsupported by the mainline driver, for which Arm has not yet released > errata information, have been removed from the issue list as the kernel > need not concern itself with these. I had scrubbed the issue list to keep just the errata with work-arounds in kbase. I'd rather not have to search this information again because in kbase we have to filter out all the issues which don't affect the kernel side. Rob ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 33/37] drm/i915: cpu-map based dumb buffers
From: Abdiel Janulgue
If there is no aperture we can't use map_gtt to map dumb buffers, so we
need a cpu-map based path to do it. We prefer map_gtt on platforms that
do have aperture.
Signed-off-by: Abdiel Janulgue
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
4 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 304ea578fd30..4fe83e31c1b3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -500,7 +500,8 @@ static void i915_gem_object_release_mmap_offset(struct
drm_i915_gem_object *obj)
list_for_each_entry(mmo, >mmap_offsets, offset) {
if (mmo->mmap_type == I915_MMAP_TYPE_OFFSET_WC ||
mmo->mmap_type == I915_MMAP_TYPE_OFFSET_WB ||
- mmo->mmap_type == I915_MMAP_TYPE_OFFSET_UC)
+ mmo->mmap_type == I915_MMAP_TYPE_OFFSET_UC ||
+ mmo->mmap_type == I915_MMAP_TYPE_DUMB_WC)
drm_vma_node_unmap(>vma_node,
obj->base.dev->anon_inode->i_mapping);
}
@@ -602,6 +603,19 @@ __assign_gem_object_mmap_data(struct drm_file *file,
return ret;
}
+int
+i915_gem_mmap_dumb(struct drm_file *file,
+ struct drm_device *dev,
+ u32 handle,
+ u64 *offset)
+{
+ struct drm_i915_private *i915 = dev->dev_private;
+ enum i915_mmap_type mmap_type = HAS_MAPPABLE_APERTURE(i915) ?
+ I915_MMAP_TYPE_GTT : I915_MMAP_TYPE_DUMB_WC;
+
+ return __assign_gem_object_mmap_data(file, handle, mmap_type, offset);
+}
+
/**
* i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
* @dev: DRM device
@@ -714,6 +728,7 @@ static void set_vmdata_mmap_offset(struct i915_mmap_offset
*mmo, struct vm_area_
{
switch (mmo->mmap_type) {
case I915_MMAP_TYPE_OFFSET_WC:
+ case I915_MMAP_TYPE_DUMB_WC:
vma->vm_page_prot =
pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
break;
@@ -801,6 +816,7 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct
*vma)
case I915_MMAP_TYPE_OFFSET_WC:
case I915_MMAP_TYPE_OFFSET_WB:
case I915_MMAP_TYPE_OFFSET_UC:
+ case I915_MMAP_TYPE_DUMB_WC:
set_vmdata_mmap_offset(mmo, vma);
break;
case I915_MMAP_TYPE_GTT:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 4ea78d3c92a9..d280267689f9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -67,6 +67,7 @@ enum i915_mmap_type {
I915_MMAP_TYPE_OFFSET_WC,
I915_MMAP_TYPE_OFFSET_WB,
I915_MMAP_TYPE_OFFSET_UC,
+ I915_MMAP_TYPE_DUMB_WC,
};
struct i915_mmap_offset {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cf390092c927..f6a3daf696f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2762,7 +2762,7 @@ static struct drm_driver driver = {
.get_scanout_position = i915_get_crtc_scanoutpos,
.dumb_create = i915_gem_dumb_create,
- .dumb_map_offset = i915_gem_mmap_gtt,
+ .dumb_map_offset = i915_gem_mmap_dumb,
.ioctls = i915_ioctls,
.num_ioctls = ARRAY_SIZE(i915_ioctls),
.fops = _driver_fops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a5b90670e16..f93f55947b7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2363,7 +2363,7 @@ i915_mutex_lock_interruptible(struct drm_device *dev)
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
-int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
+int i915_gem_mmap_dumb(struct drm_file *file_priv, struct drm_device *dev,
u32 handle, u64 *offset);
int i915_gem_mmap_gtt_version(void);
--
2.20.1
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[PATCH v3 26/37] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 64 ++-
2 files changed, 63 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index dd28c54527e3..0819ac9837dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2630,7 +2630,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
{
ggtt_release_guc_top(ggtt);
- drm_mm_remove_node(>error_capture);
+ if (drm_mm_node_allocated(>error_capture))
+ drm_mm_remove_node(>error_capture);
}
static int init_ggtt(struct i915_ggtt *ggtt)
@@ -2661,13 +2662,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(>vm.mm, >error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (HAS_MAPPABLE_APERTURE(ggtt->vm.i915)) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(>vm.mm,
>error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/*
* The upper portion of the GuC address space has a sizeable hole
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 92986d3f6995..19eb5ccba387 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -40,6 +40,7 @@
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
@@ -235,6 +236,7 @@ struct compress {
struct pagevec pool;
struct z_stream_s zstream;
void *tmp;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
struct z_stream_s *zstream = >zstream;
zstream->next_in = src;
- if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
+ if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
zstream->next_in = c->tmp;
zstream->avail_in = PAGE_SIZE;
@@ -367,6 +369,7 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
struct compress {
struct pagevec pool;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
if (!ptr)
return -ENOMEM;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -963,7 +966,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct drm_i915_error_object *dst;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
might_sleep();
@@ -988,17 +990,53 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
+ compress->wc = i915_gem_object_is_lmem(vma->obj) ||
+ drm_mm_node_allocated(>error_capture);
+
ret = -EINVAL;
- for_each_sgt_dma(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(>error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(>vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_dma(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(>vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_wc(>iomap, slot, PAGE_SIZE);
- ret = compress_page(compress, (void __force *)s, dst);
- io_mapping_unmap(s);
- if (ret)
- break;
+ s = io_mapping_map_wc(>iomap, slot, PAGE_SIZE);
+ ret = compress_page(compress, (void __force *)s, dst);
+ io_mapping_unmap(s);
+ if (ret)
+
[PATCH v3 27/37] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 634ef45b77da..46658ecd8975 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -512,7 +512,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && HAS_MAPPABLE_APERTURE(engine->i915)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 32/37] drm/i915: Add cpu and lmem fault handlers
From: Abdiel Janulgue
Fault handler to handle missing pages to be filled depending on an
object's backing storage. Handle also changes needed to refault pages
depending on fault handler usage.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 54 +++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 3 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 155 +++--
drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c| 2 +-
5 files changed, 201 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 8d0251af5dfc..2194e2c3bdcd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_gt.h"
#include "i915_drv.h"
static int lmem_pread(struct drm_i915_gem_object *obj,
@@ -179,6 +180,59 @@ static int lmem_pwrite(struct drm_i915_gem_object *obj,
return ret;
}
+vm_fault_t i915_gem_fault_lmem(struct vm_fault *vmf)
+{
+ struct vm_area_struct *area = vmf->vma;
+ struct i915_mmap_offset *priv = area->vm_private_data;
+ struct drm_i915_gem_object *obj = priv->obj;
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ unsigned long size = area->vm_end - area->vm_start;
+ bool write = area->vm_flags & VM_WRITE;
+ vm_fault_t vmf_ret;
+ int i, ret;
+
+ /* Sanity check that we allow writing into this object */
+ if (i915_gem_object_is_readonly(obj) && write)
+ return VM_FAULT_SIGBUS;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ goto err;
+
+ for (i = 0; i < size >> PAGE_SHIFT; i++) {
+ vmf_ret = vmf_insert_pfn(area,
+(unsigned long)area->vm_start + i *
PAGE_SIZE,
+i915_gem_object_lmem_io_offset(obj, i)
>> PAGE_SHIFT);
+ if (vmf_ret & VM_FAULT_ERROR) {
+ ret = vm_fault_to_errno(vmf_ret, 0);
+ goto err;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+err:
+ switch (ret) {
+ case -EIO:
+ if (!intel_gt_is_wedged(>gt))
+ return VM_FAULT_SIGBUS;
+ /* fallthrough */
+ case -EAGAIN:
+ case 0:
+ case -ERESTARTSYS:
+ case -EINTR:
+ case -EBUSY:
+ return VM_FAULT_NOPAGE;
+ case -ENOMEM:
+ return VM_FAULT_OOM;
+ case -ENOSPC:
+ case -EFAULT:
+ return VM_FAULT_SIGBUS;
+ default:
+ WARN_ONCE(ret, "unhandled error in %s: %i\n", __func__, ret);
+ return VM_FAULT_SIGBUS;
+ }
+}
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.flags = I915_GEM_OBJECT_IS_MAPPABLE,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index 43e6e715eeed..c3255eb6daa5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -7,6 +7,7 @@
#define __I915_GEM_LMEM_H
#include
+#include
struct drm_i915_private;
struct drm_i915_gem_object;
@@ -24,6 +25,8 @@ i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object *obj,
resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj,
unsigned long n);
+vm_fault_t i915_gem_fault_lmem(struct vm_fault *vmf);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index a62657a1f011..304ea578fd30 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include "gt/intel_gt.h"
@@ -12,6 +13,7 @@
#include "i915_drv.h"
#include "i915_gem_gtt.h"
#include "i915_gem_ioctls.h"
+#include "i915_gem_lmem.h"
#include "i915_gem_object.h"
#include "i915_trace.h"
#include "i915_vma.h"
@@ -371,7 +373,62 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
}
}
-void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
+static vm_fault_t i915_gem_fault_cpu(struct vm_fault *vmf)
+{
+ struct vm_area_struct *area = vmf->vma;
+ struct i915_mmap_offset *priv = area->vm_private_data;
+ struct drm_i915_gem_object *obj = priv->obj;
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ vm_fault_t vmf_ret;
+ unsigned long size = area->vm_end - area->vm_start;
+ bool
[PATCH v3 37/37] HAX drm/i915: add the fake lmem region
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the aperture and 1:1 it map to the stolen region.
To enable simply set i915_fake_lmem_start= on the kernel cmdline with the
start of reserved region(see memmap=). The size of the region we can
use is determined by the size of the mappable aperture, so the size of
reserved region should be >= mappable_end.
eg. memmap=2G$16G i915_fake_lmem_start=0x4
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
arch/x86/kernel/early-quirks.c | 26
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 3 +
drivers/gpu/drm/i915/i915_drv.c| 8 +++
drivers/gpu/drm/i915/i915_gem_gtt.c| 3 +
drivers/gpu/drm/i915/intel_memory_region.h | 4 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 69 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 5 ++
include/drm/i915_drm.h | 3 +
8 files changed, 121 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6f6b1d04dadf..9b04655e3926 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -603,6 +603,32 @@ static void __init intel_graphics_quirks(int num, int
slot, int func)
}
}
+struct resource intel_graphics_fake_lmem_res __ro_after_init =
DEFINE_RES_MEM(0, 0);
+EXPORT_SYMBOL(intel_graphics_fake_lmem_res);
+
+static int __init early_i915_fake_lmem_init(char *s)
+{
+ u64 start;
+ int ret;
+
+ if (*s == '=')
+ s++;
+
+ ret = kstrtoull(s, 16, );
+ if (ret)
+ return ret;
+
+ intel_graphics_fake_lmem_res.start = start;
+ intel_graphics_fake_lmem_res.end = SZ_2G; /* Placeholder; depends on
aperture size */
+
+ printk(KERN_INFO "Intel graphics fake LMEM starts at %pa\n",
+ _graphics_fake_lmem_res.start);
+
+ return 0;
+}
+
+early_param("i915_fake_lmem_start", early_i915_fake_lmem_init);
+
static void __init force_disable_hpet(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 2194e2c3bdcd..bcdc7fd099af 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -252,6 +252,7 @@ void __iomem *i915_gem_object_lmem_io_map_page(struct
drm_i915_gem_object *obj,
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= intel_graphics_fake_lmem_res.start;
return io_mapping_map_wc(>mm.region->iomap, offset, PAGE_SIZE);
}
@@ -262,6 +263,7 @@ void __iomem
*i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= intel_graphics_fake_lmem_res.start;
return io_mapping_map_atomic_wc(>mm.region->iomap, offset);
}
@@ -275,6 +277,7 @@ void __iomem *i915_gem_object_lmem_io_map(struct
drm_i915_gem_object *obj,
GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= intel_graphics_fake_lmem_res.start;
return io_mapping_map_wc(>mm.region->iomap, offset, size);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 845e80c2acc0..f71685a6d49b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1474,6 +1474,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
+ /* Check if we support fake LMEM -- enable for live selftests */
+ if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live &&
+ intel_graphics_fake_lmem_res.start) {
+ mkwrite_device_info(dev_priv)->memory_regions =
+ REGION_SMEM | REGION_LMEM;
+ GEM_BUG_ON(!HAS_LMEM(dev_priv));
+ }
+
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0819ac9837dc..355268d85374 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2747,6 +2747,9 @@ int i915_gem_init_memory_regions(struct drm_i915_private
*i915)
case INTEL_STOLEN:
mem = i915_gem_stolen_setup(i915);
break;
+ case INTEL_LMEM:
+ mem = intel_setup_fake_lmem(i915);
+ break;
}
if
[PATCH v3 30/37] drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET
From: Abdiel Janulgue
Add a new CPU mmap implementation that allows multiple fault handlers
that depends on the object's backing pages.
Note that we multiplex mmap_gtt and mmap_offset through the same ioctl,
and use the zero extending behaviour of drm to differentiate between
them, when we inspect the flags.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 2 ++
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 30 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_getparam.c | 1 +
include/uapi/drm/i915_drm.h | 31 +++
6 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
index ddc7f2a52b3e..5abd5b2172f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
@@ -30,6 +30,8 @@ int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
+int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index d4a9d59803a7..a62657a1f011 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -538,12 +538,42 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void
*data,
struct drm_file *file)
{
struct drm_i915_gem_mmap_offset *args = data;
+ struct drm_i915_private *i915 = to_i915(dev);
+
+ if (args->flags & I915_MMAP_OFFSET_FLAGS)
+ return i915_gem_mmap_offset_ioctl(dev, data, file);
+
+ if (!HAS_MAPPABLE_APERTURE(i915)) {
+ DRM_ERROR("No aperture, cannot mmap via legacy GTT\n");
+ return -ENODEV;
+ }
return __assign_gem_object_mmap_data(file, args->handle,
I915_MMAP_TYPE_GTT,
>offset);
}
+int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_gem_mmap_offset *args = data;
+ enum i915_mmap_type type;
+
+ if ((args->flags & (I915_MMAP_OFFSET_WC | I915_MMAP_OFFSET_WB)) &&
+ !boot_cpu_has(X86_FEATURE_PAT))
+ return -ENODEV;
+
+ if (args->flags & I915_MMAP_OFFSET_WC)
+ type = I915_MMAP_TYPE_OFFSET_WC;
+ else if (args->flags & I915_MMAP_OFFSET_WB)
+ type = I915_MMAP_TYPE_OFFSET_WB;
+ else if (args->flags & I915_MMAP_OFFSET_UC)
+ type = I915_MMAP_TYPE_OFFSET_UC;
+
+ return __assign_gem_object_mmap_data(file, args->handle, type,
+>offset);
+}
+
void i915_mmap_offset_object_release(struct kref *ref)
{
struct i915_mmap_offset *mmo = container_of(ref,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a3745f7d57a1..4ea78d3c92a9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -64,6 +64,9 @@ struct drm_i915_gem_object_ops {
enum i915_mmap_type {
I915_MMAP_TYPE_GTT = 0,
+ I915_MMAP_TYPE_OFFSET_WC,
+ I915_MMAP_TYPE_OFFSET_WB,
+ I915_MMAP_TYPE_OFFSET_UC,
};
struct i915_mmap_offset {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fcee06ed3469..cf390092c927 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2710,7 +2710,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
- DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_gtt_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl,
DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
[PATCH v3 29/37] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core
From: Abdiel Janulgue
This enables us to store extra data within vma->vm_private_data and assign
the pagefault ops for each mmap instance.
We replace the core drm_gem_mmap implementation to overcome the limitation
in having only a single offset node per gem object, allowing us to have
multiple offsets per object. This enables a mapping instance to use unique
fault-hadlers, per object.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 183 --
drivers/gpu/drm/i915/gem/i915_gem_object.c| 16 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 7 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 18 ++
.../drm/i915/gem/selftests/i915_gem_mman.c| 12 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 13 +-
drivers/gpu/drm/i915/i915_drv.c | 9 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 21 +-
9 files changed, 244 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 1e7311493530..d4a9d59803a7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -221,7 +221,8 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
{
#define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
struct vm_area_struct *area = vmf->vma;
- struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
+ struct i915_mmap_offset *priv = area->vm_private_data;
+ struct drm_i915_gem_object *obj = priv->obj;
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_runtime_pm *rpm = >runtime_pm;
@@ -373,13 +374,15 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
{
struct i915_vma *vma;
+ struct i915_mmap_offset *mmo;
GEM_BUG_ON(!obj->userfault_count);
obj->userfault_count = 0;
list_del(>userfault_link);
- drm_vma_node_unmap(>base.vma_node,
- obj->base.dev->anon_inode->i_mapping);
+ list_for_each_entry(mmo, >mmap_offsets, offset)
+ drm_vma_node_unmap(>vma_node,
+ obj->base.dev->anon_inode->i_mapping);
for_each_ggtt_vma(vma, obj)
i915_vma_unset_userfault(vma);
@@ -433,14 +436,31 @@ void i915_gem_object_release_mmap(struct
drm_i915_gem_object *obj)
intel_runtime_pm_put(>runtime_pm, wakeref);
}
-static int create_mmap_offset(struct drm_i915_gem_object *obj)
+static void init_mmap_offset(struct drm_i915_gem_object *obj,
+struct i915_mmap_offset *mmo)
+{
+ mutex_lock(>mmo_lock);
+ kref_init(>ref);
+ list_add(>offset, >mmap_offsets);
+ mutex_unlock(>mmo_lock);
+}
+
+static int create_mmap_offset(struct drm_i915_gem_object *obj,
+ struct i915_mmap_offset *mmo)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct drm_device *dev = obj->base.dev;
int err;
- err = drm_gem_create_mmap_offset(>base);
- if (likely(!err))
+ drm_vma_node_reset(>vma_node);
+ if (mmo->file)
+ drm_vma_node_allow(>vma_node, mmo->file);
+ err = drm_vma_offset_add(dev->vma_offset_manager, >vma_node,
+obj->base.size / PAGE_SIZE);
+ if (likely(!err)) {
+ init_mmap_offset(obj, mmo);
return 0;
+ }
/* Attempt to reap some mmap space from dead objects */
do {
@@ -451,32 +471,49 @@ static int create_mmap_offset(struct drm_i915_gem_object
*obj)
break;
i915_gem_drain_freed_objects(i915);
- err = drm_gem_create_mmap_offset(>base);
- if (!err)
+ err = drm_vma_offset_add(dev->vma_offset_manager,
>vma_node,
+obj->base.size / PAGE_SIZE);
+ if (!err) {
+ init_mmap_offset(obj, mmo);
break;
+ }
} while (flush_delayed_work(>gem.retire_work));
return err;
}
-int
-i915_gem_mmap_gtt(struct drm_file *file,
- struct drm_device *dev,
- u32 handle,
- u64 *offset)
+static int
+__assign_gem_object_mmap_data(struct drm_file *file,
+ u32 handle,
+ enum i915_mmap_type mmap_type,
+ u64 *offset)
{
struct drm_i915_gem_object *obj;
+ struct i915_mmap_offset *mmo;
int ret;
obj = i915_gem_object_lookup(file, handle);
if (!obj)
return -ENOENT;
- ret = create_mmap_offset(obj);
- if (ret == 0)
-
[PATCH v3 36/37] drm/i915/query: Expose memory regions through the query uAPI
From: Abdiel Janulgue
Returns the available memory region areas supported by the HW.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c | 57 +++
include/uapi/drm/i915_drm.h | 39 +
2 files changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index ad9240a0817a..69a2a906feef 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -142,10 +142,67 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int query_memregion_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_memory_region_info __user *query_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_memory_region_info __user *info_ptr =
+ _ptr->regions[0];
+ struct drm_i915_memory_region_info info = { };
+ struct drm_i915_query_memory_region_info query;
+ u32 total_length;
+ int ret, i;
+
+ if (query_item->flags != 0)
+ return -EINVAL;
+
+ total_length = sizeof(struct drm_i915_query_memory_region_info);
+ for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
+ struct intel_memory_region *region = dev_priv->regions[i];
+
+ if (!region)
+ continue;
+
+ total_length += sizeof(struct drm_i915_memory_region_info);
+ }
+
+ ret = copy_query_item(, sizeof(query), total_length,
+ query_item);
+ if (ret != 0)
+ return ret;
+
+ if (query.num_regions || query.rsvd[0] || query.rsvd[1] ||
+ query.rsvd[2])
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
+ struct intel_memory_region *region = dev_priv->regions[i];
+
+ if (!region)
+ continue;
+
+ info.id = region->id;
+ info.size = resource_size(>region);
+
+ if (__copy_to_user(info_ptr, , sizeof(info)))
+ return -EFAULT;
+
+ query.num_regions++;
+ info_ptr++;
+ }
+
+ if (__copy_to_user(query_ptr, , sizeof(query)))
+ return -EFAULT;
+
+ return total_length;
+}
+
static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
= {
query_topology_info,
query_engine_info,
+ query_memregion_info,
};
int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 75d79c17e91b..7ef037f58e1b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2038,6 +2038,7 @@ struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO1
#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_MEMREGION_INFO 3
/* Must be kept compact -- no holes and well documented */
/*
@@ -2177,6 +2178,44 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
+struct drm_i915_memory_region_info {
+
+ /** Base type of a region
+*/
+#define I915_SYSTEM_MEMORY 0
+#define I915_DEVICE_MEMORY 1
+
+ /** The region id is encoded in a layout which makes it possible to
+* retrieve the following information:
+*
+* Base type: log2(ID >> 16)
+* Instance: log2(ID & 0x)
+*/
+ __u32 id;
+
+ /** Reserved field. MBZ */
+ __u32 rsvd0;
+
+ /** Unused for now. MBZ */
+ __u64 flags;
+
+ __u64 size;
+
+ /** Reserved fields must be cleared to zero. */
+ __u64 rsvd1[4];
+};
+
+struct drm_i915_query_memory_region_info {
+
+ /** Number of struct drm_i915_memory_region_info structs */
+ __u32 num_regions;
+
+ /** MBZ */
+ __u32 rsvd[3];
+
+ struct drm_i915_memory_region_info regions[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.20.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 34/37] drm/i915: support basic object migration
We are going want to able to move objects between different regions
like system memory and local memory. In the future everything should
be just another region.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 140 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
.../drm/i915/selftests/intel_memory_region.c | 129
4 files changed, 278 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 24f737b00e84..5982aeaaa2e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -28,6 +28,8 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_object.h"
+#include "i915_gem_object_blt.h"
+#include "i915_gem_region.h"
#include "i915_globals.h"
#include "i915_trace.h"
@@ -170,6 +172,144 @@ static void __i915_gem_free_object_rcu(struct rcu_head
*head)
atomic_dec(>mm.free_count);
}
+
+int i915_gem_object_prepare_move(struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ lockdep_assert_held(>base.dev->struct_mutex);
+
+ if (obj->mm.madv != I915_MADV_WILLNEED)
+ return -EINVAL;
+
+ if (i915_gem_object_needs_bit17_swizzle(obj))
+ return -EINVAL;
+
+ if (atomic_read(>mm.pages_pin_count) >
+ atomic_read(>bind_count))
+ return -EBUSY;
+
+ if (obj->pin_global)
+ return -EBUSY;
+
+ i915_gem_object_release_mmap(obj);
+
+ GEM_BUG_ON(obj->mm.mapping);
+ GEM_BUG_ON(obj->base.filp && mapping_mapped(obj->base.filp->f_mapping));
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_LOCKED |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ return err;
+
+ return i915_gem_object_unbind(obj,
+ I915_GEM_OBJECT_UNBIND_ACTIVE);
+}
+
+int i915_gem_object_migrate(struct drm_i915_gem_object *obj,
+ struct intel_context *ce,
+ enum intel_region_id id)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct drm_i915_gem_object *donor;
+ struct intel_memory_region *mem;
+ struct sg_table *pages = NULL;
+ unsigned int page_sizes;
+ int err = 0;
+
+ lockdep_assert_held(>drm.struct_mutex);
+
+ GEM_BUG_ON(id >= INTEL_MEMORY_UKNOWN);
+ GEM_BUG_ON(obj->mm.region->id == id);
+ GEM_BUG_ON(obj->mm.madv != I915_MADV_WILLNEED);
+
+ mem = i915->regions[id];
+
+ donor = i915_gem_object_create_region(mem, obj->base.size, 0);
+ if (IS_ERR(donor))
+ return PTR_ERR(donor);
+
+ /* Copy backing-pages if we have to */
+ if (i915_gem_object_has_pages(obj)) {
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto err_put_donor;
+
+ err = i915_gem_object_copy_blt(obj, donor, ce);
+ if (err)
+ goto err_put_donor;
+
+ i915_gem_object_lock(donor);
+ err = i915_gem_object_set_to_cpu_domain(donor, false);
+ i915_gem_object_unlock(donor);
+ if (err)
+ goto err_put_donor;
+
+ i915_retire_requests(i915);
+
+ i915_gem_object_unbind(donor, 0);
+ err = i915_gem_object_unbind(obj, 0);
+ if (err)
+ goto err_put_donor;
+
+ mutex_lock(>mm.lock);
+
+ pages = __i915_gem_object_unset_pages(obj);
+ obj->ops->put_pages(obj, pages);
+
+ mutex_unlock(>mm.lock);
+
+ page_sizes = donor->mm.page_sizes.phys;
+ pages = __i915_gem_object_unset_pages(donor);
+ }
+
+ if (obj->ops->release)
+ obj->ops->release(obj);
+
+ mutex_lock(>mm.lock);
+
+ /* We need still need a little special casing for shmem */
+ if (obj->base.filp)
+ fput(fetch_and_zero(>base.filp));
+ else if (donor->base.filp) {
+ atomic_long_inc(>base.filp->f_count);
+ obj->base.filp = donor->base.filp;
+ }
+
+ obj->base.size = donor->base.size;
+ obj->mm.region = mem;
+ obj->flags = donor->flags;
+ obj->ops = donor->ops;
+ obj->cache_level = donor->cache_level;
+ obj->cache_coherent = donor->cache_coherent;
+ obj->cache_dirty = donor->cache_dirty;
+
+ list_replace_init(>mm.blocks, >mm.blocks);
+
+ mutex_lock(>obj_lock);
+
[PATCH v3 35/37] drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION
From: Abdiel Janulgue
This call will specify which memory region an object should be placed.
Note that changing the object's backing storage should be immediately
done after an object is created or if it's not yet in use, otherwise
this will fail on a busy object.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 +++
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_object.c | 115
drivers/gpu/drm/i915/i915_drv.c | 2 +-
include/uapi/drm/i915_drm.h | 23
6 files changed, 160 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index b407baaf0014..572033ac6e3b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -76,6 +76,7 @@
#include "i915_globals.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
+#include "i915_gem_ioctls.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
@@ -2308,6 +2309,22 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
return ret;
}
+int i915_gem_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_gem_context_param *args = data;
+ u32 object_class = upper_32_bits(args->param);
+
+ switch (object_class) {
+ case 0:
+ return i915_gem_context_setparam_ioctl(dev, data, file);
+ case 1:
+ return i915_gem_object_setparam_ioctl(dev, data, file);
+
+ }
+ return -EINVAL;
+}
+
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 106e2ccf7a4c..1cfcf1e6bbb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -157,6 +157,8 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+int i915_gem_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file);
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
index 5abd5b2172f2..af7465bceebd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
@@ -32,6 +32,8 @@ int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void
*data,
struct drm_file *file);
int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+int i915_gem_object_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 5982aeaaa2e3..52ea65f203a1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -506,6 +506,121 @@ int __init i915_global_objects_init(void)
return 0;
}
+static enum intel_region_id
+__region_id(u32 region)
+{
+ enum intel_region_id id;
+
+ for (id = 0; id < INTEL_MEMORY_UKNOWN; ++id) {
+ if (intel_region_map[id] == region)
+ return id;
+ }
+
+ return INTEL_MEMORY_UKNOWN;
+}
+
+static int i915_gem_object_region_select(struct drm_i915_private *dev_priv,
+struct drm_i915_gem_object_param *args,
+struct drm_file *file,
+struct drm_i915_gem_object *obj)
+{
+ struct intel_context *ce = dev_priv->engine[BCS0]->kernel_context;
+ u32 __user *uregions = u64_to_user_ptr(args->data);
+ u32 uregions_copy[INTEL_MEMORY_UKNOWN];
+ int i, ret;
+
+ if (args->size > INTEL_MEMORY_UKNOWN)
+ return -EINVAL;
+
+ memset(uregions_copy, 0, sizeof(uregions_copy));
+ for (i = 0; i < args->size; i++) {
+ u32 region;
+
+ ret = get_user(region, uregions);
+ if (ret)
+ return ret;
+
+ uregions_copy[i] =
[PATCH v3 21/37] drm/i915: treat stolen as a region
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 71 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
drivers/gpu/drm/i915/i915_pci.c| 2 +-
5 files changed, 68 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 592012bb9b14..b6f18c3b9eed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -158,7 +158,7 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
return ERR_PTR(-E2BIG);
obj = mem->ops->create_object(mem, size, flags);
- if (!IS_ERR(obj))
+ if (!IS_ERR_OR_NULL(obj))
trace_i915_gem_object_create(obj);
return obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 696dea5ec7c6..c93a3fac90f6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -10,6 +10,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
@@ -150,7 +151,7 @@ static int i915_adjust_stolen(struct drm_i915_private
*dev_priv,
return 0;
}
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
{
if (!drm_mm_initialized(_priv->mm.stolen))
return;
@@ -355,7 +356,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private
*i915,
}
}
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
+static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
@@ -532,6 +533,9 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj)
i915_gem_stolen_remove_node(dev_priv, stolen);
kfree(stolen);
+
+ if (obj->mm.region)
+ i915_gem_object_release_memory_region(obj);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
@@ -541,8 +545,9 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_stolen_ops = {
};
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- struct drm_mm_node *stolen)
+__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *stolen,
+ struct intel_memory_region *mem)
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
@@ -559,6 +564,9 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency(obj, cache_level);
+ if (mem)
+ i915_gem_object_init_memory_region(obj, mem, 0);
+
if (i915_gem_object_pin_pages(obj))
goto cleanup;
@@ -569,10 +577,12 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size)
+static struct drm_i915_gem_object *
+_i915_gem_object_create_stolen(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
{
+ struct drm_i915_private *dev_priv = mem->i915;
struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
int ret;
@@ -593,7 +603,7 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
- obj = _i915_gem_object_create_stolen(dev_priv, stolen);
+ obj = __i915_gem_object_create_stolen(dev_priv, stolen, mem);
if (obj)
return obj;
@@ -602,6 +612,49 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size)
+{
+ struct drm_i915_gem_object *obj;
+
+ obj =
i915_gem_object_create_region(dev_priv->regions[INTEL_MEMORY_STOLEN],
+ size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj))
+ return NULL;
+
+ return obj;
+}
+
+static int init_stolen(struct intel_memory_region *mem)
+{
+ /*
+* Initialise stolen early so that we may reserve
[PATCH v3 31/37] drm/i915/lmem: add helper to get CPU accessible offset
From: Abdiel Janulgue
LMEM can be accessed by the CPU through a BAR. The mapping itself should
be 1:1.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 16
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index f00078ac331e..8d0251af5dfc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -225,6 +225,22 @@ void __iomem *i915_gem_object_lmem_io_map(struct
drm_i915_gem_object *obj,
return io_mapping_map_wc(>mm.region->iomap, offset, size);
}
+resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ dma_addr_t daddr;
+
+ /*
+* XXX: It's not a dma address, more a device address or physical
+* offset, so we are clearly abusing the semantics of the sg_table
+* here, and elsewhere like in the gtt paths.
+*/
+ daddr = i915_gem_object_get_dma_address(obj, n);
+
+ return mem->io_start + daddr;
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->mm.region;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index 31a6462bdbb6..43e6e715eeed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -21,6 +21,9 @@ void __iomem *
i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
unsigned long n);
+resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 15/37] drm/i915/selftest: extend coverage to include LMEM huge-pages
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index c36cef61ce3c..4bac15363020 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -970,7 +971,7 @@ static int gpu_write(struct i915_vma *vma,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1002,6 +1003,51 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct drm_i915_gem_object *obj,
@@ -1382,6 +1428,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1732,6 +1850,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private
[PATCH v3 16/37] drm/i915/lmem: support CPU relocations
Add LMEM support for the CPU reloc path. When doing relocations we have
both a GPU and CPU reloc path, as well as some debugging options to force a
particular path. The GPU reloc path is preferred when the object
is not currently idle, otherwise we use the CPU reloc path. Since we
can't kmap the object, and the mappable aperture might not be available,
add support for mapping it through LMEMBAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 55 +--
1 file changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 2fa08357944e..d70b3e6dc12d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -15,6 +15,7 @@
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_ioctls.h"
+#include "gem/i915_gem_lmem.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pool.h"
#include "gt/intel_gt.h"
@@ -251,6 +252,7 @@ struct i915_execbuffer {
bool has_llc : 1;
bool has_fence : 1;
bool needs_unfenced : 1;
+ bool is_lmem : 1;
struct i915_request *rq;
u32 *rq_cmd;
@@ -959,6 +961,7 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
cache->has_fence = cache->gen < 4;
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
+ cache->is_lmem = false;
cache->node.allocated = false;
cache->rq = NULL;
cache->rq_size = 0;
@@ -1017,10 +1020,14 @@ static void reloc_cache_reset(struct reloc_cache *cache)
} else {
struct i915_ggtt *ggtt = cache_to_ggtt(cache);
- intel_gt_flush_ggtt_writes(ggtt->vm.gt);
+ if (!cache->is_lmem)
+ intel_gt_flush_ggtt_writes(ggtt->vm.gt);
io_mapping_unmap_atomic((void __iomem *)vaddr);
- if (cache->node.allocated) {
+ if (cache->is_lmem) {
+ i915_gem_object_unpin_pages((struct drm_i915_gem_object
*)cache->node.mm);
+ cache->is_lmem = false;
+ } else if (cache->node.allocated) {
ggtt->vm.clear_range(>vm,
cache->node.start,
cache->node.size);
@@ -1066,6 +1073,42 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
return vaddr;
}
+static void *reloc_lmem(struct drm_i915_gem_object *obj,
+ struct reloc_cache *cache,
+ unsigned long page)
+{
+ void *vaddr;
+ int err;
+
+ GEM_BUG_ON(use_cpu_reloc(cache, obj));
+
+ if (cache->vaddr) {
+ io_mapping_unmap_atomic((void __force __iomem *)
unmask_page(cache->vaddr));
+ } else {
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return ERR_PTR(err);
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ i915_gem_object_unlock(obj);
+ if (err) {
+ i915_gem_object_unpin_pages(obj);
+ return ERR_PTR(err);
+ }
+
+ cache->node.mm = (void *)obj;
+ cache->is_lmem = true;
+ }
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, page);
+
+ cache->vaddr = (unsigned long)vaddr;
+ cache->page = page;
+
+ return vaddr;
+}
+
static void *reloc_iomap(struct drm_i915_gem_object *obj,
struct reloc_cache *cache,
unsigned long page)
@@ -1142,8 +1185,12 @@ static void *reloc_vaddr(struct drm_i915_gem_object *obj,
vaddr = unmask_page(cache->vaddr);
} else {
vaddr = NULL;
- if ((cache->vaddr & KMAP) == 0)
- vaddr = reloc_iomap(obj, cache, page);
+ if ((cache->vaddr & KMAP) == 0) {
+ if (i915_gem_object_is_lmem(obj))
+ vaddr = reloc_lmem(obj, cache, page);
+ else
+ vaddr = reloc_iomap(obj, cache, page);
+ }
if (!vaddr)
vaddr = reloc_kmap(obj, cache, page);
}
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 25/37] drm/i915/selftests: check for missing aperture
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 3 +++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
drivers/gpu/drm/i915/selftests/i915_gem.c | 3 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
5 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index a1a4b53cdc4a..42db49ff9b8e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -244,7 +244,10 @@ static bool always_valid(struct drm_i915_private *i915)
static bool needs_fence_registers(struct drm_i915_private *i915)
{
- return !intel_gt_is_wedged(>gt);
+ if (intel_gt_is_wedged(>gt))
+ return false;
+
+ return i915->ggtt.num_fences;
}
static bool needs_mi_store_dword(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 50aa7e95124d..fa83745abcc0 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -184,6 +184,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 4484b4447db1..233810da5387 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1179,8 +1179,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1217,10 +1221,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index bb6dd54a6ff3..0e62d5e07fcc 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -42,6 +42,9 @@ static void trash_stolen(struct drm_i915_private *i915)
unsigned long page;
u32 prng = 0x12345678;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return;
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 81850e3a7d2d..2b72276d4e97 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1147,6 +1147,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
mutex_lock(>drm.struct_mutex);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 24/37] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index bcac359ec661..bb7d9321cadf 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -808,8 +808,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(i915); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!HAS_MAPPABLE_APERTURE(i915)) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 18/37] drm/i915/lmem: support pwrite
We need to add support for pwrite'ing an LMEM object.
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 87
1 file changed, 87 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index f5a13994dc2a..f00078ac331e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -94,6 +94,92 @@ static int lmem_pread(struct drm_i915_gem_object *obj,
return ret;
}
+static int lmem_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *arg)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_runtime_pm *rpm = >runtime_pm;
+ intel_wakeref_t wakeref;
+ struct dma_fence *fence;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_lock(obj);
+ ret = i915_gem_object_set_to_wc_domain(obj, true);
+ if (ret) {
+ i915_gem_object_unlock(obj);
+ goto out_unpin;
+ }
+
+ fence = i915_gem_object_lock_fence(obj);
+ i915_gem_object_unlock(obj);
+ if (!fence) {
+ ret = -ENOMEM;
+ goto out_unpin;
+ }
+
+ wakeref = intel_runtime_pm_get(rpm);
+
+ remain = arg->size;
+ user_data = u64_to_user_ptr(arg->data_ptr);
+ offset = offset_in_page(arg->offset);
+ for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+
+ unwritten = __copy_from_user_inatomic_nocache((void
__force*)vaddr + offset,
+ user_data,
length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ unwritten = copy_from_user((void __force*)vaddr +
offset,
+ user_data, length);
+ io_mapping_unmap(vaddr);
+ }
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(rpm, wakeref);
+ i915_gem_object_unlock_fence(obj, fence);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
+
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.flags = I915_GEM_OBJECT_IS_MAPPABLE,
@@ -102,6 +188,7 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops
= {
.release = i915_gem_object_release_memory_region,
.pread = lmem_pread,
+ .pwrite = lmem_pwrite,
};
/* XXX: Time to vfunc your life up? */
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 13/37] drm/i915/selftests: move gpu-write-dw into utils
Using the gpu to write to some dword over a number of pages is rather
useful, and we already have two copies of such a thing, and we don't
want a third so move it to utils. There is probably some other stuff
also...
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 120 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 134 ++---
.../drm/i915/gem/selftests/igt_gem_utils.c| 135 ++
.../drm/i915/gem/selftests/igt_gem_utils.h| 16 +++
4 files changed, 169 insertions(+), 236 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 6ead53455c51..c36cef61ce3c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -952,126 +952,22 @@ static int igt_mock_ppgtt_64K(void *arg)
return err;
}
-static struct i915_vma *
-gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
-{
- struct drm_i915_private *i915 = vma->vm->i915;
- const int gen = INTEL_GEN(i915);
- unsigned int count = vma->size >> PAGE_SHIFT;
- struct drm_i915_gem_object *obj;
- struct i915_vma *batch;
- unsigned int size;
- u32 *cmd;
- int n;
- int err;
-
- size = (1 + 4 * count) * sizeof(u32);
- size = round_up(size, PAGE_SIZE);
- obj = i915_gem_object_create_internal(i915, size);
- if (IS_ERR(obj))
- return ERR_CAST(obj);
-
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
- if (IS_ERR(cmd)) {
- err = PTR_ERR(cmd);
- goto err;
- }
-
- offset += vma->node.start;
-
- for (n = 0; n < count; n++) {
- if (gen >= 8) {
- *cmd++ = MI_STORE_DWORD_IMM_GEN4;
- *cmd++ = lower_32_bits(offset);
- *cmd++ = upper_32_bits(offset);
- *cmd++ = val;
- } else if (gen >= 4) {
- *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
- (gen < 6 ? MI_USE_GGTT : 0);
- *cmd++ = 0;
- *cmd++ = offset;
- *cmd++ = val;
- } else {
- *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
- *cmd++ = offset;
- *cmd++ = val;
- }
-
- offset += PAGE_SIZE;
- }
-
- *cmd = MI_BATCH_BUFFER_END;
- intel_gt_chipset_flush(vma->vm->gt);
-
- i915_gem_object_unpin_map(obj);
-
- batch = i915_vma_instance(obj, vma->vm, NULL);
- if (IS_ERR(batch)) {
- err = PTR_ERR(batch);
- goto err;
- }
-
- err = i915_vma_pin(batch, 0, 0, PIN_USER);
- if (err)
- goto err;
-
- return batch;
-
-err:
- i915_gem_object_put(obj);
-
- return ERR_PTR(err);
-}
-
static int gpu_write(struct i915_vma *vma,
struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
-u32 dword,
-u32 value)
+u32 dw,
+u32 val)
{
- struct i915_request *rq;
- struct i915_vma *batch;
int err;
- GEM_BUG_ON(!intel_engine_can_store_dword(engine));
-
- batch = gpu_write_dw(vma, dword * sizeof(u32), value);
- if (IS_ERR(batch))
- return PTR_ERR(batch);
-
- rq = igt_request_alloc(ctx, engine);
- if (IS_ERR(rq)) {
- err = PTR_ERR(rq);
- goto err_batch;
- }
-
- i915_vma_lock(batch);
- err = i915_vma_move_to_active(batch, rq, 0);
- i915_vma_unlock(batch);
- if (err)
- goto err_request;
-
- i915_vma_lock(vma);
- err = i915_gem_object_set_to_gtt_domain(vma->obj, false);
- if (err == 0)
- err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
+ i915_gem_object_lock(vma->obj);
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ i915_gem_object_unlock(vma->obj);
if (err)
- goto err_request;
-
- err = engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
- 0);
-err_request:
- if (err)
- i915_request_skip(rq, err);
- i915_request_add(rq);
-err_batch:
- i915_vma_unpin(batch);
- i915_vma_close(batch);
- i915_vma_put(batch);
+ return err;
- return err;
+ return igt_gpu_fill_dw(vma, ctx, engine, dw * sizeof(u32),
+ vma->size >> PAGE_SHIFT, val);
}
static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
[PATCH v3 20/37] drm/i915: treat shmem as a region
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 68 ++-
drivers/gpu/drm/i915/i915_drv.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 13 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 29 +---
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
9 files changed, 99 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 768356908160..f0e5e0df00ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -16,6 +16,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
+#include "i915_gem_region.h"
#include "i915_scatterlist.h"
static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
@@ -191,8 +192,11 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj, int align)
/* Perma-pin (until release) the physical set of pages */
__i915_gem_object_pin_pages(obj);
- if (!IS_ERR_OR_NULL(pages))
+ if (!IS_ERR_OR_NULL(pages)) {
i915_gem_shmem_ops.put_pages(obj, pages);
+ /* XXX: where is the fput now though? */
+ i915_gem_object_release_memory_region(obj);
+ }
mutex_unlock(>mm.lock);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 0d09da9f7168..592012bb9b14 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_trace.h"
void
i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
@@ -143,11 +144,22 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
GEM_BUG_ON(!size);
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
+ /*
+* There is a prevalence of the assumption that we fit the object's
+* page count inside a 32bit _signed_ variable. Let's document this and
+* catch if we ever need to fix it. In the meantime, if you do spot
+* such a local variable, please consider fixing!
+*/
+
if (size >> PAGE_SHIFT > INT_MAX)
return ERR_PTR(-E2BIG);
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
- return mem->ops->create_object(mem, size, flags);
+ obj = mem->ops->create_object(mem, size, flags);
+ if (!IS_ERR(obj))
+ trace_i915_gem_object_create(obj);
+
+ return obj;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 9f5d903f7793..ac7a552349b4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -7,7 +7,9 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_gemfs.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
@@ -26,6 +28,7 @@ static void check_release_pagevec(struct pagevec *pvec)
static int shmem_get_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->mm.region;
const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned long i;
struct address_space *mapping;
@@ -52,7 +55,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (page_count > totalram_pages())
+ if (obj->base.size > resource_size(>region))
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
@@ -417,6 +420,8 @@ shmem_pwrite(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
+ i915_gem_object_release_memory_region(obj);
+
fput(obj->base.filp);
}
@@ -435,7 +440,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.release = shmem_release,
};
-static int create_shmem(struct drm_i915_private *i915,
+static int __create_shmem(struct drm_i915_private *i915,
struct drm_gem_object *obj,
size_t size)
{
@@ -456,31 +461,23 @@ static int create_shmem(struct drm_i915_private *i915,
return 0;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
+static struct drm_i915_gem_object *
+create_shmem(struct intel_memory_region
[PATCH v3 22/37] drm/i915: define HAS_MAPPABLE_APERTURE
From: Daniele Ceraolo Spurio The following patches in the series will use it to avoid certain operations when aperture is not available in HW. Signed-off-by: Daniele Ceraolo Spurio Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f94f1f3ccaa..182ed6b46aa5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2168,6 +2168,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ (INTEL_INFO(dev_priv)->display.overlay_needs_physical) +#define HAS_MAPPABLE_APERTURE(dev_priv) (dev_priv->ggtt.mappable_end > 0) + /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv)(IS_I830(dev_priv) || IS_I845G(dev_priv)) -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 28/37] drm/i915: check for missing aperture in insert_mappable_node
From: CQ Tang
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2aa4fbe7edc0..af63d1a0af14 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -64,6 +64,9 @@ static int
insert_mappable_node(struct i915_ggtt *ggtt,
struct drm_mm_node *node, u32 size)
{
+ if (!ggtt->mappable_end)
+ return -ENOSPC;
+
memset(node, 0, sizeof(*node));
return drm_mm_insert_node_in_range(>vm.mm, node,
size, 0, I915_COLOR_UNEVICTABLE,
--
2.20.1
___
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[PATCH v3 17/37] drm/i915/lmem: support pread
We need to add support for pread'ing an LMEM object.
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 88 +++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 6 ++
3 files changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 8d957135afa4..f5a13994dc2a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -8,12 +8,100 @@
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
+static int lmem_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *arg)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_runtime_pm *rpm = >runtime_pm;
+ intel_wakeref_t wakeref;
+ struct dma_fence *fence;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_lock(obj);
+ ret = i915_gem_object_set_to_wc_domain(obj, false);
+ if (ret) {
+ i915_gem_object_unlock(obj);
+ goto out_unpin;
+ }
+
+ fence = i915_gem_object_lock_fence(obj);
+ i915_gem_object_unlock(obj);
+ if (!fence) {
+ ret = -ENOMEM;
+ goto out_unpin;
+ }
+
+ wakeref = intel_runtime_pm_get(rpm);
+
+ remain = arg->size;
+ user_data = u64_to_user_ptr(arg->data_ptr);
+ offset = offset_in_page(arg->offset);
+ for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+ unwritten = __copy_to_user_inatomic(user_data,
+ (void __force *)vaddr +
offset,
+ length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ unwritten = copy_to_user(user_data,
+(void __force *)vaddr + offset,
+length);
+ io_mapping_unmap(vaddr);
+ }
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(rpm, wakeref);
+ i915_gem_object_unlock_fence(obj, fence);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.flags = I915_GEM_OBJECT_IS_MAPPABLE,
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
+
+ .pread = lmem_pread,
};
/* XXX: Time to vfunc your life up? */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 19c3f9804b68..cd06051eb797 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -53,6 +53,8 @@ struct drm_i915_gem_object_ops {
void (*truncate)(struct drm_i915_gem_object *obj);
void (*writeback)(struct drm_i915_gem_object *obj);
+ int (*pread)(struct drm_i915_gem_object *,
+const struct drm_i915_gem_pread *arg);
int (*pwrite)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *arg);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8735dea74809..96e143d133d1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -465,6 +465,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
trace_i915_gem_object_pread(obj, args->offset, args->size);
+ ret = -ENODEV;
+ if (obj->ops->pread)
+ ret = obj->ops->pread(obj,
[PATCH v3 23/37] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++---
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5bcf71b18e5f..dd28c54527e3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2795,8 +2795,10 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
mutex_unlock(>drm.struct_mutex);
- arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(>iomap);
+ if (HAS_MAPPABLE_APERTURE(i915)) {
+ arch_phys_wc_del(ggtt->mtrr);
+ io_mapping_fini(>iomap);
+ }
}
/**
@@ -2992,10 +2994,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(>gmadr);
+ /* FIXME: We probably need to add do device_info or runtime_info */
+ if (!HAS_LMEM(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(>gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3220,15 +3225,18 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
- if (!io_mapping_init_wc(>iomap,
- ggtt->gmadr.start,
- ggtt->mappable_end)) {
- ggtt->vm.cleanup(>vm);
- ret = -EIO;
- goto out;
- }
+ if (HAS_MAPPABLE_APERTURE(i915)) {
+ if (!io_mapping_init_wc(>iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt->vm.cleanup(>vm);
+ ret = -EIO;
+ goto out;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
i915_ggtt_init_fences(ggtt);
--
2.20.1
___
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[PATCH v3 19/37] drm/i915: enumerate and init each supported region
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
3 files changed, 72 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7be8cee4709..3d7da69f0d1b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2436,6 +2436,9 @@ int __must_check i915_gem_evict_for_node(struct
i915_address_space *vm,
unsigned int flags);
int i915_gem_evict_vm(struct i915_address_space *vm);
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
+int i915_gem_init_memory_regions(struct drm_i915_private *i915);
+
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 83a02e773c58..a1dd3e7e1ad9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2713,6 +2713,66 @@ int i915_init_ggtt(struct drm_i915_private *i915)
return 0;
}
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
+{
+ int i;
+
+ i915_gem_cleanup_stolen(i915);
+
+ for (i = 0; i < ARRAY_SIZE(i915->regions); ++i) {
+ struct intel_memory_region *region = i915->regions[i];
+
+ if (region)
+ intel_memory_region_destroy(region);
+ }
+}
+
+int i915_gem_init_memory_regions(struct drm_i915_private *i915)
+{
+ int err, i;
+
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ /* XXX: stolen will become a region at some point */
+ err = i915_gem_init_stolen(i915);
+ if (err)
+ return err;
+
+ for (i = 0; i < INTEL_MEMORY_UKNOWN; i++) {
+ struct intel_memory_region *mem = NULL;
+ u32 type;
+
+ if (!HAS_REGION(i915, BIT(i)))
+ continue;
+
+ type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
+ switch (type) {
+ default:
+ break;
+ }
+
+ if (IS_ERR(mem)) {
+ err = PTR_ERR(mem);
+ DRM_ERROR("Failed to setup region(%d) type=%d\n", err,
type);
+ goto out_cleanup;
+ }
+
+ mem->id = intel_region_map[i];
+ mem->type = type;
+ mem->instance =
MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
+
+ i915->regions[i] = mem;
+ }
+
+ return 0;
+
+out_cleanup:
+ i915_gem_cleanup_memory_regions(i915);
+ return err;
+}
+
static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
@@ -2754,6 +2814,8 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
{
struct pagevec *pvec;
+ i915_gem_cleanup_memory_regions(i915);
+
fini_aliasing_ppgtt(>ggtt);
ggtt_cleanup_hw(>ggtt);
@@ -2763,8 +2825,6 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
set_pages_array_wb(pvec->pages, pvec->nr);
__pagevec_release(pvec);
}
-
- i915_gem_cleanup_stolen(i915);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3204,11 +3264,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- ret = i915_gem_init_stolen(dev_priv);
+ ret = i915_gem_init_memory_regions(dev_priv);
if (ret)
goto out_gtt_cleanup;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index cc0fe0a79330..c6944e17a2c5 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -82,6 +82,8 @@ static void mock_device_release(struct drm_device *dev)
i915_gemfs_fini(i915);
+ i915_gem_cleanup_memory_regions(i915);
+
drm_mode_config_cleanup(>drm);
drm_dev_fini(>drm);
@@ -219,6 +221,10 @@ struct drm_i915_private *mock_gem_device(void)
WARN_ON(i915_gemfs_init(i915));
+ err = i915_gem_init_memory_regions(i915);
+ if (err)
+ goto err_context;
+
return i915;
err_context:
--
2.20.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
[PATCH v3 14/37] drm/i915/selftests: add write-dword test for LMEM
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 179 ++
1 file changed, 179 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 2570fa93e286..4123e81a2bda 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -7,6 +7,7 @@
#include "../i915_selftest.h"
+
#include "mock_drm.h"
#include "mock_gem_device.h"
#include "mock_region.h"
@@ -14,9 +15,11 @@
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
+#include "selftests/i915_random.h"
static void close_objects(struct list_head *objects)
{
@@ -354,6 +357,128 @@ static int igt_mock_volatile(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct i915_vma *vma,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ u32 dword,
+ u32 value)
+{
+ int err;
+
+ i915_gem_object_lock(vma->obj);
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ i915_gem_object_unlock(vma->obj);
+ if (err)
+ return err;
+
+ return igt_gpu_fill_dw(vma, ctx, engine, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct i915_address_space *vm = ctx->vm ?: >ggtt.vm;
+ static struct intel_engine_cs *engines[I915_NUM_ENGINES];
+ struct intel_engine_cs *engine;
+ IGT_TIMEOUT(end_time);
+ I915_RND_STATE(prng);
+ struct i915_vma *vma;
+ unsigned int id;
+ int *order;
+ int i, n;
+ int err;
+
+ n = 0;
+ for_each_engine(engine, i915, id) {
+ if (!intel_engine_can_store_dword(engine)) {
+ pr_info("store-dword-imm not supported on engine=%u\n",
+ id);
+ continue;
+ }
+ engines[n++] = engine;
+ }
+
+ if (!n)
+ return 0;
+
+ order = i915_random_order(n * I915_NUM_ENGINES, );
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ do {
+ u32 rng = prandom_u32_state();
+ u32 dword = offset_in_page(rng) / 4;
+
+ engine = engines[order[i] % n];
+ i = (i + 1) % (n * I915_NUM_ENGINES);
+
+ err = igt_gpu_write_dw(vma, ctx, engine, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+
+ i915_vma_unpin(vma);
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -375,6 +500,59 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+
[PATCH v3 04/37] drm/i915/region: support continuous allocations
Some objects may need to be allocated as a continuous block, thinking
ahead the various kernel io_mapping interfaces seem to expect it.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 10 +-
drivers/gpu/drm/i915/gem/i915_gem_region.h| 3 +-
.../drm/i915/selftests/intel_memory_region.c | 152 +-
drivers/gpu/drm/i915/selftests/mock_region.c | 5 +-
5 files changed, 166 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 5e2fa37e9bc0..eb92243d473b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -116,6 +116,10 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
+ unsigned long flags;
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index be126e70c90f..d9cd722b5dbf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -42,6 +42,9 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
return -ENOMEM;
}
+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
+ flags = I915_ALLOC_CONTIGUOUS;
+
ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
if (ret)
goto err_free_sg;
@@ -98,10 +101,12 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
}
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem)
+ struct intel_memory_region *mem,
+ unsigned long flags)
{
INIT_LIST_HEAD(>mm.blocks);
obj->mm.region= mem;
+ obj->flags = flags;
mutex_lock(>obj_lock);
list_add(>mm.region_link, >objects);
@@ -125,6 +130,9 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
if (!mem)
return ERR_PTR(-ENODEV);
+ if (flags & ~I915_BO_ALLOC_FLAGS)
+ return ERR_PTR(-EINVAL);
+
size = round_up(size, mem->min_page_size);
GEM_BUG_ON(!size);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index ebddc86d78f7..f2ff6f8bff74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -17,7 +17,8 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
struct sg_table *pages);
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem);
+ struct intel_memory_region *mem,
+ unsigned long flags);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 2f13e4c1d999..70b467d4e811 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -81,17 +81,17 @@ static int igt_mock_fill(void *arg)
static void igt_mark_evictable(struct drm_i915_gem_object *obj)
{
- i915_gem_object_unpin_pages(obj);
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
obj->mm.madv = I915_MADV_DONTNEED;
list_move(>mm.region_link, >mm.region->purgeable);
}
-static int igt_mock_shrink(void *arg)
+static int igt_frag_region(struct intel_memory_region *mem,
+ struct list_head *objects)
{
- struct intel_memory_region *mem = arg;
struct drm_i915_gem_object *obj;
unsigned long n_objects;
- LIST_HEAD(objects);
resource_size_t target;
resource_size_t total;
int err = 0;
@@ -109,7 +109,7 @@ static int igt_mock_shrink(void *arg)
goto err_close_objects;
}
- list_add(>st_link, );
+ list_add(>st_link, objects);
err = i915_gem_object_pin_pages(obj);
if (err)
@@ -123,6 +123,39 @@ static int igt_mock_shrink(void *arg)
igt_mark_evictable(obj);
}
+ return 0;
+
+err_close_objects:
+ close_objects(objects);
+ return err;
+}
+
+static
[PATCH v3 12/37] drm/i915/blt: support copying objects
We can already clear an object with the blt, so try to do the same to
support copying from one object backing store to another. Really this is
just object -> object, which is not that useful yet, what we really want
is two backing stores, but that will require some vma rework first,
otherwise we are stuck with "tmp" objects.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue vm->i915;
+ const u32 block_size = S16_MAX * PAGE_SIZE;
+ struct intel_engine_pool_node *pool;
+ struct i915_vma *batch;
+ u64 src_offset, dst_offset;
+ u64 count;
+ u64 rem;
+ u32 size;
+ u32 *cmd;
+ int err;
+
+ GEM_BUG_ON(src->size != dst->size);
+
+ count = div_u64(dst->size, block_size);
+ size = (1 + 11 * count) * sizeof(u32);
+ size = round_up(size, PAGE_SIZE);
+ pool = intel_engine_pool_get(>engine->pool, size);
+ if (IS_ERR(pool))
+ return ERR_CAST(pool);
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto out_put;
+ }
+
+ rem = src->size;
+ src_offset = src->node.start;
+ dst_offset = dst->node.start;
+
+ do {
+ u32 size = min_t(u64, rem, block_size);
+
+ GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
+
+ if (INTEL_GEN(i915) >= 9) {
+ *cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
+ *cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst_offset);
+ *cmd++ = upper_32_bits(dst_offset);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src_offset);
+ *cmd++ = upper_32_bits(src_offset);
+ } else if (INTEL_GEN(i915) >= 8) {
+ *cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 -
2);
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst_offset);
+ *cmd++ = upper_32_bits(dst_offset);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src_offset);
+ *cmd++ = upper_32_bits(src_offset);
+ } else {
+ *cmd++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;
+ *cmd++ = dst_offset;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = src_offset;
+ }
+
+ /* Allow ourselves to be preempted in between blocks. */
+ *cmd++ = MI_ARB_CHECK;
+
+ src_offset += size;
+ dst_offset += size;
+ rem -= size;
+ } while (rem);
+
+ *cmd = MI_BATCH_BUFFER_END;
+ intel_gt_chipset_flush(ce->vm->gt);
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_put;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out_put;
+
+ *p = pool;
+ return batch;
+
+out_put:
+ intel_engine_pool_put(pool);
+ return ERR_PTR(err);
+}
+
+int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
+struct drm_i915_gem_object *dst,
+struct intel_context *ce)
+{
+ struct drm_gem_object *objs[] = { >base, >base };
+ struct i915_address_space *vm = ce->vm;
+ struct intel_engine_pool_node *pool;
+ struct ww_acquire_ctx acquire;
+ struct i915_vma *vma_src, *vma_dst;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ int err;
+
+ vma_src = i915_vma_instance(src, vm, NULL);
+ if (IS_ERR(vma_src))
+ return PTR_ERR(vma_src);
+
+ err = i915_vma_pin(vma_src, 0, 0, PIN_USER);
+ if (unlikely(err))
+ return err;
+
+ vma_dst = i915_vma_instance(dst, vm, NULL);
+ if (IS_ERR(vma_dst))
+ goto out_unpin_src;
+
+ err = i915_vma_pin(vma_dst, 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out_unpin_src;
+
+ intel_engine_pm_get(ce->engine);
+ batch = intel_emit_vma_copy_blt(, ce, vma_src, vma_dst);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_unpin_dst;
+ }
+
+
[PATCH v3 11/37] drm/i915/blt: bump size restriction
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 31 +++-
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 139 ++
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 9 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
.../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
5 files changed, 170 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 08a84c940d8d..4b096309a97e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -5,6 +5,8 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -156,7 +158,9 @@ static void clear_pages_worker(struct work_struct *work)
struct drm_i915_private *i915 = w->ce->engine->i915;
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
+ struct intel_engine_pool_node *pool;
struct i915_request *rq;
+ struct i915_vma *batch;
int err = w->dma.error;
if (unlikely(err))
@@ -176,10 +180,17 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
+ intel_engine_pm_get(w->ce->engine);
+ batch = intel_emit_vma_fill_blt(, w->ce, vma, w->value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_unpin;
+ }
+
rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto out_unpin;
+ goto out_batch;
}
/* There's no way the fence has signalled */
@@ -187,6 +198,16 @@ static void clear_pages_worker(struct work_struct *work)
clear_pages_dma_fence_cb))
GEM_BUG_ON(1);
+ i915_vma_lock(batch);
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (unlikely(err))
+ goto out_request;
+
+ err = intel_engine_pool_mark_active(pool, rq);
+ if (unlikely(err))
+ goto out_request;
+
if (w->ce->engine->emit_init_breadcrumb) {
err = w->ce->engine->emit_init_breadcrumb(rq);
if (unlikely(err))
@@ -202,7 +223,9 @@ static void clear_pages_worker(struct work_struct *work)
if (err)
goto out_request;
- err = intel_emit_vma_fill_blt(rq, vma, w->value);
+ err = w->ce->engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
out_request:
if (unlikely(err)) {
i915_request_skip(rq, err);
@@ -210,7 +233,11 @@ static void clear_pages_worker(struct work_struct *work)
}
i915_request_add(rq);
+out_batch:
+ i915_vma_unpin(batch);
+ intel_engine_pool_put(pool);
out_unpin:
+ intel_engine_pm_put(w->ce->engine);
i915_vma_unpin(vma);
out_unlock:
mutex_unlock(>drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index fa90c38c8b07..c1e5edd1e359 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -5,49 +5,103 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
+#include "gt/intel_gt.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
-int intel_emit_vma_fill_blt(struct i915_request *rq,
- struct i915_vma *vma,
- u32 value)
+struct i915_vma *intel_emit_vma_fill_blt(struct intel_engine_pool_node **p,
+struct intel_context *ce,
+struct i915_vma *vma,
+u32 value)
{
- u32 *cs;
-
- cs = intel_ring_begin(rq, 8);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- if (INTEL_GEN(rq->i915) >= 8) {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
- *cs++ = value;
- *cs++ = MI_NOOP;
- } else {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->size >>
[PATCH v3 10/37] drm/i915/blt: don't assume pinned intel_context
Currently we just pass in bcs0->engine_context so it matters not, but in
the future we may want to pass in something that is not a
kernel_context, so try to be a bit more generic.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_client_blt.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index de6616bdb3a6..08a84c940d8d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -175,7 +176,7 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
- rq = i915_request_create(w->ce);
+ rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 837dd6636dd1..fa90c38c8b07 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
@@ -64,7 +65,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
i915_gem_object_unlock(obj);
}
- rq = i915_request_create(ce);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
--
2.20.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 07/37] drm/i915: support creating LMEM objects
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 31
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 23 +
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 48 +++
drivers/gpu/drm/i915/intel_region_lmem.h | 11 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 45 +
8 files changed, 166 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e9cf87696bde..17394fd0c7f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -112,6 +112,7 @@ gem-y += \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
+ gem/i915_gem_lmem.o \
gem/i915_gem_mman.o \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
@@ -140,6 +141,7 @@ i915-y += \
i915_scheduler.o \
i915_trace_points.o \
i915_vma.o \
+ intel_region_lmem.o \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
new file mode 100644
index ..ac5a15db1d27
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
+#include "i915_drv.h"
+
+const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .get_pages = i915_gem_object_get_pages_buddy,
+ .put_pages = i915_gem_object_put_pages_buddy,
+ .release = i915_gem_object_release_memory_region,
+};
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *region = obj->mm.region;
+
+ return region && region->type == INTEL_LMEM;
+}
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags)
+{
+ return i915_gem_object_create_region(i915->regions[INTEL_MEMORY_LMEM],
+size, flags);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
new file mode 100644
index ..ebc15fe24f58
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __I915_GEM_LMEM_H
+#define __I915_GEM_LMEM_H
+
+#include
+
+struct drm_i915_private;
+struct drm_i915_gem_object;
+
+extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags);
+
+#endif /* !__I915_GEM_LMEM_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d947f7415861..f7be8cee4709 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -98,6 +98,8 @@
#include "i915_vma.h"
#include "i915_irq.h"
+#include "intel_region_lmem.h"
+
#include "intel_gvt.h"
/* General customization:
@@ -1369,6 +1371,8 @@ struct drm_i915_private {
*/
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
+ struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
+
struct intel_uncore uncore;
struct i915_virtual_gpu vgpu;
@@ -2213,6 +2217,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
new file mode 100644
index ..ca906d1ff631
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
[PATCH v3 00/37] Introduce memory region concept (including device local memory)
In preparation for upcoming devices with device local memory, introduce the concept of different memory regions, and a simple buddy allocator to manage them in i915. One of the concerns raised from v1 was around not using enough of TTM, which is a fair criticism, so trying to get better alignment here is something we are investigating, though currently that is still WIP so in the meantime v3 still continues to push more of the low-level details forward, but not yet the TTM interactions. Sidenote: Daniel raised a fair point with the whole mmap_offset uAPI and whether we can just get away with using gtt_mmap, it looks like it should work and would simplify a few things and possibly allow us to drop a couple patches. Thoughts? Abdiel Janulgue (11): drm/i915: Add memory region information to device_info drm/i915: setup io-mapping for LMEM drm/i915/lmem: support kernel mapping drm/i915: enumerate and init each supported region drm/i915: Allow i915 to manage the vma offset nodes instead of drm core drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET drm/i915/lmem: add helper to get CPU accessible offset drm/i915: Add cpu and lmem fault handlers drm/i915: cpu-map based dumb buffers drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION drm/i915/query: Expose memory regions through the query uAPI CQ Tang (1): drm/i915: check for missing aperture in insert_mappable_node Daniele Ceraolo Spurio (4): drm/i915: define HAS_MAPPABLE_APERTURE drm/i915: do not map aperture if it is not available. drm/i915: set num_fence_regs to 0 if there is no aperture drm/i915: error capture with no ggtt slot Matthew Auld (20): drm/i915: buddy allocator drm/i915: introduce intel_memory_region drm/i915/region: support basic eviction drm/i915/region: support continuous allocations drm/i915/region: support volatile objects drm/i915: support creating LMEM objects drm/i915/blt: don't assume pinned intel_context drm/i915/blt: bump size restriction drm/i915/blt: support copying objects drm/i915/selftests: move gpu-write-dw into utils drm/i915/selftests: add write-dword test for LMEM drm/i915/selftest: extend coverage to include LMEM huge-pages drm/i915/lmem: support CPU relocations drm/i915/lmem: support pread drm/i915/lmem: support pwrite drm/i915: treat shmem as a region drm/i915: treat stolen as a region drm/i915/selftests: check for missing aperture drm/i915: support basic object migration HAX drm/i915: add the fake lmem region Michal Wajdeczko (1): drm/i915: Don't try to place HWS in non-existing mappable region arch/x86/kernel/early-quirks.c| 26 + drivers/gpu/drm/i915/Makefile | 5 + .../gpu/drm/i915/gem/i915_gem_client_blt.c| 34 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 + drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 55 +- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 4 + drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 315 +++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 37 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 376 +++- drivers/gpu/drm/i915/gem/i915_gem_object.c| 271 ++ drivers/gpu/drm/i915/gem/i915_gem_object.h| 29 +- .../gpu/drm/i915/gem/i915_gem_object_blt.c| 349 +++- .../gpu/drm/i915/gem/i915_gem_object_blt.h| 18 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 48 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 28 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_region.c| 165 drivers/gpu/drm/i915/gem/i915_gem_region.h| 29 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 71 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 71 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 3 +- .../drm/i915/gem/selftests/huge_gem_object.c | 4 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 331 --- .../i915/gem/selftests/i915_gem_client_blt.c | 16 +- .../i915/gem/selftests/i915_gem_coherency.c | 5 +- .../drm/i915/gem/selftests/i915_gem_context.c | 134 +-- .../drm/i915/gem/selftests/i915_gem_mman.c| 15 +- .../i915/gem/selftests/i915_gem_object_blt.c | 128 ++- .../drm/i915/gem/selftests/igt_gem_utils.c| 135 +++ .../drm/i915/gem/selftests/igt_gem_utils.h| 16 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 5 +- drivers/gpu/drm/i915/gt/intel_reset.c | 13 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 2 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 +- drivers/gpu/drm/i915/i915_buddy.c | 433 ++ drivers/gpu/drm/i915/i915_buddy.h | 128 +++ drivers/gpu/drm/i915/i915_drv.c | 28 +- drivers/gpu/drm/i915/i915_drv.h | 20 +- drivers/gpu/drm/i915/i915_gem.c | 41
[PATCH v3 09/37] drm/i915/lmem: support kernel mapping
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 20 -
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../drm/i915/selftests/intel_memory_region.c | 76 +++
9 files changed, 152 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 5e72cb1cc2d3..c2e237702e8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -140,7 +140,9 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
-I915_GEM_OBJECT_IS_SHRINKABLE,
+I915_GEM_OBJECT_IS_SHRINKABLE |
+I915_GEM_OBJECT_IS_MAPPABLE,
+
.get_pages = i915_gem_object_get_pages_internal,
.put_pages = i915_gem_object_put_pages_internal,
};
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index ac5a15db1d27..8d957135afa4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -9,11 +9,47 @@
#include "i915_drv.h"
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .flags = I915_GEM_OBJECT_IS_MAPPABLE,
+
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(>mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(>mm.region->iomap, offset);
+}
+
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(>mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->mm.region;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ebc15fe24f58..31a6462bdbb6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -13,6 +13,14 @@ struct drm_i915_gem_object;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n, unsigned long size);
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 1af838050d6c..1cbc63470212 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -158,6 +158,12 @@ i915_gem_object_is_proxy(const struct drm_i915_gem_object
*obj)
return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
}
+static inline bool
+i915_gem_object_is_mappable(const struct drm_i915_gem_object *obj)
+{
+ return obj->ops->flags & I915_GEM_OBJECT_IS_MAPPABLE;
+}
+
static inline bool
i915_gem_object_needs_async_cancel(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
[PATCH v3 02/37] drm/i915: introduce intel_memory_region
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of course device. At some point we are probably going to want
use a common struct here, such that we are better aligned with say TTM.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Niranjana Vishwanathapura
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 2 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 129 +
drivers/gpu/drm/i915/gem/i915_gem_region.h| 27 +++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 78
drivers/gpu/drm/i915/i915_buddy.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_memory_region.c| 175 ++
drivers/gpu/drm/i915/intel_memory_region.h| 107 +++
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 114
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
drivers/gpu/drm/i915/selftests/mock_region.c | 60 ++
drivers/gpu/drm/i915/selftests/mock_region.h | 16 ++
14 files changed, 722 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3962d9728dd7..e9cf87696bde 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,6 +50,7 @@ i915-y += i915_drv.o \
i915_utils.o \
intel_csr.o \
intel_device_info.o \
+ intel_memory_region.o \
intel_pch.o \
intel_pm.o \
intel_runtime_pm.o \
@@ -115,6 +116,7 @@ gem-y += \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
gem/i915_gem_pm.o \
+ gem/i915_gem_region.o \
gem/i915_gem_shmem.o \
gem/i915_gem_shrinker.o \
gem/i915_gem_stolen.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index d474c6ac4100..a32066e66271 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -160,6 +160,15 @@ struct drm_i915_gem_object {
struct mutex lock; /* protects the pages and their use */
atomic_t pages_pin_count;
+ /**
+* Memory region for this object.
+*/
+ struct intel_memory_region *region;
+ /**
+* List of memory region blocks allocated for this object.
+*/
+ struct list_head blocks;
+
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
new file mode 100644
index ..3cd1bf15e25b
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "i915_gem_region.h"
+#include "i915_drv.h"
+
+void
+i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ __intel_memory_region_put_pages_buddy(obj->mm.region, >mm.blocks);
+
+ obj->mm.dirty = false;
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = >mm.blocks;
+ resource_size_t size = obj->base.size;
+ resource_size_t prev_end;
+ struct i915_buddy_block *block;
+ unsigned int flags = 0;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_page_sizes;
+ unsigned long i;
+ int ret;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size), GFP_KERNEL)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
+ if (ret)
+ goto err_free_sg;
+
+ GEM_BUG_ON(list_empty(blocks));
+
+ sg = st->sgl;
+
[PATCH v3 08/37] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index ca906d1ff631..7f1543e2759c 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -41,8 +41,32 @@ lmem_create_object(struct intel_memory_region *mem,
return obj;
}
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(>iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(>iomap,
+ mem->io_start,
+ resource_size(>region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(>iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = lmem_create_object,
};
--
2.20.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 06/37] drm/i915: Add memory region information to device_info
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39cdf4eac2a6..d947f7415861 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2212,6 +2212,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 92e0c2e0954c..3166f38910f7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -159,6 +159,8 @@ struct intel_device_info {
unsigned int page_sizes; /* page sizes supported by the HW */
+ u32 memory_regions; /* regions supported by the HW */
+
u32 display_mmio_offset;
u8 num_pipes;
--
2.20.1
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 03/37] drm/i915/region: support basic eviction
Support basic eviction for regions.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 7 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c| 11 +++
drivers/gpu/drm/i915/gem/i915_gem_region.h| 1 +
drivers/gpu/drm/i915/i915_gem.c | 17 +
drivers/gpu/drm/i915/intel_memory_region.c| 73 +-
drivers/gpu/drm/i915/intel_memory_region.h| 5 ++
.../drm/i915/selftests/intel_memory_region.c | 76 +++
drivers/gpu/drm/i915/selftests/mock_region.c | 1 +
8 files changed, 187 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a32066e66271..5e2fa37e9bc0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -168,6 +168,13 @@ struct drm_i915_gem_object {
* List of memory region blocks allocated for this object.
*/
struct list_head blocks;
+ /**
+* Element within memory_region->objects or
+* memory_region->purgeable if the object is marked as
+* DONTNEED. Access is protected by memory_region->obj_lock.
+*/
+ struct list_head region_link;
+ struct list_head tmp_link;
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 3cd1bf15e25b..be126e70c90f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -102,6 +102,17 @@ void i915_gem_object_init_memory_region(struct
drm_i915_gem_object *obj,
{
INIT_LIST_HEAD(>mm.blocks);
obj->mm.region= mem;
+
+ mutex_lock(>obj_lock);
+ list_add(>mm.region_link, >objects);
+ mutex_unlock(>obj_lock);
+}
+
+void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj)
+{
+ mutex_lock(>mm.region->obj_lock);
+ list_del(>mm.region_link);
+ mutex_unlock(>mm.region->obj_lock);
}
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index da5a2ca1a0fb..ebddc86d78f7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -18,6 +18,7 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
struct intel_memory_region *mem);
+void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
i915_gem_object_create_region(struct intel_memory_region *mem,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6ff01a404346..8735dea74809 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1105,6 +1105,23 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
*data,
!i915_gem_object_has_pages(obj))
i915_gem_object_truncate(obj);
+ if (obj->mm.region) {
+ mutex_lock(>mm.region->obj_lock);
+
+ switch (obj->mm.madv) {
+ case I915_MADV_WILLNEED:
+ list_move(>mm.region_link,
+ >mm.region->objects);
+ break;
+ default:
+ list_move(>mm.region_link,
+ >mm.region->purgeable);
+ break;
+ }
+
+ mutex_unlock(>mm.region->obj_lock);
+ }
+
args->retained = obj->mm.madv != __I915_MADV_PURGED;
mutex_unlock(>mm.lock);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index ef12e462acb8..3a3caaadea1f 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -12,6 +12,51 @@ const u32 intel_region_map[] = {
[INTEL_MEMORY_STOLEN] = BIT(INTEL_STOLEN + INTEL_MEMORY_TYPE_SHIFT) |
BIT(0),
};
+static int
+intel_memory_region_evict(struct intel_memory_region *mem,
+ resource_size_t target,
+ unsigned int flags)
+{
+ struct drm_i915_gem_object *obj;
+ resource_size_t found;
+ int err;
+
+ err = 0;
+ found = 0;
+
+ mutex_lock(>obj_lock);
+ list_for_each_entry(obj, >purgeable, mm.region_link) {
+ if (!i915_gem_object_has_pages(obj))
+ continue;
+
+ if (READ_ONCE(obj->pin_global))
+ continue;
+
+ if (atomic_read(>bind_count))
+ continue;
+
+
[PATCH v3 05/37] drm/i915/region: support volatile objects
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 17 +++---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c| 7 ++-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 12 ++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 +-
.../drm/i915/selftests/intel_memory_region.c | 56 +++
8 files changed, 91 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 0c41e04ab8fa..5e72cb1cc2d3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -117,13 +117,6 @@ static int i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
goto err;
}
- /* Mark the pages as dontneed whilst they are still pinned. As soon
-* as they are unpinned they are allowed to be reaped by the shrinker,
-* and the caller is expected to repopulate - the contents of this
-* object are only valid whilst active and pinned.
-*/
- obj->mm.madv = I915_MADV_DONTNEED;
-
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -143,7 +136,6 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
internal_free_pages(pages);
obj->mm.dirty = false;
- obj->mm.madv = I915_MADV_WILLNEED;
}
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
@@ -188,6 +180,15 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
drm_gem_private_object_init(>drm, >base, size);
i915_gem_object_init(obj, _gem_object_internal_ops);
+ /*
+* Mark the object as volatile, such that the pages are marked as
+* dontneed whilst they are still pinned. As soon as they are unpinned
+* they are allowed to be reaped by the shrinker, and the caller is
+* expected to repopulate - the contents of this object are only valid
+* whilst active and pinned.
+*/
+ obj->flags = I915_BO_ALLOC_VOLATILE;
+
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3714cf234d64..1af838050d6c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -122,6 +122,12 @@ i915_gem_object_lock_fence(struct drm_i915_gem_object
*obj);
void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
struct dma_fence *fence);
+static inline bool
+i915_gem_object_is_volatile(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_VOLATILE;
+}
+
static inline void
i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index eb92243d473b..2142d74a57ea 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -118,7 +118,8 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
/*
* Is the object to be mapped as read-only to the GPU
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 18f0ce0135c1..d3f0debdb875 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -18,6 +18,9 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
lockdep_assert_held(>mm.lock);
+ if (i915_gem_object_is_volatile(obj))
+ obj->mm.madv = I915_MADV_DONTNEED;
+
/* Make the pages coherent with the GPU (flushing any swapin). */
if (obj->cache_dirty) {
obj->write_domain = 0;
@@ -159,6 +162,9 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
if (IS_ERR_OR_NULL(pages))
return pages;
+ if (i915_gem_object_is_volatile(obj))
+ obj->mm.madv = I915_MADV_WILLNEED;
+
i915_gem_object_make_unshrinkable(obj);
if (obj->mm.mapping) {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index d9cd722b5dbf..0d09da9f7168 100644
---
[PATCH v3 01/37] drm/i915: buddy allocator
Simple buddy allocator. We want to allocate properly aligned
power-of-two blocks to promote usage of huge-pages for the GTT, so 64K,
2M and possibly even 1G. While we do support allocating stuff at a
specific offset, it is more intended for preallocating portions of the
address space, say for an initial framebuffer, for other uses drm_mm is
probably a much better fit. Anyway, hopefully this can all be thrown
away if we eventually move to having the core MM manage device memory.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_buddy.c | 433 +++
drivers/gpu/drm/i915/i915_buddy.h | 126 +++
drivers/gpu/drm/i915/i915_globals.c | 1 +
drivers/gpu/drm/i915/i915_globals.h | 1 +
drivers/gpu/drm/i915/selftests/i915_buddy.c | 719 ++
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
7 files changed, 1282 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_buddy.c
create mode 100644 drivers/gpu/drm/i915/i915_buddy.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d3ca46dc54ae..3962d9728dd7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -126,6 +126,7 @@ gem-y += \
i915-y += \
$(gem-y) \
i915_active.o \
+ i915_buddy.o \
i915_cmd_parser.o \
i915_gem_evict.o \
i915_gem_fence_reg.o \
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
new file mode 100644
index ..e3039e1273ef
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_buddy.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+
+#include "i915_buddy.h"
+
+#include "i915_gem.h"
+#include "i915_globals.h"
+#include "i915_utils.h"
+
+static struct i915_global_block {
+ struct i915_global base;
+ struct kmem_cache *slab_blocks;
+} global;
+
+static void i915_global_buddy_shrink(void)
+{
+ kmem_cache_shrink(global.slab_blocks);
+}
+
+static void i915_global_buddy_exit(void)
+{
+ kmem_cache_destroy(global.slab_blocks);
+}
+
+static struct i915_global_block global = { {
+ .shrink = i915_global_buddy_shrink,
+ .exit = i915_global_buddy_exit,
+} };
+
+int __init i915_global_buddy_init(void)
+{
+ global.slab_blocks = KMEM_CACHE(i915_buddy_block, SLAB_HWCACHE_ALIGN);
+ if (!global.slab_blocks)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static struct i915_buddy_block *i915_block_alloc(struct i915_buddy_block
*parent,
+unsigned int order,
+u64 offset)
+{
+ struct i915_buddy_block *block;
+
+ block = kmem_cache_zalloc(global.slab_blocks, GFP_KERNEL);
+ if (!block)
+ return NULL;
+
+ block->header = offset;
+ block->header |= order;
+ block->parent = parent;
+
+ return block;
+}
+
+static void i915_block_free(struct i915_buddy_block *block)
+{
+ kmem_cache_free(global.slab_blocks, block);
+}
+
+static void mark_allocated(struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_ALLOCATED;
+
+ list_del(>link);
+}
+
+static void mark_free(struct i915_buddy_mm *mm,
+ struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_FREE;
+
+ list_add(>link,
+>free_list[i915_buddy_block_order(block)]);
+}
+
+static void mark_split(struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_SPLIT;
+
+ list_del(>link);
+}
+
+int i915_buddy_init(struct i915_buddy_mm *mm, u64 size, u64 chunk_size)
+{
+ unsigned int i;
+ u64 offset;
+
+ if (size < chunk_size)
+ return -EINVAL;
+
+ if (chunk_size < PAGE_SIZE)
+ return -EINVAL;
+
+ if (!is_power_of_2(chunk_size))
+ return -EINVAL;
+
+ size = round_down(size, chunk_size);
+
+ mm->size = size;
+ mm->chunk_size = chunk_size;
+ mm->max_order = ilog2(size) - ilog2(chunk_size);
+
+ GEM_BUG_ON(mm->max_order > I915_BUDDY_MAX_ORDER);
+
+ mm->free_list = kmalloc_array(mm->max_order + 1,
+ sizeof(struct list_head),
+ GFP_KERNEL);
+ if (!mm->free_list)
+ return -ENOMEM;
+
+ for (i = 0; i <= mm->max_order; ++i)
+ INIT_LIST_HEAD(>free_list[i]);
+
+ mm->n_roots = hweight64(size);
+
+ mm->roots = kmalloc_array(mm->n_roots,
+ sizeof(struct i915_buddy_block *),
+ GFP_KERNEL);
Re: [PATCH] drm: Fix kerneldoc warns in connector-related docs
Hi Sean.
> > > > > --- a/include/drm/drm_connector.h
> > > > > +++ b/include/drm/drm_connector.h
> > > > > @@ -543,8 +543,8 @@ struct drm_connector_state {
> > > > >*
> > > > >* This is also used in the atomic helpers to map encoders to
> > > > > their
> > > > >* current and previous connectors, see
> > > > > - * _atomic_get_old_connector_for_encoder() and
> > > > > - * _atomic_get_new_connector_for_encoder().
> > > > > + * _atomic_get_old_connector_for_encoder and
> > > > > + * _atomic_get_new_connector_for_encoder.
> > > > Please fix this to use () for the functions and drop the "&".
> > > > This is what we use in drm kernel-doc for functions.
> > > > See for example function references in doc of writeback_job in the same
> > > > file.
> > >
> > > Doing this won't get a hyperlink in the docs. It seems like these hooks
> > > aren't
> > > recognized as functions by sphinx (not sure didn't look into it too
> > > deeply). The
> > > other "_funcs.*" hooks are also handled with '&' (there are lots of
> > > examples in
> > > drm_connector.h).
> > >
> > > I think preserving the hyperlinks probably outweighs the missing (),
> > > thoughts?
> >
> > Hmm, I actually tested it here - with sphinx_1.4.9.
> > The links was preserved, the only difference was that they had the ()
> > prefixed to their name.
> >
> > Do you happen to use an older sphinx version?
>
> I'm on 1.7.9. I just rechecked and was a bit confused in my last mail. The
> drm_atomic_get_*_connector_for_encoder links do work with (), it's the ones
> drm_connector_helper_funcs in the paragraph above that need the '&'. So I'll
> switch up these 2 and leave the others as-is. Cool?
Perfect!
You can add my:
Reviewed-by: Sam Ravnborg
and then apply.
Sam
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Re: [PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
On Fri, Aug 9, 2019 at 10:24 AM Guido Günther wrote:
>
> The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
>
> Signed-off-by: Guido Günther
> ---
> .../bindings/display/bridge/nwl-dsi.yaml | 155 ++
> 1 file changed, 155 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> new file mode 100644
> index ..5ed8bc4a4d18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> @@ -0,0 +1,155 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Northwest Logic MIPI-DSI on imx SoCs
> +
> +maintainers:
> + - Guido Gúnther
> + - Robert Chiras
> +
> +description: |
> + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi
> bridge for
> + the SOCs NWL MIPI-DSI host controller.
> +
> +properties:
> + compatible:
> +oneOf:
> + - items:
> +- const: fsl,imx8mq-nwl-dsi
Don't need oneOf nor items here for a single possible value:
compatible:
const: fsl,imx8mq-nwl-dsi
Or go ahead and add other compatibles because the 'if' below seems to
indicate you'll have more.
> +
> + reg:
> +maxItems: 1
> +
> + interrupts:
> +maxItems: 1
> +
> + clocks:
> +items:
> + - description: DSI core clock
> + - description: RX_ESC clock (used in escape mode)
> + - description: TX_ESC clock (used in escape mode)
> + - description: PHY_REF clock
> +
> + clock-names:
> +items:
> + - const: core
> + - const: rx_esc
> + - const: tx_esc
> + - const: phy_ref
> +
> + phys:
> +maxItems: 1
> +description:
> + A phandle to the phy module representing the DPHY
> +
> + phy-names:
> +items:
> + - const: dphy
> +
> + power-domains:
> +maxItems: 1
> +description:
> + A phandle to the power domain
> +
> + resets:
> +maxItems: 4
> +description:
> + A phandle to the reset controller
Sounds like 4 phandles... This should look similar to 'clocks'.
> +
> + reset-names:
> +items:
> + - const: byte
> + - const: dpi
> + - const: esc
> + - const: pclk
> +
> + mux-sel:
Needs a vendor prefix and will need a $ref to the type.
> +maxItems: 1
> +description:
> + A phandle to the MUX register set
> +
> + port:
> +type: object
> +description:
> + A input put or output port node.
> +
> + ports:
> +type: object
> +description:
> + A node containing DSI input & output port nodes with endpoint
> + definitions as documented in
> + Documentation/devicetree/bindings/graph.txt.
You need to define what port@0 and port@1 are.
> +
> +patternProperties:
> + "^panel@[0-9]+$": true
> +
> +allOf:
> + - if:
> + properties:
> +compatible:
> + contains:
> +enum:
> + - fsl,imx8mq-nwl-dsi
This conditional isn't needed until you have more than one compatible.
> + required:
> +- resets
> +- reset-names
> +- mux-sel
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
ports should be required.
> +
> +examples:
> + - |
> +
> + mipi_dsi: mipi_dsi@30a0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mq-nwl-dsi";
> + reg = <0x30A0 0x300>;
> + clocks = < 163>, < 244>, < 245>, < 164>;
> + clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
> + interrupts = <0 34 4>;
> + power-domains = <_mipi>;
> + resets = < 0>, < 1>, < 2>, < 3>;
> + reset-names = "byte", "dpi", "esc", "pclk";
> + mux-sel = <_gpr>;
> + phys = <>;
> + phy-names = "dphy";
> +
> + panel@0 {
> + compatible = "...";
Needs to be a valid compatible. Also need 'reg' here or drop the unit-address.
> + port@0 {
> + panel_in: endpoint {
> + remote-endpoint = <_dsi_out>;
> + };
> + };
> + };
> +
> + ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> + reg = <0>;
> + mipi_dsi_in: endpoint {
> +remote-endpoint = <_mipi_dsi>;
> + };
> +};
> +port@1 {
> + reg = <1>;
> +
[PATCH 09/16] fbdev: remove w90x900/nuc900 platform drivers
The ARM w90x900 platform is getting removed, so this driver is obsolete.
Signed-off-by: Arnd Bergmann
---
drivers/video/fbdev/Kconfig | 14 -
drivers/video/fbdev/Makefile | 1 -
drivers/video/fbdev/nuc900fb.c | 760 ---
drivers/video/fbdev/nuc900fb.h | 51 --
include/Kbuild | 1 -
include/linux/platform_data/video-nuc900fb.h | 79 --
6 files changed, 906 deletions(-)
delete mode 100644 drivers/video/fbdev/nuc900fb.c
delete mode 100644 drivers/video/fbdev/nuc900fb.h
delete mode 100644 include/linux/platform_data/video-nuc900fb.h
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index 6b2de93bd302..5f83cd715387 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -1924,20 +1924,6 @@ config FB_S3C2410_DEBUG
Turn on debugging messages. Note that you can set/unset at run time
through sysfs
-config FB_NUC900
- tristate "NUC900 LCD framebuffer support"
- depends on FB && ARCH_W90X900
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- ---help---
- Frame buffer driver for the built-in LCD controller in the Nuvoton
- NUC900 processor
-
-config GPM1040A0_320X240
- bool "Giantplus Technology GPM1040A0 320x240 Color TFT LCD"
- depends on FB_NUC900
-
config FB_SM501
tristate "Silicon Motion SM501 framebuffer support"
depends on FB && MFD_SM501
diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
index 7dc4861a93e6..aab7155884ea 100644
--- a/drivers/video/fbdev/Makefile
+++ b/drivers/video/fbdev/Makefile
@@ -116,7 +116,6 @@ obj-y += omap2/
obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
obj-$(CONFIG_FB_CARMINE) += carminefb.o
obj-$(CONFIG_FB_MB862XX) += mb862xx/
-obj-$(CONFIG_FB_NUC900) += nuc900fb.o
obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o
obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o
obj-$(CONFIG_FB_HYPERV) += hyperv_fb.o
diff --git a/drivers/video/fbdev/nuc900fb.c b/drivers/video/fbdev/nuc900fb.c
deleted file mode 100644
index 4fd851598584..
--- a/drivers/video/fbdev/nuc900fb.c
+++ /dev/null
@@ -1,760 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- *
- * Copyright (c) 2009 Nuvoton technology corporation
- * All rights reserved.
- *
- * Description:
- *Nuvoton LCD Controller Driver
- * Author:
- *Wang Qiang (rurality.li...@gmail.com) 2009/12/11
- */
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-#include
-#include
-#include
-
-#include "nuc900fb.h"
-
-
-/*
- * Initialize the nuc900 video (dual) buffer address
- */
-static void nuc900fb_set_lcdaddr(struct fb_info *info)
-{
- struct nuc900fb_info *fbi = info->par;
- void __iomem *regs = fbi->io;
- unsigned long vbaddr1, vbaddr2;
-
- vbaddr1 = info->fix.smem_start;
- vbaddr2 = info->fix.smem_start;
- vbaddr2 += info->fix.line_length * info->var.yres;
-
- /* set frambuffer start phy addr*/
- writel(vbaddr1, regs + REG_LCM_VA_BADDR0);
- writel(vbaddr2, regs + REG_LCM_VA_BADDR1);
-
- writel(fbi->regs.lcd_va_fbctrl, regs + REG_LCM_VA_FBCTRL);
- writel(fbi->regs.lcd_va_scale, regs + REG_LCM_VA_SCALE);
-}
-
-/*
- * calculate divider for lcd div
- */
-static unsigned int nuc900fb_calc_pixclk(struct nuc900fb_info *fbi,
-unsigned long pixclk)
-{
- unsigned long clk = fbi->clk_rate;
- unsigned long long div;
-
- /* pixclk is in picseconds. our clock is in Hz*/
- /* div = (clk * pixclk)/10^12 */
- div = (unsigned long long)clk * pixclk;
- div >>= 12;
- do_div(div, 625 * 625UL * 625);
-
- dev_dbg(fbi->dev, "pixclk %ld, divisor is %lld\n", pixclk, div);
-
- return div;
-}
-
-/*
- * Check the video params of 'var'.
- */
-static int nuc900fb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- struct nuc900fb_info *fbi = info->par;
- struct nuc900fb_mach_info *mach_info = dev_get_platdata(fbi->dev);
- struct nuc900fb_display *display = NULL;
- struct nuc900fb_display *default_display = mach_info->displays +
- mach_info->default_display;
- int i;
-
- dev_dbg(fbi->dev, "check_var(var=%p, info=%p)\n", var, info);
-
- /* validate x/y resolution */
- /* choose default mode if possible */
- if (var->xres == default_display->xres &&
- var->yres == default_display->yres &&
- var->bits_per_pixel == default_display->bpp)
-
Re: [PATCH] drm: Fix kerneldoc warns in connector-related docs
On Fri, Aug 09, 2019 at 10:15:51PM +0200, Sam Ravnborg wrote:
> Hi Sean.
>
> > > > --- a/include/drm/drm_connector.h
> > > > +++ b/include/drm/drm_connector.h
> > > > @@ -543,8 +543,8 @@ struct drm_connector_state {
> > > > *
> > > > * This is also used in the atomic helpers to map encoders to
> > > > their
> > > > * current and previous connectors, see
> > > > -* _atomic_get_old_connector_for_encoder() and
> > > > -* _atomic_get_new_connector_for_encoder().
> > > > +* _atomic_get_old_connector_for_encoder and
> > > > +* _atomic_get_new_connector_for_encoder.
> > > Please fix this to use () for the functions and drop the "&".
> > > This is what we use in drm kernel-doc for functions.
> > > See for example function references in doc of writeback_job in the same
> > > file.
> >
> > Doing this won't get a hyperlink in the docs. It seems like these hooks
> > aren't
> > recognized as functions by sphinx (not sure didn't look into it too
> > deeply). The
> > other "_funcs.*" hooks are also handled with '&' (there are lots of
> > examples in
> > drm_connector.h).
> >
> > I think preserving the hyperlinks probably outweighs the missing (),
> > thoughts?
>
> Hmm, I actually tested it here - with sphinx_1.4.9.
> The links was preserved, the only difference was that they had the ()
> prefixed to their name.
>
> Do you happen to use an older sphinx version?
I'm on 1.7.9. I just rechecked and was a bit confused in my last mail. The
drm_atomic_get_*_connector_for_encoder links do work with (), it's the ones
drm_connector_helper_funcs in the paragraph above that need the '&'. So I'll
switch up these 2 and leave the others as-is. Cool?
Sean
>
> Sam
--
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Re: [PATCH] drm/i915: Remove redundant user_access_end() from __copy_from_user() error path
On Fri, Aug 9, 2019 at 1:03 AM Nick Desaulniers wrote: > > On Thu, Aug 8, 2019 at 1:22 PM Thomas Gleixner wrote: > > > tglx just picked up 2 other patches of mine, bumping just in case he's > > > not picking up patches while on vacation. ;) > > > > I'm only half on vacation :) > > > > So I can pick it up. > > Thanks, will send half margaritas. > Sends some Turkish Cay. - Sedat -
Re: [PATCH] drm: Fix kerneldoc warns in connector-related docs
Hi Sean.
> > > --- a/include/drm/drm_connector.h
> > > +++ b/include/drm/drm_connector.h
> > > @@ -543,8 +543,8 @@ struct drm_connector_state {
> > >*
> > >* This is also used in the atomic helpers to map encoders to their
> > >* current and previous connectors, see
> > > - * _atomic_get_old_connector_for_encoder() and
> > > - * _atomic_get_new_connector_for_encoder().
> > > + * _atomic_get_old_connector_for_encoder and
> > > + * _atomic_get_new_connector_for_encoder.
> > Please fix this to use () for the functions and drop the "&".
> > This is what we use in drm kernel-doc for functions.
> > See for example function references in doc of writeback_job in the same
> > file.
>
> Doing this won't get a hyperlink in the docs. It seems like these hooks aren't
> recognized as functions by sphinx (not sure didn't look into it too deeply).
> The
> other "_funcs.*" hooks are also handled with '&' (there are lots of examples
> in
> drm_connector.h).
>
> I think preserving the hyperlinks probably outweighs the missing (), thoughts?
Hmm, I actually tested it here - with sphinx_1.4.9.
The links was preserved, the only difference was that they had the ()
prefixed to their name.
Do you happen to use an older sphinx version?
Sam
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Re: [PATCH 02/22] ARM: omap1: make omapfb standalone compilable
On Fri, Aug 9, 2019 at 4:36 PM Bartlomiej Zolnierkiewicz
wrote:
> On 8/9/19 1:43 PM, Arnd Bergmann wrote:
> >
> > That would have been ok as well, but having the addition here was
> > intentional and seems more logical to me as this is where the headers
> > get moved around.
> I see that this is an optimization for making the patch series more
> compact but I think that this addition logically belongs to patch #9
> (which adds support for COMPILE_TEST) where the new code is required.
>
> Moreover patch description for patch #2 lacks any comment about this
> addition being a preparation for changes in patch #9 so I was quite
> puzzled about its purpose when seeing it first.
>
> Therefore please have mercy on the poor/stupid reviewer and don't do
> such optimizations intentionally (or at least describe them properly
> somewhere).. ;-)
Ok, I looked at it some more and agree that you are right. I've split it
up further now into patches that make more sense by themselves:
commit ad71cdc54404ecde2e88678ee6bc7ae7fb8aec97
Author: Arnd Bergmann
Date: Tue Aug 6 16:08:34 2019 +0200
fbdev: omap: avoid using mach/*.h files
All the headers we actually need are now in include/linux/soc,
so use those versions instead and allow compile-testing on
other architectures.
Acked-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Arnd Bergmann
drivers/video/backlight/Kconfig | 4 ++--
drivers/video/backlight/omap1_bl.c | 4 ++--
drivers/video/fbdev/omap/Kconfig | 4 ++--
drivers/video/fbdev/omap/lcd_ams_delta.c | 2 +-
drivers/video/fbdev/omap/lcd_dma.c | 3 ++-
drivers/video/fbdev/omap/lcd_inn1510.c | 2 +-
drivers/video/fbdev/omap/lcd_osk.c | 4 ++--
drivers/video/fbdev/omap/lcdc.c | 2 ++
drivers/video/fbdev/omap/omapfb_main.c | 3 +--
drivers/video/fbdev/omap/sossi.c | 1 +
10 files changed, 16 insertions(+), 13 deletions(-)
commit 959e0d68751757e84dd703f60405c7268763dba4
Author: Arnd Bergmann
Date: Fri Aug 9 21:27:01 2019 +0200
fbdev: omap: pass irqs as resource
To avoid relying on the mach/irqs.h header, stop using
OMAP_LCDC_IRQ and INT_1610_SoSSI_MATCH directly in the driver
code, but instead pass these as resources.
Signed-off-by: Arnd Bergmann
arch/arm/mach-omap1/fb.c | 19 ++-
drivers/video/fbdev/omap/lcdc.c| 6 +++---
drivers/video/fbdev/omap/omapfb.h | 2 ++
drivers/video/fbdev/omap/omapfb_main.c | 16 +++-
drivers/video/fbdev/omap/sossi.c | 2 +-
5 files changed, 39 insertions(+), 6 deletions(-)
commit 6643f7a7da3ca7ce8f2ff094fecab7a0fd706acf
Author: Arnd Bergmann
Date: Fri Aug 9 21:42:31 2019 +0200
ARM: omap1: declare a dummy omap_set_dma_priority
omapfb calls directly into the omap_set_dma_priority() function in
the DMA driver. This prevents compile-testing omapfb on other
architectures. Add an inline function next to the other ones
for non-omap configurations.
Signed-off-by: Arnd Bergmann
include/linux/omap-dma.h | 3 +++
1 file changed, 3 insertions(+)
commit 154bfb7ddcecdbca66d9a086776a3108831ef0b9
Author: Arnd Bergmann
Date: Mon Aug 5 23:15:37 2019 +0200
ARM: omap1: move lcd_dma code into omapfb driver
The omapfb driver is split into platform specific code for omap1, and
driver code that is also specific to omap1.
Moving both parts into the driver directory simplifies the structure
and avoids the dependency on certain omap machine header files.
As mach/lcd_dma.h can not be included from include/linux/omap-dma.h
any more now, move the omap_lcd_dma_running() declaration into the
omap-dma header, which matches where it is defined.
Signed-off-by: Arnd Bergmann
arch/arm/mach-omap1/Makefile
| 4
arch/arm/mach-omap1/include/mach/lcdc.h
| 44
drivers/video/fbdev/Makefile
| 2 +-
drivers/video/fbdev/omap/Makefile
| 5 +
{arch/arm/mach-omap1 => drivers/video/fbdev/omap}/lcd_dma.c
| 4 +++-
{arch/arm/mach-omap1/include/mach =>
drivers/video/fbdev/omap}/lcd_dma.h | 2 --
drivers/video/fbdev/omap/lcdc.c
| 2 +-
drivers/video/fbdev/omap/lcdc.h
| 35 +++
drivers/video/fbdev/omap/sossi.c | 1 +
include/linux/omap-dma.h
| 4 ++--
10 files changed, 48 insertions(+), 55 deletions(-)
commit b8ddb98d29a43fecb4387d0d8218935cb1997a28
Author: Arnd Bergmann
Date: Tue Aug 6 14:59:00 2019 +0200
ARM: omap1: innovator: pass lcd control address as pdata
To avoid using the mach/omap1510.h header file, pass the correct
address as platform data.
Acked-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Arnd Bergmann
arch/arm/mach-omap1/board-innovator.c | 3 +++
drivers/video/fbdev/omap/lcd_inn1510.c | 7 +--
2 files changed, 8 insertions(+), 2 deletions(-)
The resulting code is the same as before,
Re: [PATCH] drm: Fix kerneldoc warns in connector-related docs
On Wed, Aug 07, 2019 at 07:30:23PM +0200, Sam Ravnborg wrote:
> Hi Sean.
>
> On Wed, Aug 07, 2019 at 12:28:04PM -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > Fixes the following warnings:
> > ../drivers/gpu/drm/drm_connector.c:989: WARNING: Unexpected indentation.
> > ../drivers/gpu/drm/drm_connector.c:993: WARNING: Unexpected indentation.
> > ../include/drm/drm_connector.h:544: WARNING: Inline interpreted text or
> > phrase reference start-string without end-string.
> > ../include/drm/drm_connector.h:544: WARNING: Inline interpreted text or
> > phrase reference start-string without end-string.
>
> Thanks, 4 less warnings..
> >
> > Fixes: 1b27fbdde1df ("drm: Add
> > drm_atomic_get_(old|new)_connector_for_encoder() helpers")
> > Fixes: bb5a45d40d50 ("drm/hdcp: update content protection property with
> > uevent")
> > Cc: Ramalingam C
> > Cc: Daniel Vetter
> > Cc: Pekka Paalanen
> > Cc: Sam Ravnborg
> > Cc: Laurent Pinchart
> > Cc: Jani Nikula
> > Cc: Sean Paul
> > Cc: Maarten Lankhorst
> > Cc: Maxime Ripard
> > Cc: Sean Paul
> > Cc: David Airlie
> > Cc: dri-devel@lists.freedesktop.org
> > Signed-off-by: Sean Paul
> > ---
> > drivers/gpu/drm/drm_connector.c | 10 ++
> > include/drm/drm_connector.h | 4 ++--
> > 2 files changed, 8 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_connector.c
> > b/drivers/gpu/drm/drm_connector.c
> > index 354798bad576..4c766624b20d 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -986,12 +986,14 @@ static const struct drm_prop_enum_list
> > hdmi_colorspaces[] = {
> > * - Kernel sends uevent with the connector id and property id through
> > * @drm_hdcp_update_content_protection, upon below kernel triggered
> > * scenarios:
> > - * DESIRED -> ENABLED (authentication success)
> > - * ENABLED -> DESIRED (termination of authentication)
> > + *
> > + * - DESIRED -> ENABLED (authentication success)
> > + * - ENABLED -> DESIRED (termination of authentication)
> > * - Please note no uevents for userspace triggered property state changes,
> > * which can't fail such as
> > - * DESIRED/ENABLED -> UNDESIRED
> > - * UNDESIRED -> DESIRED
> > + *
> > + * - DESIRED/ENABLED -> UNDESIRED
> > + * - UNDESIRED -> DESIRED
> > * - Userspace is responsible for polling the property or listen to uevents
> > * to determine when the value transitions from ENABLED to DESIRED.
> > * This signifies the link is no longer protected and userspace should
> > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> > index 0b9997e27689..e391f9c05f98 100644
> > --- a/include/drm/drm_connector.h
> > +++ b/include/drm/drm_connector.h
> > @@ -543,8 +543,8 @@ struct drm_connector_state {
> > *
> > * This is also used in the atomic helpers to map encoders to their
> > * current and previous connectors, see
> > -* _atomic_get_old_connector_for_encoder() and
> > -* _atomic_get_new_connector_for_encoder().
> > +* _atomic_get_old_connector_for_encoder and
> > +* _atomic_get_new_connector_for_encoder.
> Please fix this to use () for the functions and drop the "&".
> This is what we use in drm kernel-doc for functions.
> See for example function references in doc of writeback_job in the same file.
Doing this won't get a hyperlink in the docs. It seems like these hooks aren't
recognized as functions by sphinx (not sure didn't look into it too deeply). The
other "_funcs.*" hooks are also handled with '&' (there are lots of examples in
drm_connector.h).
I think preserving the hyperlinks probably outweighs the missing (), thoughts?
Sean
>
> With this fixed:
> Reviewed-by: Sam Ravnborg
>
> > *
> > * NOTE: Atomic drivers must fill this out (either themselves or through
> > * helpers), for otherwise the GETCONNECTOR and GETENCODER IOCTLs will
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
--
Sean Paul, Software Engineer, Google / Chromium OS
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[pull] amdgpu, amdkfd, radeon, ttm drm-next-5.4
Hi Dave, Daniel, Same request as earlier, but with the readq/writeq stuff resolved and 5.3-rc3 backmerged. diffstat trimmed for size. The following changes since commit 41a5a2a8531f95d18bb4efddea581ccb469e8ee5: drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq (2019-07-18 14:12:08 -0500) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/drm-next-5.4-2019-08-09 for you to fetch changes up to 3f61fd41f38328f0a585eaba2d72d339fe9aecda: Merge tag 'v5.3-rc3' into drm-next-5.4 (2019-08-09 13:07:28 -0500) drm-next-5.4-2019-08-09: Same as drm-next-5.4-2019-08-06, but with the readq/writeq stuff fixed and 5.3-rc3 backmerged. amdgpu: - Add navi14 support - Add navi12 support - Add Arcturus support - Enable mclk DPM for Navi - Misc DC display fixes - Add perfmon support for DF - Add scatter/gather display support for Raven - Improve SMU handling for GPU reset - RAS support for GFX - Drop last of drmP.h - Add support for wiping memory on buffer release - Allow cursor async updates for fb swaps - Misc fixes and cleanups amdkfd: - Add navi14 support - Add navi12 support - Add Arcturus support - CWSR trap handlers updates for gfx9, 10 - Drop last of drmP.h - Update MAINTAINERS radeon: - Misc fixes and cleanups - Make kexec more reliable by tearing down the GPU ttm: - Add release_notify callback uapi: - Add wipe memory on release flag for buffer creation ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] i2c: replace i2c_new_secondary_device with an ERR_PTR variant
Hi Wolfram,
On Fri, Aug 09, 2019 at 05:40:47PM +0200, Wolfram Sang wrote:
> In the general move to have i2c_new_*_device functions which return
> ERR_PTR instead of NULL, this patch converts i2c_new_secondary_device().
>
> There are only few users, so this patch converts the I2C core and all
> users in one go. The function gets renamed to i2c_new_ancillary_device()
> so out-of-tree users will get a build failure to understand they need to
> adapt their error checking code.
>
> Signed-off-by: Wolfram Sang
> Reviewed-by: Kieran Bingham #
> adv748x
> Reviewed-by: Laurent Pinchart # adv7511
> ---
>
> Changes since v1:
>
> * adv7604: use a local variable for error handling
> * adv7604: simplify unregistering dummy clients because I2C core helper
>is NULL ptr aware
For adv7604:
Reviewed-by: Laurent Pinchart
> * added tags for adv748x and adv7511
>
> Thanks Kieran and Laurent!
>
> drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 18
> drivers/i2c/i2c-core-base.c | 10 -
> drivers/media/i2c/adv748x/adv748x-core.c | 6 +++---
> drivers/media/i2c/adv7604.c | 22 +++-
> include/linux/i2c.h | 2 +-
> 5 files changed, 30 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> index f6d2681f6927..9e13e466e72c 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> @@ -981,10 +981,10 @@ static int adv7511_init_cec_regmap(struct adv7511 *adv)
> {
> int ret;
>
> - adv->i2c_cec = i2c_new_secondary_device(adv->i2c_main, "cec",
> + adv->i2c_cec = i2c_new_ancillary_device(adv->i2c_main, "cec",
> ADV7511_CEC_I2C_ADDR_DEFAULT);
> - if (!adv->i2c_cec)
> - return -EINVAL;
> + if (IS_ERR(adv->i2c_cec))
> + return PTR_ERR(adv->i2c_cec);
> i2c_set_clientdata(adv->i2c_cec, adv);
>
> adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
> @@ -1165,20 +1165,20 @@ static int adv7511_probe(struct i2c_client *i2c,
> const struct i2c_device_id *id)
>
> adv7511_packet_disable(adv7511, 0x);
>
> - adv7511->i2c_edid = i2c_new_secondary_device(i2c, "edid",
> + adv7511->i2c_edid = i2c_new_ancillary_device(i2c, "edid",
> ADV7511_EDID_I2C_ADDR_DEFAULT);
> - if (!adv7511->i2c_edid) {
> - ret = -EINVAL;
> + if (IS_ERR(adv7511->i2c_edid)) {
> + ret = PTR_ERR(adv7511->i2c_edid);
> goto uninit_regulators;
> }
>
> regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR,
>adv7511->i2c_edid->addr << 1);
>
> - adv7511->i2c_packet = i2c_new_secondary_device(i2c, "packet",
> + adv7511->i2c_packet = i2c_new_ancillary_device(i2c, "packet",
> ADV7511_PACKET_I2C_ADDR_DEFAULT);
> - if (!adv7511->i2c_packet) {
> - ret = -EINVAL;
> + if (IS_ERR(adv7511->i2c_packet)) {
> + ret = PTR_ERR(adv7511->i2c_packet);
> goto err_i2c_unregister_edid;
> }
>
> diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
> index f26ed495d384..76cb91e064b8 100644
> --- a/drivers/i2c/i2c-core-base.c
> +++ b/drivers/i2c/i2c-core-base.c
> @@ -966,7 +966,7 @@ struct i2c_client *devm_i2c_new_dummy_device(struct
> device *dev,
> EXPORT_SYMBOL_GPL(devm_i2c_new_dummy_device);
>
> /**
> - * i2c_new_secondary_device - Helper to get the instantiated secondary
> address
> + * i2c_new_ancillary_device - Helper to get the instantiated secondary
> address
> * and create the associated device
> * @client: Handle to the primary client
> * @name: Handle to specify which secondary address to get
> @@ -985,9 +985,9 @@ EXPORT_SYMBOL_GPL(devm_i2c_new_dummy_device);
> * cell whose "reg-names" value matches the slave name.
> *
> * This returns the new i2c client, which should be saved for later use with
> - * i2c_unregister_device(); or NULL to indicate an error.
> + * i2c_unregister_device(); or an ERR_PTR to describe the error.
> */
> -struct i2c_client *i2c_new_secondary_device(struct i2c_client *client,
> +struct i2c_client *i2c_new_ancillary_device(struct i2c_client *client,
> const char *name,
> u16 default_addr)
> {
> @@ -1002,9 +1002,9 @@ struct i2c_client *i2c_new_secondary_device(struct
> i2c_client *client,
> }
>
> dev_dbg(>adapter->dev, "Address for %s : 0x%x\n", name, addr);
> - return i2c_new_dummy(client->adapter, addr);
> + return i2c_new_dummy_device(client->adapter, addr);
> }
> -EXPORT_SYMBOL_GPL(i2c_new_secondary_device);
> +EXPORT_SYMBOL_GPL(i2c_new_ancillary_device);
>
> /*
RE: [PATCH 00/34] put_user_pages(): miscellaneous call sites
> > On Wed 07-08-19 19:36:37, Ira Weiny wrote: > > On Wed, Aug 07, 2019 at 10:46:49AM +0200, Michal Hocko wrote: > > > > So I think your debug option and my suggested renaming serve a bit > > > > different purposes (and thus both make sense). If you do the > > > > renaming, you can just grep to see unconverted sites. Also when > > > > someone merges new GUP user (unaware of the new rules) while you > > > > switch GUP to use pins instead of ordinary references, you'll get > > > > compilation error in case of renaming instead of hard to debug > > > > refcount leak without the renaming. And such conflict is almost > > > > bound to happen given the size of GUP patch set... Also the > > > > renaming serves against the "coding inertia" - i.e., GUP is around for > ages so people just use it without checking any documentation or comments. > > > > After switching how GUP works, what used to be correct isn't > > > > anymore so renaming the function serves as a warning that > > > > something has really changed. > > > > > > Fully agreed! > > > > Ok Prior to this I've been basing all my work for the RDMA/FS DAX > > stuff in Johns put_user_pages()... (Including when I proposed failing > > truncate with a lease in June [1]) > > > > However, based on the suggestions in that thread it became clear that > > a new interface was going to need to be added to pass in the "RDMA > > file" information to GUP to associate file pins with the correct > > processes... > > > > I have many drawings on my white board with "a whole lot of lines" on > > them to make sure that if a process opens a file, mmaps it, pins it > > with RDMA, _closes_ it, and ummaps it; that the resulting file pin can > > still be traced back to the RDMA context and all the processes which > > may have access to it No matter where the original context may > > have come from. I believe I have accomplished that. > > > > Before I go on, I would like to say that the "imbalance" of > > get_user_pages() and put_page() bothers me from a purist standpoint... > > However, since this discussion cropped up I went ahead and ported my > > work to Linus' current master > > (5.3-rc3+) and in doing so I only had to steal a bit of Johns code... > > Sorry John... :-( > > > > I don't have the commit messages all cleaned up and I know there may > > be some discussion on these new interfaces but I wanted to throw this > > series out there because I think it may be what Jan and Michal are > > driving at (or at least in that direction. > > > > Right now only RDMA and DAX FS's are supported. Other users of GUP > > will still fail on a DAX file and regular files will still be at > > risk.[2] > > > > I've pushed this work (based 5.3-rc3+ (33920f1ec5bf)) here[3]: > > > > https://github.com/weiny2/linux-kernel/tree/linus-rdmafsdax-b0-v3 > > > > I think the most relevant patch to this conversation is: > > > > https://github.com/weiny2/linux- > kernel/commit/5d377653ba5cf11c3b716f90 > > 4b057bee6641aaf6 > > > > I stole Jans suggestion for a name as the name I used while > > prototyping was pretty bad... So Thanks Jan... ;-) > > For your function, I'd choose a name like vaddr_pin_leased_pages() so that > association with a lease is clear from the name :) My gut was to just change this as you suggested. But the fact is that these calls can get used on anonymous pages as well. So the "leased" semantic may not apply... OTOH if a file is encountered it will fail the pin... :-/ I'm going to leave it for now and get the patches submitted to the list... > Also I'd choose the > counterpart to be vaddr_unpin_leased_page[s](). Especially having put_page > in the name looks confusing to me... Ah yes, totally agree with the "pin/unpin" symmetry. I've changed from "put" to "unpin"... Thanks, Ira > > Honza > > -- > Jan Kara > SUSE Labs, CR ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 24/60] drm/panel: Add driver for the Toppology TD043MTEA1 panel
Hi Sam,
On Fri, Aug 09, 2019 at 03:33:08PM +0200, Sam Ravnborg wrote:
> Hi Laurent.
>
> > > > +static int td043mtea1_disable(struct drm_panel *panel)
> > > > +{
> > > > + struct td043mtea1_device *lcd = to_td043mtea1_device(panel);
> > > > +
> > > > + if (!lcd->spi_suspended)
> > > > + td043mtea1_power_off(lcd);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int td043mtea1_enable(struct drm_panel *panel)
> > > > +{
> > > > + struct td043mtea1_device *lcd = to_td043mtea1_device(panel);
> > > > + int ret;
> > > > +
> > > > + /*
> > > > +* If we are resuming from system suspend, SPI might not be
> > > > enabled
> > > > +* yet, so we'll program the LCD from SPI PM resume callback.
> > > > +*/
> > > > + if (lcd->spi_suspended)
> > > > + return 0;
> > >
> > > I do not recall this is needed in other panel drivers, so look at what
> > > other spi based panels do here.
> > > I think this is something that today is not required.
> >
> > The problem here is that the display controller may be resumed before
> > the SPI bus. Has that been solved somewhere in core code ?
>
> I dunno. So the conclusion is to keep it as is, and any change
> will wait until someone with HW can step up.
Great, thanks.
> As for all your other feedback to this and the other panel drivers
> they did not trigger any repsonse from me.
>
> Looks forward for next iteration of this nice set of patches.
> Can we maybe get the panel drivers in before some of the infrastructure
> work?
> I know the users then may come a bit later, but I think thats OK.
Sure. I'll post the next version soon.
--
Regards,
Laurent Pinchart
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[Bug 110457] System resumes failed and hits [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx timeout on Acer Aspire A315-21G
https://bugs.freedesktop.org/show_bug.cgi?id=110457 --- Comment #10 from Eugene Bright --- The patch is on it's way https://bugs.freedesktop.org/show_bug.cgi?id=110258#c12 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 110258] Lenovo V110-15AST AMD A9-9410 AMD R5 Stoney hangs after waking after suspend. 5.0 onwards
https://bugs.freedesktop.org/show_bug.cgi?id=110258 --- Comment #13 from Eugene Bright --- The patch works! I've been able to apply it to the gentoo-sources-5.2.7. Thank you very much for reply! -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] mxsfb: allow attachment of display bridges
Hi,
On Thu, Aug 01, 2019 at 11:18:53AM +, Ville Baillie wrote:
> ---
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 20
> drivers/gpu/drm/mxsfb/mxsfb_drv.h | 1 +
> drivers/gpu/drm/mxsfb/mxsfb_out.c | 14 +++---
> 3 files changed, 28 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> index 6fafc90da4ec..c19a7b7aa3a6 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> @@ -229,10 +229,22 @@ static int mxsfb_load(struct drm_device *drm, unsigned
> long flags)
> goto err_vblank;
> }
>
> - ret = drm_panel_attach(mxsfb->panel, >connector);
> - if (ret) {
> - dev_err(drm->dev, "Cannot connect panel\n");
> - goto err_vblank;
> + if (mxsfb->panel) {
> + ret = drm_panel_attach(mxsfb->panel, >connector);
> + if (ret) {
> + dev_err(drm->dev, "Cannot connect panel\n");
> + goto err_vblank;
> + }
> + } else if (mxsfb->bridge) {
> + ret = drm_bridge_attach(>pipe.encoder, mxsfb->bridge,
> + NULL);
> + if (ret) {
> + dev_err(drm->dev, "Cannot connect bridge\n");
> + goto err_vblank;
> + }
> + } else {
> + dev_err(drm->dev, "No panel or bridge\n");
> + return -EINVAL;
> }
>
> drm->mode_config.min_width = MXSFB_MIN_XRES;
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> index d975300dca05..436fe4bbb47a 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> @@ -29,6 +29,7 @@ struct mxsfb_drm_private {
> struct drm_simple_display_pipe pipe;
> struct drm_connectorconnector;
> struct drm_panel*panel;
> + struct drm_bridge *bridge;
> };
>
> int mxsfb_setup_crtc(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_out.c
> b/drivers/gpu/drm/mxsfb/mxsfb_out.c
> index 91e76f9cead6..77e03eb0fca6 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_out.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_out.c
> @@ -78,9 +78,11 @@ int mxsfb_create_output(struct drm_device *drm)
> {
> struct mxsfb_drm_private *mxsfb = drm->dev_private;
> struct drm_panel *panel;
> + struct drm_bridge *bridge;
> int ret;
>
> - ret = drm_of_find_panel_or_bridge(drm->dev->of_node, 0, 0, ,
> NULL);
> + ret = drm_of_find_panel_or_bridge(drm->dev->of_node, 0, 0, ,
> + );
> if (ret)
> return ret;
>
> @@ -91,8 +93,14 @@ int mxsfb_create_output(struct drm_device *drm)
> ret = drm_connector_init(drm, >connector,
>_panel_connector_funcs,
>DRM_MODE_CONNECTOR_Unknown);
> - if (!ret)
> - mxsfb->panel = panel;
> + if (!ret) {
> + if (panel)
> + mxsfb->panel = panel;
> + else if (bridge)
> + mxsfb->bridge = bridge;
> + else
> + return -EINVAL;
> + }
>
> return ret;
> }
> --
> 2.17.1
Robert Chiras posted bridge support for mxsfb back in June:
https://patchwork.freedesktop.org/patch/314430/?series=62822=1
Cheers,
-- Guido
>
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Re: [GIT PULL] fbdev fix for v5.3-rc4
The pull request you sent on Fri, 9 Aug 2019 16:07:35 +0200: > https://github.com/bzolnier/linux.git tags/fbdev-v5.3-rc4 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/ec4c99ad7bd23dd39ffb1381136cefa4bb632e31 Thank you! -- Deet-doot-dot, I am a bot. https://korg.wiki.kernel.org/userdoc/prtracker ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/3] drm/bridge: Add NWL MIPI DSI host controller support
Hi Laurent, thanks for the review! Most of it seemed clear how to fix for the rest i've put some questions below: On Sat, Jul 27, 2019 at 05:47:00AM +0300, Laurent Pinchart wrote: > Hello Guido, > > Thank you for the patch. > > On Wed, Jul 24, 2019 at 05:52:26PM +0200, Guido Günther wrote: > > This adds initial support for the NWL MIPI DSI Host controller found on > > i.MX8 SoCs. > > > > It adds support for the i.MX8MQ but the same IP can be found on > > e.g. the i.MX8QXP. > > > > It has been tested on the Librem 5 devkit using mxsfb. > > > > Signed-off-by: Guido Günther > > Co-developed-by: Robert Chiras > > --- > > drivers/gpu/drm/bridge/Kconfig | 2 + > > drivers/gpu/drm/bridge/Makefile | 1 + > > drivers/gpu/drm/bridge/imx-nwl/Kconfig | 15 + > > drivers/gpu/drm/bridge/imx-nwl/Makefile | 2 + > > drivers/gpu/drm/bridge/imx-nwl/nwl-drv.c | 529 > > drivers/gpu/drm/bridge/imx-nwl/nwl-drv.h | 72 +++ > > drivers/gpu/drm/bridge/imx-nwl/nwl-dsi.c | 745 +++ > > drivers/gpu/drm/bridge/imx-nwl/nwl-dsi.h | 111 > > 8 files changed, 1477 insertions(+) > > create mode 100644 drivers/gpu/drm/bridge/imx-nwl/Kconfig > > create mode 100644 drivers/gpu/drm/bridge/imx-nwl/Makefile > > create mode 100644 drivers/gpu/drm/bridge/imx-nwl/nwl-drv.c > > create mode 100644 drivers/gpu/drm/bridge/imx-nwl/nwl-drv.h > > create mode 100644 drivers/gpu/drm/bridge/imx-nwl/nwl-dsi.c > > create mode 100644 drivers/gpu/drm/bridge/imx-nwl/nwl-dsi.h > > > > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > > index a6eec908c43e..38c3145a7e57 100644 > > --- a/drivers/gpu/drm/bridge/Kconfig > > +++ b/drivers/gpu/drm/bridge/Kconfig > > @@ -152,6 +152,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig" > > > > source "drivers/gpu/drm/bridge/adv7511/Kconfig" > > > > +source "drivers/gpu/drm/bridge/imx-nwl/Kconfig" > > + > > As this doesn't seem to be an i.MX-specific IP, I wouldn't use the name > imx in file names or in the code, at least in the parts that are not > NXP-specific. O.k. Since i've not seen other SoCs using this ip core I wasn't sure what would be sharable but we'll figure that out. Renamed to nwl-dsi/ > > source "drivers/gpu/drm/bridge/synopsys/Kconfig" > > > > endmenu > > diff --git a/drivers/gpu/drm/bridge/Makefile > > b/drivers/gpu/drm/bridge/Makefile > > index 4934fcf5a6f8..904a9eb3a20a 100644 > > --- a/drivers/gpu/drm/bridge/Makefile > > +++ b/drivers/gpu/drm/bridge/Makefile > > @@ -16,4 +16,5 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ > > obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ > > obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o > > obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o > > +obj-y += imx-nwl/ > > obj-y += synopsys/ > > diff --git a/drivers/gpu/drm/bridge/imx-nwl/Kconfig > > b/drivers/gpu/drm/bridge/imx-nwl/Kconfig > > new file mode 100644 > > index ..822dba1b380a > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/imx-nwl/Kconfig > > @@ -0,0 +1,15 @@ > > +config DRM_IMX_NWL_DSI > > + tristate "Support for Northwest Logic MIPI DSI Host controller" > > + depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM || COMPILE_TEST) > > + depends on COMMON_CLK > > + depends on OF && HAS_IOMEM > > + select DRM_KMS_HELPER > > + select DRM_MIPI_DSI > > + select DRM_PANEL_BRIDGE > > + select GENERIC_PHY_MIPI_DPHY > > + select MFD_SYSCON > > + select REGMAP_MMIO > > + help > > + This enables the Northwest Logic MIPI DSI Host controller as > > + found on NXP's i.MX8 Processors. > > + > > diff --git a/drivers/gpu/drm/bridge/imx-nwl/Makefile > > b/drivers/gpu/drm/bridge/imx-nwl/Makefile > > new file mode 100644 > > index ..9fa63483da5b > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/imx-nwl/Makefile > > @@ -0,0 +1,2 @@ > > +imx-nwl-objs := nwl-drv.o nwl-dsi.o > > +obj-$(CONFIG_DRM_IMX_NWL_DSI) += imx-nwl.o > > diff --git a/drivers/gpu/drm/bridge/imx-nwl/nwl-drv.c > > b/drivers/gpu/drm/bridge/imx-nwl/nwl-drv.c > > new file mode 100644 > > index ..451f8f067c6f > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/imx-nwl/nwl-drv.c > > @@ -0,0 +1,529 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * i.MX8 NWL MIPI DSI host driver > > + * > > + * Copyright (C) 2017 NXP > > + * Copyright (C) 2019 Purism SPC > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > This doesn't seem to be needed. Dropped. > > > +#include > > +#include > > Same here. Dropped (it was a component driver before). > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "nwl-drv.h" > > +#include "nwl-dsi.h" > > + > > +#define DRV_NAME "imx-nwl-dsi" > > + > > +/* 8MQ SRC specific registers */ > > +#define SRC_MIPIPHY_RCR0x28 > > +#define RESET_BYTE_N
[PATCH v2 3/3] drm/bridge: Add NWL MIPI DSI host controller support
This adds initial support for the NWL MIPI DSI Host controller found on
i.MX8 SoCs.
It adds support for the i.MX8MQ but the same IP can be found on
e.g. the i.MX8QXP.
It has been tested on the Librem 5 devkit using mxsfb.
Signed-off-by: Guido Günther
Co-developed-by: Robert Chiras
---
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/nwl-dsi/Kconfig | 15 +
drivers/gpu/drm/bridge/nwl-dsi/Makefile | 4 +
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c | 484
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h | 66 +++
drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c | 700 +++
drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h | 112
8 files changed, 1384 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Kconfig
create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Makefile
create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c
create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h
create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c
create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 1cc9f502c1f2..7980b5c2156f 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -154,6 +154,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig"
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
+source "drivers/gpu/drm/bridge/nwl-dsi/Kconfig"
+
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 4934fcf5a6f8..d9f6c0f77592 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -16,4 +16,5 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/nwl-dsi/Kconfig
b/drivers/gpu/drm/bridge/nwl-dsi/Kconfig
new file mode 100644
index ..27ec86c05401
--- /dev/null
+++ b/drivers/gpu/drm/bridge/nwl-dsi/Kconfig
@@ -0,0 +1,15 @@
+config DRM_NWL_MIPI_DSI
+ tristate "Support for Northwest Logic MIPI DSI Host controller"
+ depends on DRM
+ depends on COMMON_CLK
+ depends on OF && HAS_IOMEM
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ select MFD_SYSCON
+ select REGMAP_MMIO
+ help
+ This enables the Northwest Logic MIPI DSI Host controller as
+ for example found on NXP's i.MX8 Processors.
+
diff --git a/drivers/gpu/drm/bridge/nwl-dsi/Makefile
b/drivers/gpu/drm/bridge/nwl-dsi/Makefile
new file mode 100644
index ..804baf2f1916
--- /dev/null
+++ b/drivers/gpu/drm/bridge/nwl-dsi/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+nwl-mipi-dsi-y := nwl-drv.o nwl-dsi.o
+obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-mipi-dsi.o
+header-test-y += nwl-drv.h nwl-dsi.h
diff --git a/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c
b/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c
new file mode 100644
index ..0bd3a4184885
--- /dev/null
+++ b/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c
@@ -0,0 +1,484 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX8 NWL MIPI DSI host driver
+ *
+ * Copyright (C) 2017 NXP
+ * Copyright (C) 2019 Purism SPC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "nwl-drv.h"
+#include "nwl-dsi.h"
+
+#define DRV_NAME "nwl-dsi"
+
+/* Possible platform specific clocks */
+#define NWL_DSI_CLK_CORE "core"
+
+enum nwl_dsi_ext_regs {
+ NWL_DSI_IMX_REG_GPR = BIT(1),
+};
+
+static const struct regmap_config nwl_dsi_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = NWL_DSI_IRQ_MASK2,
+ .name = DRV_NAME,
+};
+
+struct nwl_dsi_platform_data {
+ int (*poweron)(struct nwl_dsi *dsi);
+ int (*poweroff)(struct nwl_dsi *dsi);
+ void (*probe)(struct nwl_dsi *dsi);
+ void (*select_input)(struct nwl_dsi *dsi);
+ u32 ext_regs; /* required external registers */
+ struct nwl_dsi_plat_clk_config clk_config[NWL_DSI_MAX_PLATFORM_CLOCKS];
+};
+
+static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct nwl_dsi, bridge);
+}
+
+static int nwl_dsi_set_platform_clocks(struct nwl_dsi *dsi, bool enable)
+{
+ struct device *dev = dsi->dev;
+ const char *id;
+ struct clk *clk;
+ size_t i;
+ unsigned long rate;
+ int ret, result = 0;
+
+ DRM_DEV_DEBUG_DRIVER(dev, "%s platform clocks\n",
+enable ? "enabling" : "disabling");
+ for
[PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by: Guido Günther
---
.../bindings/display/bridge/nwl-dsi.yaml | 155 ++
1 file changed, 155 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
new file mode 100644
index ..5ed8bc4a4d18
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Northwest Logic MIPI-DSI on imx SoCs
+
+maintainers:
+ - Guido Gúnther
+ - Robert Chiras
+
+description: |
+ NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge
for
+ the SOCs NWL MIPI-DSI host controller.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+- const: fsl,imx8mq-nwl-dsi
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: DSI core clock
+ - description: RX_ESC clock (used in escape mode)
+ - description: TX_ESC clock (used in escape mode)
+ - description: PHY_REF clock
+
+ clock-names:
+items:
+ - const: core
+ - const: rx_esc
+ - const: tx_esc
+ - const: phy_ref
+
+ phys:
+maxItems: 1
+description:
+ A phandle to the phy module representing the DPHY
+
+ phy-names:
+items:
+ - const: dphy
+
+ power-domains:
+maxItems: 1
+description:
+ A phandle to the power domain
+
+ resets:
+maxItems: 4
+description:
+ A phandle to the reset controller
+
+ reset-names:
+items:
+ - const: byte
+ - const: dpi
+ - const: esc
+ - const: pclk
+
+ mux-sel:
+maxItems: 1
+description:
+ A phandle to the MUX register set
+
+ port:
+type: object
+description:
+ A input put or output port node.
+
+ ports:
+type: object
+description:
+ A node containing DSI input & output port nodes with endpoint
+ definitions as documented in
+ Documentation/devicetree/bindings/graph.txt.
+
+patternProperties:
+ "^panel@[0-9]+$": true
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - fsl,imx8mq-nwl-dsi
+then:
+ required:
+- resets
+- reset-names
+- mux-sel
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+
+examples:
+ - |
+
+ mipi_dsi: mipi_dsi@30a0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mq-nwl-dsi";
+ reg = <0x30A0 0x300>;
+ clocks = < 163>, < 244>, < 245>, < 164>;
+ clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
+ interrupts = <0 34 4>;
+ power-domains = <_mipi>;
+ resets = < 0>, < 1>, < 2>, < 3>;
+ reset-names = "byte", "dpi", "esc", "pclk";
+ mux-sel = <_gpr>;
+ phys = <>;
+ phy-names = "dphy";
+
+ panel@0 {
+ compatible = "...";
+ port@0 {
+ panel_in: endpoint {
+ remote-endpoint = <_dsi_out>;
+ };
+ };
+ };
+
+ ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+ reg = <0>;
+ mipi_dsi_in: endpoint {
+remote-endpoint = <_mipi_dsi>;
+ };
+};
+port@1 {
+ reg = <1>;
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <_in>;
+ };
+};
+ };
+ };
--
2.20.1
[PATCH v2 0/3] drm: bridge: Add NWL MIPI DSI host controller support
This adds initial support for the NWL MIPI DSI Host controller found on i.MX8
SoCs.
It adds support for the i.MX8MQ but the same IP core can also be found on e.g.
i.MX8QXP. I added the necessary hooks to support other imx8 variants but since
I only have imx8mq boards to test I omitted the platform data for other SoCs.
The code is based on NXPs BSP so I added Robert Chiras as
Co-authored-by. Robert, if this looks sane could you add your
Signed-off-by:?
The most notable changes over the BSP driver are
- Calculate HS mode timing from phy_configure_opts_mipi_dphy
- Perform all clock setup via DT
- Merge nwl-imx and nwl drivers
- Add B0 silion revision quirk
- Become a bridge driver to hook into mxsfb (from what I read[0] DCSS, which
also can drive the nwl on the imx8mq will likely not become part of
imx-display-subsystem so it makes sense to make it drive a bridge for dsi as
well).
- Use panel_bridge to attach the panel
This has been tested on a Librem 5 devkit using mxsfb with Robert's patches[1]
and the rocktech-jh057n00900 panel driver on next-20190807. The DCSS can later
on also act as input source too.
Changes from v1:
- Per review comments by Sam Ravnborg
https://lists.freedesktop.org/archives/dri-devel/2019-July/228130.html
- Change binding docs to YAML
- build: Don't always visit imx-nwl/
- build: Add header-test-y
- Sort headers according to DRM convention
- Use drm_display_mode instead of videmode
- Per review comments by Fabio Estevam
https://lists.freedesktop.org/archives/dri-devel/2019-July/228299.html
- Don't restrict build to ARCH_MXC
- Drop unused includes
- Drop unreachable code in imx_nwl_dsi_bridge_mode_fixup()
- Drop remaining calls of dev_err() and use DRM_DEV_ERR()
consistently.
- Use devm_platform_ioremap_resource()
- Drop devm_free_irq() in probe() error path
- Use single line comments where sufficient
- Use instead of defining USEC_PER_SEC
- Make input source select imx8 specific
- Drop inclusion (after removal of get_unaligned_le32)
- Drop all EXPORT_SYMBOL_GPL() for functions used in the same module
but different source files.
- Drop nwl_dsi_enable_{rx,tx}_clock() by invoking clk_prepare_enable()
directly
- Remove pointless comment
- Laurent Pinchart
https://lists.freedesktop.org/archives/dri-devel/2019-July/228313.html
https://lists.freedesktop.org/archives/dri-devel/2019-July/228308.html
- Drop (on iMX8MQ) unused csr regmap
- Use NWL_MAX_PLATFORM_CLOCKS everywhere
- Drop get_unaligned_le32() usage
- remove duplicate 'for the' in binding docs
- Don't include unused
- Don't include unused
- Drop dpms_mode for tracking state, trust the drm layer on that
- Use pm_runtime_put() instead of pm_runtime_put_sync()
- Don't overwrite encoder type
- Make imx_nwl_platform_data const
- Use the reset controller API instead of open coding that platform specific
part
- Use intead of making up our own defines
- name mipi_dsi_transfer less generic: nwl_dsi_transfer
- ensure clean in .remove by calling mipi_dsi_host_unregister.
- prefix constants by NWL_DSI_
- properly format transfer_direction enum
- simplify platform clock handling
- Don't modify state in mode_fixup() and use mode_set() instead
- Drop bridge detach(), already handle by nwl_dsi_host_detach()
- Drop USE_*_QUIRK() macros
- Drop (for now) unused clock defnitions. 'pixel' and 'bypass' clock will be
used for i.MX8 SoCs but since they're unused atm drop the definitions - but
keep the logic to enable/disable several clocks in place since we know we'll
need it in the future.
Changes from v0:
- Add quirk for IMQ8MQ silicon B0 revision to not mess with the
system reset controller on power down since enable() won't work
otherwise.
- Drop devm_free_irq() handled by the device driver core
- Disable tx esc clock after the phy power down to unbreak
disable/enable (unblank/blank)
- Add ports to dt binding docs
- Select GENERIC_PHY_MIPI_DPHY instead of GENERIC_PHY for
phy_mipi_dphy_get_default_config
- Select DRM_MIPI_DSI
- Include drm_print.h to fix build on next-20190408
- Drop some debugging messages
- Newline terminate all DRM_ printouts
- Turn component driver into a drm bridge
[0]: https://lists.freedesktop.org/archives/dri-devel/2019-May/219484.html
[1]: https://patchwork.freedesktop.org/series/62822/
Guido Günther (3):
arm64: imx8mq: add imx8mq iomux-gpr field defines
dt-bindings: display/bridge: Add binding for NWL mipi dsi host
controller
drm/bridge: Add NWL MIPI DSI host controller support
.../bindings/display/bridge/nwl-dsi.yaml | 155
drivers/gpu/drm/bridge/Kconfig| 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/nwl-dsi/Kconfig| 15 +
drivers/gpu/drm/bridge/nwl-dsi/Makefile | 4 +
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c | 484
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h | 66 ++
[PATCH v2 1/3] arm64: imx8mq: add imx8mq iomux-gpr field defines
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge. Signed-off-by: Guido Günther --- include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h | 62 1 file changed, 62 insertions(+) create mode 100644 include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h diff --git a/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file mode 100644 index ..62e85ffacfad --- /dev/null +++ b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 NXP + * 2019 Purism SPC + */ + +#ifndef __LINUX_IMX8MQ_IOMUXC_GPR_H +#define __LINUX_IMX8MQ_IOMUXC_GPR_H + +#define IOMUXC_GPR00x00 +#define IOMUXC_GPR10x04 +#define IOMUXC_GPR20x08 +#define IOMUXC_GPR30x0c +#define IOMUXC_GPR40x10 +#define IOMUXC_GPR50x14 +#define IOMUXC_GPR60x18 +#define IOMUXC_GPR70x1c +#define IOMUXC_GPR80x20 +#define IOMUXC_GPR90x24 +#define IOMUXC_GPR10 0x28 +#define IOMUXC_GPR11 0x2c +#define IOMUXC_GPR12 0x30 +#define IOMUXC_GPR13 0x34 +#define IOMUXC_GPR14 0x38 +#define IOMUXC_GPR15 0x3c +#define IOMUXC_GPR16 0x40 +#define IOMUXC_GPR17 0x44 +#define IOMUXC_GPR18 0x48 +#define IOMUXC_GPR19 0x4c +#define IOMUXC_GPR20 0x50 +#define IOMUXC_GPR21 0x54 +#define IOMUXC_GPR22 0x58 +#define IOMUXC_GPR23 0x5c +#define IOMUXC_GPR24 0x60 +#define IOMUXC_GPR25 0x64 +#define IOMUXC_GPR26 0x68 +#define IOMUXC_GPR27 0x6c +#define IOMUXC_GPR28 0x70 +#define IOMUXC_GPR29 0x74 +#define IOMUXC_GPR30 0x78 +#define IOMUXC_GPR31 0x7c +#define IOMUXC_GPR32 0x80 +#define IOMUXC_GPR33 0x84 +#define IOMUXC_GPR34 0x88 +#define IOMUXC_GPR35 0x8c +#define IOMUXC_GPR36 0x90 +#define IOMUXC_GPR37 0x94 +#define IOMUXC_GPR38 0x98 +#define IOMUXC_GPR39 0x9c +#define IOMUXC_GPR40 0xa0 +#define IOMUXC_GPR41 0xa4 +#define IOMUXC_GPR42 0xa8 +#define IOMUXC_GPR43 0xac +#define IOMUXC_GPR44 0xb0 +#define IOMUXC_GPR45 0xb4 +#define IOMUXC_GPR46 0xb8 +#define IOMUXC_GPR47 0xbc + +/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2) + +#endif /* __LINUX_IMX8MQ_IOMUXC_GPR_H */ -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111241] Shadertoy shader causing hang
https://bugs.freedesktop.org/show_bug.cgi?id=111241 --- Comment #5 from Pierre-Eric Pelloux-Prayer --- Created attachment 144994 --> https://bugs.freedesktop.org/attachment.cgi?id=144994=edit nir version -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111241] Shadertoy shader causing hang
https://bugs.freedesktop.org/show_bug.cgi?id=111241 --- Comment #4 from Pierre-Eric Pelloux-Prayer --- Created attachment 144993 --> https://bugs.freedesktop.org/attachment.cgi?id=144993=edit tgsi version of the shader -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111241] Shadertoy shader causing hang
https://bugs.freedesktop.org/show_bug.cgi?id=111241
--- Comment #3 from Pierre-Eric Pelloux-Prayer
---
Here's my understanding of the issue.
This shader uses 2 passes:
- the first pass has BufferA as input and output and does:
if (first frame)
// init bufferA content
else
// do something useful
- the 2nd pass has BufferA as input and does:
N = texelFetch(bufferA)
for(i=0; i < N; i++)
// do something
The problem here is the "// init bufferA content": it fails to initialize the
buffer content properly, leading to an infinite loop in the 2nd pass.
The exact code is:
if (iFrame==0) { O -= O; return; }
If one replaces this line with:
if (iFrame==0) { O = vec4(0.0f); return; }
The shader works fine (you can test the modified version here:
https://www.shadertoy.com/view/wtSXzw ).
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Re: [PATCH] drm/panfrost: Implement per FD address spaces
On Fri, Aug 9, 2019 at 6:45 AM Steven Price wrote: > > On 09/08/2019 04:01, Rob Herring wrote: > [...] > > I was worried too. It seems to be working pretty well though, but more > > testing would be good. I don't think there are a lot of usecases that > > use more AS than the h/w has (8 on T860), but I'm not sure. > > Yeah, 8 is overkill. Some GPUs only have 4 which is a little tight and > might come to bite when supporting queueing on the GPU. In this patch > panfrost_mmu_as_get() will simply WARN() then crash if there isn't a > free AS: > > > WARN_ON(!lru_mmu); > > > > list_del_init(_mmu->list); > > as = lru_mmu->as; > > This isn't a problem at the moment (there's a maximum of 2 jobs on the > GPU at the moment). But when you start queueing jobs it's possible for > each job to belong to a different address space. With three slots and > for each you can have one job running and one waiting that's a minimum > of 6 ASes, plus you might want one configured to dump counters. So a > total of 7 are needed to avoid having to wait. Hardware designers like > powers of 2 so we have 8. I think this could be solved by acquiring the AS in the job dependency hook instead. That may make the timeout handling more complicated as I'm not sure if dependencies are re-done. Tomeu is more familiar with the scheduler code, so I'll let him chime in. Rob ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] i2c: replace i2c_new_secondary_device with an ERR_PTR variant
Hi Laurent,
> > > > + if (IS_ERR(state->i2c_clients[i])) {
> > > > + err = PTR_ERR(state->i2c_clients[i]);
> > > > v4l2_err(sd, "failed to create i2c client
> > > > %u\n", i);
> > > > goto err_i2c;
>
> This will call adv76xx_unregister_clients(), which will try to
> i2c_unregister_device() all non-NULL i2c_clients entries. You need to
Uh, right! Sorry for missing this :(
> either set the entry to NULL here, or update
> adv76xx_unregister_clients() to skip IS_ERR() entries. My preference
> would be to store the return value of adv76xx_dummy_client() in a local
> variable here, and set state->i2c_clients[i] after the error check.
I implemented your preference and simplified
adv76xx_unregister_clients() because i2c_unregister_device is NULL
pointer aware. New patch coming in a minute.
Thanks for the review,
Wolfram
signature.asc
Description: PGP signature
[PATCH v2] i2c: replace i2c_new_secondary_device with an ERR_PTR variant
In the general move to have i2c_new_*_device functions which return
ERR_PTR instead of NULL, this patch converts i2c_new_secondary_device().
There are only few users, so this patch converts the I2C core and all
users in one go. The function gets renamed to i2c_new_ancillary_device()
so out-of-tree users will get a build failure to understand they need to
adapt their error checking code.
Signed-off-by: Wolfram Sang
Reviewed-by: Kieran Bingham # adv748x
Reviewed-by: Laurent Pinchart # adv7511
---
Changes since v1:
* adv7604: use a local variable for error handling
* adv7604: simplify unregistering dummy clients because I2C core helper
is NULL ptr aware
* added tags for adv748x and adv7511
Thanks Kieran and Laurent!
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 18
drivers/i2c/i2c-core-base.c | 10 -
drivers/media/i2c/adv748x/adv748x-core.c | 6 +++---
drivers/media/i2c/adv7604.c | 22 +++-
include/linux/i2c.h | 2 +-
5 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index f6d2681f6927..9e13e466e72c 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -981,10 +981,10 @@ static int adv7511_init_cec_regmap(struct adv7511 *adv)
{
int ret;
- adv->i2c_cec = i2c_new_secondary_device(adv->i2c_main, "cec",
+ adv->i2c_cec = i2c_new_ancillary_device(adv->i2c_main, "cec",
ADV7511_CEC_I2C_ADDR_DEFAULT);
- if (!adv->i2c_cec)
- return -EINVAL;
+ if (IS_ERR(adv->i2c_cec))
+ return PTR_ERR(adv->i2c_cec);
i2c_set_clientdata(adv->i2c_cec, adv);
adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
@@ -1165,20 +1165,20 @@ static int adv7511_probe(struct i2c_client *i2c, const
struct i2c_device_id *id)
adv7511_packet_disable(adv7511, 0x);
- adv7511->i2c_edid = i2c_new_secondary_device(i2c, "edid",
+ adv7511->i2c_edid = i2c_new_ancillary_device(i2c, "edid",
ADV7511_EDID_I2C_ADDR_DEFAULT);
- if (!adv7511->i2c_edid) {
- ret = -EINVAL;
+ if (IS_ERR(adv7511->i2c_edid)) {
+ ret = PTR_ERR(adv7511->i2c_edid);
goto uninit_regulators;
}
regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR,
adv7511->i2c_edid->addr << 1);
- adv7511->i2c_packet = i2c_new_secondary_device(i2c, "packet",
+ adv7511->i2c_packet = i2c_new_ancillary_device(i2c, "packet",
ADV7511_PACKET_I2C_ADDR_DEFAULT);
- if (!adv7511->i2c_packet) {
- ret = -EINVAL;
+ if (IS_ERR(adv7511->i2c_packet)) {
+ ret = PTR_ERR(adv7511->i2c_packet);
goto err_i2c_unregister_edid;
}
diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
index f26ed495d384..76cb91e064b8 100644
--- a/drivers/i2c/i2c-core-base.c
+++ b/drivers/i2c/i2c-core-base.c
@@ -966,7 +966,7 @@ struct i2c_client *devm_i2c_new_dummy_device(struct device
*dev,
EXPORT_SYMBOL_GPL(devm_i2c_new_dummy_device);
/**
- * i2c_new_secondary_device - Helper to get the instantiated secondary address
+ * i2c_new_ancillary_device - Helper to get the instantiated secondary address
* and create the associated device
* @client: Handle to the primary client
* @name: Handle to specify which secondary address to get
@@ -985,9 +985,9 @@ EXPORT_SYMBOL_GPL(devm_i2c_new_dummy_device);
* cell whose "reg-names" value matches the slave name.
*
* This returns the new i2c client, which should be saved for later use with
- * i2c_unregister_device(); or NULL to indicate an error.
+ * i2c_unregister_device(); or an ERR_PTR to describe the error.
*/
-struct i2c_client *i2c_new_secondary_device(struct i2c_client *client,
+struct i2c_client *i2c_new_ancillary_device(struct i2c_client *client,
const char *name,
u16 default_addr)
{
@@ -1002,9 +1002,9 @@ struct i2c_client *i2c_new_secondary_device(struct
i2c_client *client,
}
dev_dbg(>adapter->dev, "Address for %s : 0x%x\n", name, addr);
- return i2c_new_dummy(client->adapter, addr);
+ return i2c_new_dummy_device(client->adapter, addr);
}
-EXPORT_SYMBOL_GPL(i2c_new_secondary_device);
+EXPORT_SYMBOL_GPL(i2c_new_ancillary_device);
/* - */
diff --git a/drivers/media/i2c/adv748x/adv748x-core.c
b/drivers/media/i2c/adv748x/adv748x-core.c
index f57cd77a32fa..2567de2b0037 100644
--- a/drivers/media/i2c/adv748x/adv748x-core.c
+++ b/drivers/media/i2c/adv748x/adv748x-core.c
@@ -183,14
[PATCH] drm: Add high-precision time to vblank trace event
Store the timestamp of the current vblank in the new field 'time' of the
vblank trace event. If the timestamp is calculated by a driver that
supports high-precision vblank timing, set the field 'high-prec' to
'true'.
User space can now access actual hardware vblank times via the tracing
infrastructure. Tracing applications (such as GPUVis, see [0] for
related discussion), can use the newly added information to conduct a
more accurate analysis of display timing.
[0] https://github.com/mikesart/gpuvis/issues/30
Signed-off-by: Heinrich
---
drivers/gpu/drm/drm_trace.h | 14 ++
drivers/gpu/drm/drm_vblank.c | 3 ++-
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_trace.h b/drivers/gpu/drm/drm_trace.h
index baccc63db106..45f21d7fcfa1 100644
--- a/drivers/gpu/drm/drm_trace.h
+++ b/drivers/gpu/drm/drm_trace.h
@@ -11,17 +11,23 @@
#define TRACE_INCLUDE_FILE drm_trace
TRACE_EVENT(drm_vblank_event,
- TP_PROTO(int crtc, unsigned int seq),
- TP_ARGS(crtc, seq),
+ TP_PROTO(int crtc, unsigned int seq, ktime_t time, bool high_prec),
+ TP_ARGS(crtc, seq, time, high_prec),
TP_STRUCT__entry(
__field(int, crtc)
__field(unsigned int, seq)
+ __field(ktime_t, time)
+ __field(bool, high_prec)
),
TP_fast_assign(
__entry->crtc = crtc;
__entry->seq = seq;
- ),
- TP_printk("crtc=%d, seq=%u", __entry->crtc, __entry->seq)
+ __entry->time = time;
+ __entry->high_prec = high_prec;
+ ),
+ TP_printk("crtc=%d, seq=%u, time=%lld, high-prec=%s",
+ __entry->crtc, __entry->seq, __entry->time,
+ __entry->high_prec ? "true" : "false")
);
TRACE_EVENT(drm_vblank_event_queued,
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index a1b65d26d761..fb089a88b516 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -1706,7 +1706,8 @@ static void drm_handle_vblank_events(struct drm_device
*dev, unsigned int pipe)
send_vblank_event(dev, e, seq, now);
}
- trace_drm_vblank_event(pipe, seq);
+ trace_drm_vblank_event(pipe, seq, now,
+ dev->driver->get_vblank_timestamp != NULL);
}
/**
--
2.23.0.rc1
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[PATCH] drm/scheduler: use job count instead of peek
The spsc_queue_peek function is accessing queue->head which belongs to
the consumer thread and shouldn't be accessed by the producer
This is fixing a rare race condition when destroying entities.
Signed-off-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
b/drivers/gpu/drm/scheduler/sched_entity.c
index 35ddbec1375a..671c90f34ede 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -95,7 +95,7 @@ static bool drm_sched_entity_is_idle(struct drm_sched_entity
*entity)
rmb(); /* for list_empty to work without lock */
if (list_empty(>list) ||
- spsc_queue_peek(>job_queue) == NULL)
+ spsc_queue_count(>job_queue) == 0)
return true;
return false;
@@ -281,7 +281,7 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
/* Consumption of existing IBs wasn't completed. Forcefully
* remove them here.
*/
- if (spsc_queue_peek(>job_queue)) {
+ if (spsc_queue_count(>job_queue)) {
if (sched) {
/* Park the kernel for a moment to make sure it isn't
processing
* our enity.
--
2.17.1
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Re: [PATCH v2 2/2] drm: bridge: adv7511: Add support for ADV7535
Hi Bogdan.
This patch triggered a few general comments.
> --- a/drivers/gpu/drm/bridge/adv7511/Makefile
> +++ b/drivers/gpu/drm/bridge/adv7511/Makefile
> @@ -2,5 +2,5 @@
> adv7511-y := adv7511_drv.o
> adv7511-$(CONFIG_DRM_I2C_ADV7511_AUDIO) += adv7511_audio.o
> adv7511-$(CONFIG_DRM_I2C_ADV7511_CEC) += adv7511_cec.o
> -adv7511-$(CONFIG_DRM_I2C_ADV7533) += adv7533.o
> +adv7511-$(CONFIG_DRM_I2C_ADV753x) += adv7533.o
> obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h
> b/drivers/gpu/drm/bridge/adv7511/adv7511.h
> index 52b2adfdc877..38288c3c3c53 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
> @@ -91,6 +91,7 @@
> #define ADV7511_REG_ARC_CTRL 0xdf
> #define ADV7511_REG_CEC_I2C_ADDR 0xe1
> #define ADV7511_REG_CEC_CTRL 0xe2
> +#define ADV7511_REG_SUPPLY_SELECT0xe4
> #define ADV7511_REG_CHIP_ID_HIGH 0xf5
> #define ADV7511_REG_CHIP_ID_LOW 0xf6
>
> @@ -320,6 +321,7 @@ struct adv7511_video_config {
> enum adv7511_type {
> ADV7511,
> ADV7533,
> + ADV7535,
> };
>
> #define ADV7511_MAX_ADDRS 3
> @@ -393,7 +395,7 @@ static inline int adv7511_cec_init(struct device *dev,
> struct adv7511 *adv7511)
> }
> #endif
>
> -#ifdef CONFIG_DRM_I2C_ADV7533
> +#ifdef CONFIG_DRM_I2C_ADV753x
> void adv7533_dsi_power_on(struct adv7511 *adv);
> void adv7533_dsi_power_off(struct adv7511 *adv);
> void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode
> *mode);
The else part here define dummy functions.
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> index f6d2681f6927..b1501344df3e 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> @@ -367,7 +367,7 @@ static void adv7511_power_on(struct adv7511 *adv7511)
>*/
> regcache_sync(adv7511->regmap);
>
> - if (adv7511->type == ADV7533)
> + if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
> adv7533_dsi_power_on(adv7511);
In the driver we check for adv7511->type - and call
adv7533_dsi_power_on() only for the two types where we have this
function defined.
A simpler approach would be to always call adv7533_dsi_power_on(), and
let the existing logic pick up the right version.
The dummy version should then return 0 to say OK.
Same goes for several places below.
> adv7511->powered = true;
> }
> @@ -387,7 +387,7 @@ static void __adv7511_power_off(struct adv7511 *adv7511)
> static void adv7511_power_off(struct adv7511 *adv7511)
> {
> __adv7511_power_off(adv7511);
> - if (adv7511->type == ADV7533)
> + if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
> adv7533_dsi_power_off(adv7511);
> adv7511->powered = false;
> }
> @@ -761,7 +761,7 @@ static void adv7511_mode_set(struct adv7511 *adv7511,
> regmap_update_bits(adv7511->regmap, 0x17,
> 0x60, (vsync_polarity << 6) | (hsync_polarity << 5));
>
> - if (adv7511->type == ADV7533)
> + if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
> adv7533_mode_set(adv7511, adj_mode);
>
> drm_mode_copy(>curr_mode, adj_mode);
> @@ -874,7 +874,7 @@ static int adv7511_bridge_attach(struct drm_bridge
> *bridge)
>_connector_helper_funcs);
> drm_connector_attach_encoder(>connector, bridge->encoder);
>
> - if (adv->type == ADV7533)
> + if (adv->type == ADV7533 || adv->type == ADV7535)
> ret = adv7533_attach_dsi(adv);
>
> if (adv->i2c_main->irq)
> @@ -903,6 +903,7 @@ static const char * const adv7511_supply_names[] = {
> "dvdd-3v",
> };
>
> +/* The order of entries is important. If changed update hardcoded indices */
> static const char * const adv7533_supply_names[] = {
> "avdd",
> "dvdd",
> @@ -952,7 +953,7 @@ static bool adv7511_cec_register_volatile(struct device
> *dev, unsigned int reg)
> struct i2c_client *i2c = to_i2c_client(dev);
> struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
>
> - if (adv7511->type == ADV7533)
> + if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
> reg -= ADV7533_REG_CEC_OFFSET;
>
> switch (reg) {
> @@ -994,7 +995,7 @@ static int adv7511_init_cec_regmap(struct adv7511 *adv)
> goto err;
> }
>
> - if (adv->type == ADV7533) {
> + if (adv->type == ADV7533 || adv->type == ADV7535) {
> ret = adv7533_patch_cec_registers(adv);
> if (ret)
> goto err;
> @@ -1094,8 +1095,9 @@ static int adv7511_probe(struct i2c_client *i2c, const
> struct i2c_device_id *id)
> struct adv7511_link_config link_config;
> struct adv7511 *adv7511;
> struct device *dev = >dev;
> + struct regulator
[Bug 110258] Lenovo V110-15AST AMD A9-9410 AMD R5 Stoney hangs after waking after suspend. 5.0 onwards
https://bugs.freedesktop.org/show_bug.cgi?id=110258 --- Comment #12 from Alex Deucher --- Fix is on it's way upstream: https://cgit.freedesktop.org/drm/drm/commit/?h=drm-fixes=72cda9bb5e219aea0f2f62f56ae05198c59022a7 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111305] `ttm_bo_handle_move_mem` sometimes takes more than 50 ms
https://bugs.freedesktop.org/show_bug.cgi?id=111305 --- Comment #3 from Alex Deucher --- (In reply to Paul Menzel from comment #2) > > Just to clarify, the VRAM on the external graphics device is powered off, > correct? Correct. > > Are there any tools to analyze these delays? I guess profiling the relevant functions in ttm. See if we are waiting on pages, etc. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 110865] Rx480 consumes 20w more power in idle than under Windows
https://bugs.freedesktop.org/show_bug.cgi?id=110865 --- Comment #14 from Alex Deucher --- (In reply to Dieter Nützel from comment #13) > > Alex, is this the same problem? No. > > GFX Clocks and Power: > 300 MHz (MCLK) > 300 MHz (SCLK) Your mclk is going to a lower state when it's idle. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/panfrost: Implement per FD address spaces
cOn Fri, Aug 9, 2019 at 6:36 AM Steven Price wrote:
>
> On 08/08/2019 23:29, Rob Herring wrote:
> > Up until now, a single shared GPU address space was used. This is not
> > ideal as there's no protection between processes and doesn't work for
> > supporting the same GPU/CPU VA feature. Most importantly, this will
> > hopefully mitigate Alyssa's fear of WebGL, whatever that is.
> >
> > Most of the changes here are moving struct drm_mm and struct
> > panfrost_mmu objects from the per device struct to the per FD struct.
> > The critical function is panfrost_mmu_as_get() which handles allocating
> > and switching the h/w address spaces.
> >
> > Cc: Tomeu Vizoso
> > Cc: David Airlie
> > Cc: Daniel Vetter
> > Cc: Robin Murphy
> > Cc: Steven Price
> > Cc: Alyssa Rosenzweig
> > Signed-off-by: Rob Herring
> > ---
> > This depends on madvise support (now in drm-misc) and the heap/no-exec
> > series (just the rework). Seeems to be working pretty well for me, but
> > more testing would be helpful. I've run multiple 'glmark2-es2-drm
> > --off-screen' instances and Gnome Shell. Running more than 8 clients (at
> > least for T860) will hit the address space switch code paths.
> >
> > Rob
> >
> > drivers/gpu/drm/panfrost/TODO | 4 -
> > drivers/gpu/drm/panfrost/panfrost_device.c | 2 +
> > drivers/gpu/drm/panfrost/panfrost_device.h | 24 ++-
> > drivers/gpu/drm/panfrost/panfrost_drv.c| 31 ++-
> > drivers/gpu/drm/panfrost/panfrost_gem.c| 15 +-
> > drivers/gpu/drm/panfrost/panfrost_gem.h| 3 +
> > drivers/gpu/drm/panfrost/panfrost_job.c| 12 +-
> > drivers/gpu/drm/panfrost/panfrost_mmu.c| 220 +++--
> > drivers/gpu/drm/panfrost/panfrost_mmu.h| 8 +
> > 9 files changed, 239 insertions(+), 80 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/panfrost/TODO b/drivers/gpu/drm/panfrost/TODO
> > index e7727b292355..536a0d4f8d29 100644
> > --- a/drivers/gpu/drm/panfrost/TODO
> > +++ b/drivers/gpu/drm/panfrost/TODO
> > @@ -6,10 +6,6 @@
> >- Bifrost specific feature and issue handling
> >- Coherent DMA support
> >
> > -- Per FD address space support. The h/w supports multiple addresses spaces.
> > - The hard part is handling when more address spaces are needed than what
> > - the h/w provides.
> > -
> > - Support userspace controlled GPU virtual addresses. Needed for Vulkan.
> > (Tomeu)
> >
> > - Compute job support. So called 'compute only' jobs need to be plumbed up
> > to
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
> > b/drivers/gpu/drm/panfrost/panfrost_device.c
> > index 9814f4ccbd26..4da71bb56c20 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > @@ -123,8 +123,10 @@ int panfrost_device_init(struct panfrost_device *pfdev)
> > mutex_init(>sched_lock);
> > mutex_init(>reset_lock);
> > INIT_LIST_HEAD(>scheduled_jobs);
> > + INIT_LIST_HEAD(>as_lru_list);
> >
> > spin_lock_init(>hwaccess_lock);
> > + spin_lock_init(>as_lock);
> >
> > err = panfrost_clk_init(pfdev);
> > if (err) {
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
> > b/drivers/gpu/drm/panfrost/panfrost_device.h
> > index 4e5641db9c7e..f503c566e99f 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> > @@ -5,6 +5,8 @@
> > #ifndef __PANFROST_DEVICE_H__
> > #define __PANFROST_DEVICE_H__
> >
> > +#include
> > +#include
> > #include
> > #include
> > #include
> > @@ -63,9 +65,6 @@ struct panfrost_device {
> >
> > spinlock_t hwaccess_lock;
> >
> > - struct drm_mm mm;
> > - spinlock_t mm_lock;
> > -
> > void __iomem *iomem;
> > struct clk *clock;
> > struct clk *bus_clock;
> > @@ -74,7 +73,11 @@ struct panfrost_device {
> >
> > struct panfrost_features features;
> >
> > - struct panfrost_mmu *mmu;
> > + spinlock_t as_lock;
> > + unsigned long as_in_use_mask;
> > + unsigned long as_alloc_mask;
> > + struct list_head as_lru_list;
> > +
> > struct panfrost_job_slot *js;
> >
> > struct panfrost_job *jobs[NUM_JOB_SLOTS];
> > @@ -98,10 +101,23 @@ struct panfrost_device {
> > } devfreq;
> > };
> >
> > +struct panfrost_mmu {
> > + struct io_pgtable_cfg pgtbl_cfg;
> > + struct io_pgtable_ops *pgtbl_ops;
> > + struct mutex lock;
> > + int as;
> > + atomic_t as_count;
> > + struct list_head list;
> > +};
> > +
> > struct panfrost_file_priv {
> > struct panfrost_device *pfdev;
> >
> > struct drm_sched_entity sched_entity[NUM_JOB_SLOTS];
> > +
> > + struct panfrost_mmu mmu;
> > + struct drm_mm mm;
> > + spinlock_t mm_lock;
> > };
> >
> > static inline struct panfrost_device *to_panfrost_device(struct drm_device
> > *ddev)
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c
> > b/drivers/gpu/drm/panfrost/panfrost_drv.c
> > index a1352750984c..7c8aa1a8054f
Re: [PATCH 02/22] ARM: omap1: make omapfb standalone compilable
On 8/9/19 1:43 PM, Arnd Bergmann wrote: > On Fri, Aug 9, 2019 at 1:32 PM Bartlomiej Zolnierkiewicz > wrote: >> On 8/8/19 11:22 PM, Arnd Bergmann wrote: >>> The omapfb driver is split into platform specific code for omap1, and >>> driver code that is also specific to omap1. >>> >>> Moving both parts into the driver directory simplifies the structure >>> and avoids the dependency on certain omap machine header files. >>> >>> The interrupt numbers in particular however must not be referenced >>> directly from the driver to allow building in a multiplatform >>> configuration, so these have to be passed through resources, is >>> done for all other omap drivers. >>> >>> Signed-off-by: Arnd Bergmann >> >> For fbdev part: >> >> Acked-by: Bartlomiej Zolnierkiewicz > > Thanks for taking a look. > >> [ It seems that adding of static inline for omap_set_dma_priority() >> when ARCH_OMAP=n should be in patch #9 but this is a minor issue. ] > > That would have been ok as well, but having the addition here was > intentional and seems more logical to me as this is where the headers > get moved around. I see that this is an optimization for making the patch series more compact but I think that this addition logically belongs to patch #9 (which adds support for COMPILE_TEST) where the new code is required. Moreover patch description for patch #2 lacks any comment about this addition being a preparation for changes in patch #9 so I was quite puzzled about its purpose when seeing it first. Therefore please have mercy on the poor/stupid reviewer and don't do such optimizations intentionally (or at least describe them properly somewhere).. ;-) Best regards, -- Bartlomiej Zolnierkiewicz Samsung R Institute Poland Samsung Electronics ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH for-5.3] drm/omap: ensure we have a valid dma_mask
On Fri, Aug 09, 2019 at 01:00:38PM +0300, Tomi Valkeinen wrote: > Alright, thanks for the clarification! > > Here's my version. Looks god to me: Reviewed-by: Christoph Hellwig
[PATCH v2 0/2] drm: bridge: adv7511: Add support For ADV7535
This patch-set add support for ADV7535 part in ADV7511 driver. ADV7535 and ADV7533 are pin to pin compatible parts but ADV7535 support TMDS clock upto 148.5Mhz and resolutions up to 1080p@60Hz. --- Changes in v2: - rename CONFIG_DRM_I2C_ADV7533 to CONFIG_DRM_I2C_ADV753X and update decription - removed "v1p2" index search and hardcoded it Bogdan Togorean (2): dt-bindings: drm: bridge: adv7511: Add ADV7535 support drm: bridge: adv7511: Add support for ADV7535 .../bindings/display/bridge/adi,adv7511.txt | 23 +++-- drivers/gpu/drm/bridge/adv7511/Kconfig| 8 ++--- drivers/gpu/drm/bridge/adv7511/Makefile | 2 +- drivers/gpu/drm/bridge/adv7511/adv7511.h | 4 ++- drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 34 +-- 5 files changed, 44 insertions(+), 27 deletions(-) -- 2.22.0
[PATCH v2 2/2] drm: bridge: adv7511: Add support for ADV7535
ADV7535 is a DSI to HDMI bridge chip like ADV7533 but it allows
1080p@60Hz. v1p2 is fixed to 1.8V on ADV7535 but on ADV7533 can be 1.2V
or 1.8V and is configurable in a register.
Signed-off-by: Bogdan Togorean
---
drivers/gpu/drm/bridge/adv7511/Kconfig | 8 ++---
drivers/gpu/drm/bridge/adv7511/Makefile | 2 +-
drivers/gpu/drm/bridge/adv7511/adv7511.h | 4 ++-
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 34 ++--
4 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/bridge/adv7511/Kconfig
b/drivers/gpu/drm/bridge/adv7511/Kconfig
index 8a56ff81f4fb..fa43acd46ab7 100644
--- a/drivers/gpu/drm/bridge/adv7511/Kconfig
+++ b/drivers/gpu/drm/bridge/adv7511/Kconfig
@@ -15,16 +15,16 @@ config DRM_I2C_ADV7511_AUDIO
Support the ADV7511 HDMI Audio interface. This is used in
conjunction with the AV7511 HDMI driver.
-config DRM_I2C_ADV7533
- bool "ADV7533 encoder"
+config DRM_I2C_ADV753x
+ bool "ADV753x encoder"
depends on DRM_I2C_ADV7511
select DRM_MIPI_DSI
default y
help
- Support for the Analog Devices ADV7533 DSI to HDMI encoder.
+ Support for the Analog Devices ADV7533/5 DSI to HDMI encoder.
config DRM_I2C_ADV7511_CEC
- bool "ADV7511/33 HDMI CEC driver"
+ bool "ADV7511/33/35 HDMI CEC driver"
depends on DRM_I2C_ADV7511
select CEC_CORE
default y
diff --git a/drivers/gpu/drm/bridge/adv7511/Makefile
b/drivers/gpu/drm/bridge/adv7511/Makefile
index b46ebeb35fd4..319efddb268e 100644
--- a/drivers/gpu/drm/bridge/adv7511/Makefile
+++ b/drivers/gpu/drm/bridge/adv7511/Makefile
@@ -2,5 +2,5 @@
adv7511-y := adv7511_drv.o
adv7511-$(CONFIG_DRM_I2C_ADV7511_AUDIO) += adv7511_audio.o
adv7511-$(CONFIG_DRM_I2C_ADV7511_CEC) += adv7511_cec.o
-adv7511-$(CONFIG_DRM_I2C_ADV7533) += adv7533.o
+adv7511-$(CONFIG_DRM_I2C_ADV753x) += adv7533.o
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h
b/drivers/gpu/drm/bridge/adv7511/adv7511.h
index 52b2adfdc877..38288c3c3c53 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
@@ -91,6 +91,7 @@
#define ADV7511_REG_ARC_CTRL 0xdf
#define ADV7511_REG_CEC_I2C_ADDR 0xe1
#define ADV7511_REG_CEC_CTRL 0xe2
+#define ADV7511_REG_SUPPLY_SELECT 0xe4
#define ADV7511_REG_CHIP_ID_HIGH 0xf5
#define ADV7511_REG_CHIP_ID_LOW0xf6
@@ -320,6 +321,7 @@ struct adv7511_video_config {
enum adv7511_type {
ADV7511,
ADV7533,
+ ADV7535,
};
#define ADV7511_MAX_ADDRS 3
@@ -393,7 +395,7 @@ static inline int adv7511_cec_init(struct device *dev,
struct adv7511 *adv7511)
}
#endif
-#ifdef CONFIG_DRM_I2C_ADV7533
+#ifdef CONFIG_DRM_I2C_ADV753x
void adv7533_dsi_power_on(struct adv7511 *adv);
void adv7533_dsi_power_off(struct adv7511 *adv);
void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode
*mode);
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index f6d2681f6927..b1501344df3e 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -367,7 +367,7 @@ static void adv7511_power_on(struct adv7511 *adv7511)
*/
regcache_sync(adv7511->regmap);
- if (adv7511->type == ADV7533)
+ if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
adv7533_dsi_power_on(adv7511);
adv7511->powered = true;
}
@@ -387,7 +387,7 @@ static void __adv7511_power_off(struct adv7511 *adv7511)
static void adv7511_power_off(struct adv7511 *adv7511)
{
__adv7511_power_off(adv7511);
- if (adv7511->type == ADV7533)
+ if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
adv7533_dsi_power_off(adv7511);
adv7511->powered = false;
}
@@ -761,7 +761,7 @@ static void adv7511_mode_set(struct adv7511 *adv7511,
regmap_update_bits(adv7511->regmap, 0x17,
0x60, (vsync_polarity << 6) | (hsync_polarity << 5));
- if (adv7511->type == ADV7533)
+ if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
adv7533_mode_set(adv7511, adj_mode);
drm_mode_copy(>curr_mode, adj_mode);
@@ -874,7 +874,7 @@ static int adv7511_bridge_attach(struct drm_bridge *bridge)
_connector_helper_funcs);
drm_connector_attach_encoder(>connector, bridge->encoder);
- if (adv->type == ADV7533)
+ if (adv->type == ADV7533 || adv->type == ADV7535)
ret = adv7533_attach_dsi(adv);
if (adv->i2c_main->irq)
@@ -903,6 +903,7 @@ static const char * const adv7511_supply_names[] = {
"dvdd-3v",
};
+/* The order of entries is important. If changed update hardcoded indices */
static const char * const adv7533_supply_names[] =
[PATCH v2 1/2] dt-bindings: drm: bridge: adv7511: Add ADV7535 support
ADV7535 is a part compatible with ADV7533 but it supports 1080p@60hz and v1p2 supply is fixed to 1.8V Signed-off-by: Bogdan Togorean --- .../bindings/display/bridge/adi,adv7511.txt | 23 ++- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt index 2c887536258c..e8ddec5d9d91 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt @@ -1,10 +1,10 @@ -Analog Device ADV7511(W)/13/33 HDMI Encoders +Analog Device ADV7511(W)/13/33/35 HDMI Encoders - -The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters -compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, -S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while -the others support RGB interface. +The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video +transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space +conversion, S/PDIF, CEC and HDCP. ADV7533/5 supports the DSI interface for input +pixels, while the others support RGB interface. Required properties: @@ -13,6 +13,7 @@ Required properties: "adi,adv7511w" "adi,adv7513" "adi,adv7533" + "adi,adv7535" - reg: I2C slave addresses The ADV7511 internal registers are split into four pages exposed through @@ -52,14 +53,14 @@ The following input format properties are required except in "rgb 1x" and - bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is needed only for ADV7511. -The following properties are required for ADV7533: +The following properties are required for ADV7533 and ADV7535: - adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should be one of 1, 2, 3 or 4. - a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip. - v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip. - v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be - either 1.2V or 1.8V. + either 1.2V or 1.8V for ADV7533 but only 1.8V for ADV7535. Optional properties: @@ -71,9 +72,9 @@ Optional properties: - adi,embedded-sync: The input uses synchronization signals embedded in the data stream (similar to BT.656). Defaults to separate H/V synchronization signals. -- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing - generator. The chip will rely on the sync signals in the DSI data lanes, - rather than generate its own timings for HDMI output. +- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the + internal timing generator. The chip will rely on the sync signals in the + DSI data lanes, rather than generate its own timings for HDMI output. - clocks: from common clock binding: reference to the CEC clock. - clock-names: from common clock binding: must be "cec". - reg-names : Names of maps with programmable addresses. @@ -85,7 +86,7 @@ Required nodes: The ADV7511 has two video ports. Their connections are modelled using the OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. -- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the +- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533/5, the remote endpoint phandle should be a reference to a valid mipi_dsi_host device node. - Video port 1 for the HDMI output -- 2.22.0
[PATCH v2] drm/virtio: use virtio_max_dma_size
We must make sure our scatterlist segments are not too big, otherwise we might see swiotlb failures (happens with sev, also reproducable with swiotlb=force). Suggested-by: Laszlo Ersek Signed-off-by: Gerd Hoffmann --- drivers/gpu/drm/virtio/virtgpu_object.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c index b2da31310d24..6e44568813dd 100644 --- a/drivers/gpu/drm/virtio/virtgpu_object.c +++ b/drivers/gpu/drm/virtio/virtgpu_object.c @@ -204,6 +204,7 @@ int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev, .interruptible = false, .no_wait_gpu = false }; + unsigned max_segment; /* wtf swapping */ if (bo->pages) @@ -215,8 +216,13 @@ int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev, if (!bo->pages) goto out; - ret = sg_alloc_table_from_pages(bo->pages, pages, nr_pages, 0, - nr_pages << PAGE_SHIFT, GFP_KERNEL); + max_segment = virtio_max_dma_size(qdev->vdev); + max_segment &= ~(size_t)(PAGE_SIZE - 1); + if (max_segment > SCATTERLIST_MAX_SEGMENT) + max_segment = SCATTERLIST_MAX_SEGMENT; + ret = __sg_alloc_table_from_pages(bo->pages, pages, nr_pages, 0, + nr_pages << PAGE_SHIFT, + max_segment, GFP_KERNEL); if (ret) goto out; return 0; -- 2.18.1
[GIT PULL] fbdev fix for v5.3-rc4
Hi Linus, Please pull fbdev fix for v5.3-rc4 (fbdev patches will now go to upstream through drm-misc tree for improved maintainership and better integration testing so update MAINTAINERS file accordingly). Best regards, -- Bartlomiej Zolnierkiewicz Samsung R Institute Poland Samsung Electronics The following changes since commit e21a712a9685488f5ce80495b37b9fdbe96c230d: Linux 5.3-rc3 (2019-08-04 18:40:12 -0700) are available in the git repository at: https://github.com/bzolnier/linux.git tags/fbdev-v5.3-rc4 for you to fetch changes up to 6a7553e8d84d5322d883cb83bb9888c49a0f04e0: MAINTAINERS: handle fbdev changes through drm-misc tree (2019-08-09 15:46:40 +0200) fbdev fix for v5.3-rc4: - update fbdev git tree in MAINTAINERS file Bartlomiej Zolnierkiewicz (1): MAINTAINERS: handle fbdev changes through drm-misc tree MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 108718] Raven Ridge: ring sdma0 timeout on heavy CSS website with Firefox WebRender
https://bugs.freedesktop.org/show_bug.cgi?id=108718 --- Comment #2 from Pierre-Eric Pelloux-Prayer --- Can you still reproduce this issue? It seems to work fine here with a recent kernel + mesa configuration. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 8/8] drm/etnaviv: implement per-process address spaces on MMUv2
Am Freitag, den 09.08.2019, 14:04 +0200 schrieb Lucas Stach:
> This builds on top of the MMU contexts introduced earlier. Instead of having
> one context per GPU core, each GPU client receives its own context.
>
> On MMUv1 this still means a single shared pagetable set is used by all
> clients, but on MMUv2 there is now a distinct set of pagetables for each
> client. As the command fetch is also translated via the MMU on MMUv2 the
> kernel command ringbuffer is mapped into each of the client pagetables.
>
> As the MMU context switch is a bit of a heavy operation, due to the needed
> cache and TLB flushing, this patch implements a lazy way of switching the
> MMU context. The kernel does not have its own MMU context, but reuses the
> last client context for all of its operations. This has some visible impact,
> as the GPU can now only be started once a client has submitted some work and
> we got the client MMU context assigned. Also the MMU context has a different
> lifetime than the general client context, as the GPU might still execute the
> kernel command buffer in the context of a client even after the client has
> completed all GPU work and has been terminated. Only when the GPU is runtime
> suspended or switches to another clients MMU context is the old context
> freed up.
>
> > Signed-off-by: Lucas Stach
> ---
> v3: Don't call etnaviv_cmdbuf_suballoc_unmap when mapping failed.
> ---
[...]
> /*
> @@ -308,7 +312,8 @@ void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu,
> unsigned int event)
>
> /* Append a command buffer to the ring buffer. */
> void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
> > - unsigned int event, struct etnaviv_cmdbuf *cmdbuf)
> > + struct etnaviv_iommu_context *mmu_context, unsigned int event,
> > + struct etnaviv_cmdbuf *cmdbuf)
> {
> > struct etnaviv_cmdbuf *buffer = >buffer;
> > unsigned int waitlink_offset = buffer->user_size - 16;
> @@ -317,17 +322,19 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
> exec_state,
> > bool switch_context = gpu->exec_state != exec_state;
> > unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
> > bool need_flush = gpu->flush_seq != new_flush_seq;
> + bool switch_mmu_context = gpu->mmu_context != mmu_context;
I screwed up this one during the rework to avoid the flush sequence
race. I'll squash the following into this commit:
--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
@@ -320,9 +320,9 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
exec_state,
u32 return_target, return_dwords;
u32 link_target, link_dwords;
bool switch_context = gpu->exec_state != exec_state;
- unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
- bool need_flush = gpu->flush_seq != new_flush_seq;
bool switch_mmu_context = gpu->mmu_context != mmu_context;
+ unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
+ bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;
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[PATCH v5 1/1] drm/syncobj: add sideband payload
The Vulkan timeline semaphores allow signaling to happen on the point
of the timeline without all of the its dependencies to be created.
The current 2 implementations (AMD/Intel) of the Vulkan spec on top of
the Linux kernel are using a thread to wait on the dependencies of a
given point to materialize and delay actual submission to the kernel
driver until the wait completes.
If a binary semaphore is submitted for signaling along the side of a
timeline semaphore waiting for completion that means that the drm
syncobj associated with that binary semaphore will not have a DMA
fence associated with it by the time vkQueueSubmit() returns. This and
the fact that a binary semaphore can be signaled and unsignaled as
before its DMA fences materialize mean that we cannot just rely on the
fence within the syncobj but we also need a sideband payload verifying
that the fence in the syncobj matches the last submission from the
Vulkan API point of view.
This change adds a sideband payload that is incremented with signaled
syncobj when vkQueueSubmit() is called. The next vkQueueSubmit()
waiting on a the syncobj will read the sideband payload and wait for a
fence chain element with a seqno superior or equal to the sideband
payload value to be added into the fence chain and use that fence to
trigger the submission on the kernel driver.
v2: Use a separate ioctl to get/set the sideband value (Christian)
v3: Use 2 ioctls for get/set (Christian)
v4: Use a single new ioctl
v5: a bunch of blattant mistakes
Store payload atomically (Chris)
Signed-off-by: Lionel Landwerlin
Cc: Christian Koenig
Cc: Jason Ekstrand
Cc: David(ChunMing) Zhou
---
drivers/gpu/drm/drm_internal.h | 2 ++
drivers/gpu/drm/drm_ioctl.c| 3 ++
drivers/gpu/drm/drm_syncobj.c | 58 +-
include/drm/drm_syncobj.h | 9 ++
include/uapi/drm/drm.h | 17 ++
5 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 51a2055c8f18..e297dfd85019 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -208,6 +208,8 @@ int drm_syncobj_timeline_signal_ioctl(struct drm_device
*dev, void *data,
struct drm_file *file_private);
int drm_syncobj_query_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_private);
+int drm_syncobj_binary_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file_private);
/* drm_framebuffer.c */
void drm_framebuffer_print_info(struct drm_printer *p, unsigned int indent,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index f675a3bb2c88..644d0bc800a4 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -703,6 +703,9 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_QUERY, drm_syncobj_query_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_BINARY, drm_syncobj_binary_ioctl,
+ DRM_RENDER_ALLOW),
+
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_GET_SEQUENCE, drm_crtc_get_sequence_ioctl,
0),
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_QUEUE_SEQUENCE,
drm_crtc_queue_sequence_ioctl, 0),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_LEASE, drm_mode_create_lease_ioctl,
DRM_MASTER),
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index b927e482e554..d2d3a8d1374d 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -1150,8 +1150,10 @@ drm_syncobj_reset_ioctl(struct drm_device *dev, void
*data,
if (ret < 0)
return ret;
- for (i = 0; i < args->count_handles; i++)
+ for (i = 0; i < args->count_handles; i++) {
drm_syncobj_replace_fence(syncobjs[i], NULL);
+ atomic64_set([i]->binary_payload, 0);
+ }
drm_syncobj_array_free(syncobjs, args->count_handles);
@@ -1321,6 +1323,60 @@ int drm_syncobj_query_ioctl(struct drm_device *dev, void
*data,
if (ret)
break;
}
+
+ drm_syncobj_array_free(syncobjs, args->count_handles);
+
+ return ret;
+}
+
+int drm_syncobj_binary_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file_private)
+{
+ struct drm_syncobj_binary_array *args = data;
+ struct drm_syncobj **syncobjs;
+ u32 __user *access_flags = u64_to_user_ptr(args->access_flags);
+ u64 __user *values = u64_to_user_ptr(args->values);
+ u32 i;
+ int ret;
+
+ if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ_TIMELINE))
+ return -EOPNOTSUPP;
+
+ if (args->pad != 0)
+ return -EINVAL;
+
+ if (args->count_handles == 0)
+ return -EINVAL;
+
+ ret = drm_syncobj_array_find(file_private,
+
[PATCH v5 0/1] drm/syncobj: add syncobj sideband payload for threaded submission
A bunch of fixes :) Lionel Landwerlin (1): drm/syncobj: add sideband payload drivers/gpu/drm/drm_internal.h | 2 ++ drivers/gpu/drm/drm_ioctl.c| 3 ++ drivers/gpu/drm/drm_syncobj.c | 58 +- include/drm/drm_syncobj.h | 9 ++ include/uapi/drm/drm.h | 17 ++ 5 files changed, 88 insertions(+), 1 deletion(-) -- 2.23.0.rc1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 24/60] drm/panel: Add driver for the Toppology TD043MTEA1 panel
Hi Laurent.
> > > +static int td043mtea1_disable(struct drm_panel *panel)
> > > +{
> > > + struct td043mtea1_device *lcd = to_td043mtea1_device(panel);
> > > +
> > > + if (!lcd->spi_suspended)
> > > + td043mtea1_power_off(lcd);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int td043mtea1_enable(struct drm_panel *panel)
> > > +{
> > > + struct td043mtea1_device *lcd = to_td043mtea1_device(panel);
> > > + int ret;
> > > +
> > > + /*
> > > + * If we are resuming from system suspend, SPI might not be enabled
> > > + * yet, so we'll program the LCD from SPI PM resume callback.
> > > + */
> > > + if (lcd->spi_suspended)
> > > + return 0;
> >
> > I do not recall this is needed in other panel drivers, so look at what
> > other spi based panels do here.
> > I think this is something that today is not required.
>
> The problem here is that the display controller may be resumed before
> the SPI bus. Has that been solved somewhere in core code ?
I dunno. So the conclusion is to keep it as is, and any change
will wait until someone with HW can step up.
As for all your other feedback to this and the other panel drivers
they did not trigger any repsonse from me.
Looks forward for next iteration of this nice set of patches.
Can we maybe get the panel drivers in before some of the infrastructure
work?
I know the users then may come a bit later, but I think thats OK.
Sam
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Re: [PATCH v4 1/1] drm/syncobj: add sideband payload
On 09/08/2019 15:27, Koenig, Christian wrote:
Am 09.08.19 um 14:26 schrieb Lionel Landwerlin:
On 09/08/2019 14:44, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-08-09 12:30:30)
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 8a5b2f8f8eb9..1ce83853f997 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -785,6 +785,22 @@ struct drm_syncobj_timeline_array {
__u32 pad;
};
+struct drm_syncobj_binary_array {
+ /* A pointer to an array of u32 syncobj handles. */
+ __u64 handles;
+ /* A pointer to an array of u32 access flags for each
handle. */
+ __u64 access_flags;
+ /* The binary value of a syncobj is read before it is
incremented. */
+#define I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_READ (1u << 0)
+#define I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_INC (1u << 1)
You're not in Kansas anymore ;)
-Chris
Which means? :)
You are in common DRM code, but the new defines start with I915_
Cheers,
Christian.
Oh dear...
-Lionel
-Lionel
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Re: [PATCH v4 1/1] drm/syncobj: add sideband payload
Quoting Lionel Landwerlin (2019-08-09 13:38:57) > On 09/08/2019 14:58, Chris Wilson wrote: > > Not atomic (the u64 write should really be to avoid total corruption) > > and nothing prevents userspace from racing. How safe is that in the > > overall design? > > > Atomic would prevent issue related to 2 processes/threads seeing > different values because of caching? No, the kernel atomics themselves do not guarantee memory barriers in all cases. The issue I see here is that we can not safely do a u64 increment on all platforms without write tearing. E.g. two clients simultaneously incrementing from U32_MAX becomes 0x1 (both would report U32_MAX) -Chris ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 1/1] drm/syncobj: add sideband payload
Quoting Chris Wilson (2019-08-09 12:58:51)
> Quoting Lionel Landwerlin (2019-08-09 12:30:30)
> > + if (flags & I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_READ) {
> > + copy_to_user([i],
> > [i]->binary_payload, sizeof(values[i]));
> > + ret = ret ? -EFAULT : 0;
>
> More magic.
>
> if (put_user([i]->binary_payload, [i]))
> return -EFAULT;
(break not yet)
Should just be put_user(syncobjs[i]->binary_payload, [i])
The value of, not its address.
-Chris
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Re: [PATCH v4 1/1] drm/syncobj: add sideband payload
On 09/08/2019 14:58, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-08-09 12:30:30)
+int drm_syncobj_binary_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file_private)
+{
+ struct drm_syncobj_binary_array *args = data;
+ struct drm_syncobj **syncobjs;
+ u32 __user *access_flags = u64_to_user_ptr(args->access_flags);
+ u64 __user *values = u64_to_user_ptr(args->values);
+ u32 i;
+ int ret;
+
+ if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ_TIMELINE))
+ return -EOPNOTSUPP;
+
+ if (args->pad != 0)
+ return -EINVAL;
+
+ if (args->count_handles == 0)
+ return -EINVAL;
You may find it easier to just return success for 0 handles. Slightly less
obnoxious error handling?
All the other ioctls in this file return EINVAL in that case. I'm just
going for consistency.
It's also a good indication for the application it can save itself an
ioctl really :)
+ ret = drm_syncobj_array_find(file_private,
+u64_to_user_ptr(args->handles),
+args->count_handles,
+);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < args->count_handles; i++) {
+ u32 flags;
+
+ copy_from_user(, _flags[i], sizeof(flags));
+ ret = ret ? -EFAULT : 0;
Magic?
if (get_user(flags, _flags[i[))
return -EFAULT;
I give this no testing, I'm just trying to get some feedback about the
direction.
Thanks though :)
+ if (ret)
+ break;
+
+ if (flags & I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_READ) {
+ copy_to_user([i], [i]->binary_payload,
sizeof(values[i]));
+ ret = ret ? -EFAULT : 0;
More magic.
if (put_user([i]->binary_payload, [i]))
return -EFAULT;
+ if (ret)
+ break;
+ }
+
+ if (flags & I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_INC)
+ syncobjs[i]->binary_payload++;
So if an error occurs how does the user know which syncobj were
advanced before the error? (Or explain why it doesn't actually matter)
The clue I guess is with read/inc, but confirmation of design would be
nice.
I guess we could toggle the access flag bits to notify that the actions
were completed.
Not atomic (the u64 write should really be to avoid total corruption)
and nothing prevents userspace from racing. How safe is that in the
overall design?
Atomic would prevent issue related to 2 processes/threads seeing
different values because of caching?
If not then it's not really interesting for the use case. The increment
should happen during the vkQueueSubmit() call and the value is only
valid upon returning.
The application is responsible for not having
vkQueueSubmit()/vkWaitForFences() race.
Not opposed to switch to atomic though.
What would happen if the binary_payload was initialised to -1?
The 0 value is problematic because it's also used for "whatever fence in
the syncobj".
I think we need to stick to the same rules as the timeline values : 0 is
always signaled
Thanks,
-Lionel
+ }
+
drm_syncobj_array_free(syncobjs, args->count_handles);
return ret;
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Re: [PATCH v4 1/1] drm/syncobj: add sideband payload
Am 09.08.19 um 14:26 schrieb Lionel Landwerlin:
> On 09/08/2019 14:44, Chris Wilson wrote:
>> Quoting Lionel Landwerlin (2019-08-09 12:30:30)
>>> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
>>> index 8a5b2f8f8eb9..1ce83853f997 100644
>>> --- a/include/uapi/drm/drm.h
>>> +++ b/include/uapi/drm/drm.h
>>> @@ -785,6 +785,22 @@ struct drm_syncobj_timeline_array {
>>> __u32 pad;
>>> };
>>> +struct drm_syncobj_binary_array {
>>> + /* A pointer to an array of u32 syncobj handles. */
>>> + __u64 handles;
>>> + /* A pointer to an array of u32 access flags for each
>>> handle. */
>>> + __u64 access_flags;
>>> + /* The binary value of a syncobj is read before it is
>>> incremented. */
>>> +#define I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_READ (1u << 0)
>>> +#define I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_INC (1u << 1)
>> You're not in Kansas anymore ;)
>> -Chris
>>
> Which means? :)
You are in common DRM code, but the new defines start with I915_
Cheers,
Christian.
>
>
> -Lionel
>
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Re: [PATCH v3 8/8] drm/etnaviv: implement per-process address spaces on MMUv2
On Fri, 2019-08-09 at 14:04 +0200, Lucas Stach wrote: > This builds on top of the MMU contexts introduced earlier. Instead of having > one context per GPU core, each GPU client receives its own context. > > On MMUv1 this still means a single shared pagetable set is used by all > clients, but on MMUv2 there is now a distinct set of pagetables for each > client. As the command fetch is also translated via the MMU on MMUv2 the > kernel command ringbuffer is mapped into each of the client pagetables. > > As the MMU context switch is a bit of a heavy operation, due to the needed > cache and TLB flushing, this patch implements a lazy way of switching the > MMU context. The kernel does not have its own MMU context, but reuses the > last client context for all of its operations. This has some visible impact, > as the GPU can now only be started once a client has submitted some work and > we got the client MMU context assigned. Also the MMU context has a different > lifetime than the general client context, as the GPU might still execute the > kernel command buffer in the context of a client even after the client has > completed all GPU work and has been terminated. Only when the GPU is runtime > suspended or switches to another clients MMU context is the old context > freed up. > > Signed-off-by: Lucas Stach Reviewed-by: Philipp Zabel regards Philipp ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 1/1] drm/syncobj: add sideband payload
On 09/08/2019 14:44, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-08-09 12:30:30)
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 8a5b2f8f8eb9..1ce83853f997 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -785,6 +785,22 @@ struct drm_syncobj_timeline_array {
__u32 pad;
};
+struct drm_syncobj_binary_array {
+ /* A pointer to an array of u32 syncobj handles. */
+ __u64 handles;
+ /* A pointer to an array of u32 access flags for each handle. */
+ __u64 access_flags;
+ /* The binary value of a syncobj is read before it is incremented. */
+#define I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_READ (1u << 0)
+#define I915_DRM_SYNCOBJ_BINARY_ITEM_VALUE_INC (1u << 1)
You're not in Kansas anymore ;)
-Chris
Which means? :)
-Lionel
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Re: [PATCH v3 4/8] drm/etnaviv: replace MMU flush marker with flush sequence
On Fri, 2019-08-09 at 14:04 +0200, Lucas Stach wrote: > If a MMU is shared between multiple GPUs, all of them need to flush their > TLBs, so a single marker that gets reset on the first flush won't do. > Replace the flush marker with a sequence number, so that it's possible to > check if the TLB is in sync with the current page table state for each GPU. > > Signed-off-by: Lucas Stach Reviewed-by: Philipp Zabel regards Philipp ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] etnaviv: fix whitespace errors
Am Freitag, den 02.08.2019, 13:26 +0200 schrieb Christian Gmeiner:
> Changes in V2:
> - use indentation as suggested by Philipp Zabel.
>
> Signed-off-by: Christian Gmeiner
Thanks, applied.
Regards,
Lucas
> ---
> drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> index 4227a4006c34..ef24a08a58b0 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> @@ -15,8 +15,8 @@ struct etnaviv_pm_signal {
> u32 data;
>
> u32 (*sample)(struct etnaviv_gpu *gpu,
> - const struct etnaviv_pm_domain *domain,
> - const struct etnaviv_pm_signal *signal);
> + const struct etnaviv_pm_domain *domain,
> + const struct etnaviv_pm_signal *signal);
> };
>
> struct etnaviv_pm_domain {
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Re: [PATCH] etnaviv: perfmon: fix total and idle HI cyleces readout
Am Mittwoch, den 31.07.2019, 23:30 +0200 schrieb Christian Gmeiner:
> As seen at CodeAurora's linux-imx git repo in imx_4.19.35_1.0.0
> branch.
>
> Signed-off-by: Christian Gmeiner
Thanks, applied.
Regards,
Lucas
> ---
> drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 44 +--
>
> 1 file changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> index 06e6d3ee1c34..3c74b1273ea9 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> @@ -4,6 +4,7 @@
> * Copyright (C) 2017 Zodiac Inflight Innovations
> */
>
> +#include "common.xml.h"
> #include "etnaviv_gpu.h"
> #include "etnaviv_perfmon.h"
> #include "state_hi.xml.h"
> @@ -35,13 +36,6 @@ struct etnaviv_pm_domain_meta {
> u32 nr_domains;
> };
>
> -static u32 simple_reg_read(struct etnaviv_gpu *gpu,
> - const struct etnaviv_pm_domain *domain,
> - const struct etnaviv_pm_signal *signal)
> -{
> - return gpu_read(gpu, signal->data);
> -}
> -
> static u32 perf_reg_read(struct etnaviv_gpu *gpu,
> const struct etnaviv_pm_domain *domain,
> const struct etnaviv_pm_signal *signal)
> @@ -75,6 +69,34 @@ static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
> return value;
> }
>
> +static u32 hi_total_cycle_read(struct etnaviv_gpu *gpu,
> + const struct etnaviv_pm_domain *domain,
> + const struct etnaviv_pm_signal *signal)
> +{
> + u32 reg = VIVS_HI_PROFILE_TOTAL_CYCLES;
> +
> + if (gpu->identity.model == chipModel_GC880 ||
> + gpu->identity.model == chipModel_GC2000 ||
> + gpu->identity.model == chipModel_GC2100)
> + reg = VIVS_MC_PROFILE_CYCLE_COUNTER;
> +
> + return gpu_read(gpu, reg);
> +}
> +
> +static u32 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu,
> + const struct etnaviv_pm_domain *domain,
> + const struct etnaviv_pm_signal *signal)
> +{
> + u32 reg = VIVS_HI_PROFILE_IDLE_CYCLES;
> +
> + if (gpu->identity.model == chipModel_GC880 ||
> + gpu->identity.model == chipModel_GC2000 ||
> + gpu->identity.model == chipModel_GC2100)
> + reg = VIVS_HI_PROFILE_TOTAL_CYCLES;
> +
> + return gpu_read(gpu, reg);
> +}
> +
> static const struct etnaviv_pm_domain doms_3d[] = {
> {
> .name = "HI",
> @@ -84,13 +106,13 @@ static const struct etnaviv_pm_domain doms_3d[]
> = {
> .signal = (const struct etnaviv_pm_signal[]) {
> {
> "TOTAL_CYCLES",
> - VIVS_HI_PROFILE_TOTAL_CYCLES,
> - _reg_read
> + 0,
> + _total_cycle_read
> },
> {
> "IDLE_CYCLES",
> - VIVS_HI_PROFILE_IDLE_CYCLES,
> - _reg_read
> + 0,
> + _total_idle_cycle_read
> },
> {
> "AXI_CYCLES_READ_REQUEST_STALLED",
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