Re: [PATCH v2] dt-bindings: display: Convert connectors to DT schema
Hi Rob,
Thank you for the patch.
On Tue, Jun 30, 2020 at 02:02:16PM -0600, Rob Herring wrote:
> Convert the analog TV, DVI, HDMI, and VGA connector bindings to DT schema
> format.
>
> Cc: Sam Ravnborg
> Cc: Laurent Pinchart
> Cc: Maxime Ripard
> Signed-off-by: Rob Herring
Reviewed-by: Laurent Pinchart
> ---
> v2:
> - Make Laurent maintainer
> - Add missing port and compatible required
> - Drop copy-n-paste 'type' from dvi-connector
> - Use 4 space indent on examples
> ---
> .../display/connector/analog-tv-connector.txt | 31
> .../connector/analog-tv-connector.yaml| 52 ++
> .../display/connector/dvi-connector.txt | 36 --
> .../display/connector/dvi-connector.yaml | 70 +++
> .../display/connector/hdmi-connector.txt | 31
> .../display/connector/hdmi-connector.yaml | 64 +
> .../display/connector/vga-connector.txt | 36 --
> .../display/connector/vga-connector.yaml | 46
> 8 files changed, 232 insertions(+), 134 deletions(-)
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/dvi-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/dvi-connector.yaml
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/vga-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/vga-connector.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> deleted file mode 100644
> index 883bcb2604c7..
> ---
> a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -Analog TV Connector
> -===
> -
> -Required properties:
> -- compatible: "composite-video-connector" or "svideo-connector"
> -
> -Optional properties:
> -- label: a symbolic name for the connector
> -- sdtv-standards: limit the supported TV standards on a connector to the
> given
> - ones. If not specified all TV standards are allowed.
> - Possible TV standards are defined in
> - include/dt-bindings/display/sdtv-standards.h.
> -
> -Required nodes:
> -- Video port for TV input
> -
> -Example
>
> -#include
> -
> -tv: connector {
> - compatible = "composite-video-connector";
> - label = "tv";
> - sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
> -
> - port {
> - tv_connector_in: endpoint {
> - remote-endpoint = <_out>;
> - };
> - };
> -};
> diff --git
> a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
>
> b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
> new file mode 100644
> index ..eebe88fed999
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id:
> http://devicetree.org/schemas/display/connector/analog-tv-connector.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog TV Connector
> +
> +maintainers:
> + - Laurent Pinchart
> +
> +properties:
> + compatible:
> +enum:
> + - composite-video-connector
> + - svideo-connector
> +
> + label: true
> +
> + sdtv-standards:
> +description:
> + Limit the supported TV standards on a connector to the given ones. If
> + not specified all TV standards are allowed. Possible TV standards are
> + defined in include/dt-bindings/display/sdtv-standards.h.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +
> + port:
> +description: Connection to controller providing analog TV signals
> +
> +required:
> + - compatible
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +
> +connector {
> +compatible = "composite-video-connector";
> +label = "tv";
> +sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
> +
> +port {
> +tv_connector_in: endpoint {
> +remote-endpoint = <_out>;
> +};
> +};
> +};
> +
> +...
> diff --git
> a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
> b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
> deleted file mode 100644
> index 207e42e9eba0..
> ---
Re: [PATCH v1 0/7] drm_connector: drop legacy drm_bus_flags
Hi Sam, Thank you for the patches. On Tue, Jun 30, 2020 at 08:05:38PM +0200, Sam Ravnborg wrote: > Drop all uses of legacy drm_bus_flags, and then drop the flags. > Follow-up with a patch to inline the documentation of the flags. > > The conversion was triggered by Laurent's clean-up of > the bus_flags use in panel-simple. > https://lore.kernel.org/dri-devel/20200630135802.ga581...@ravnborg.org/T/#t > > Build tested only. > Patches on top of latest drm-misc-next. For the whole series, Reviewed-by: Laurent Pinchart > (Procrastination, was supposed to review patches, not producing them). > > Sam Ravnborg (7): > drm/tidss: drop use of legacy drm_bus_flags > drm/ingenic-drm: drop use of legacy drm_bus_flags > drm/panel: raydium-rm67191: drop use of legacy drm_bus_flags > drm/panel: novatek-nt39016: drop use of legacy drm_bus_flags > drm/panel: panel-simple: drop use of legacy drm_bus_flags > drm/drm_connector: drop legacy drm_bus_flags values > drm/drm_connector: use inline comments for drm_bus_flags > > drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +- > drivers/gpu/drm/panel/panel-novatek-nt39016.c | 2 +- > drivers/gpu/drm/panel/panel-raydium-rm67191.c | 2 +- > drivers/gpu/drm/panel/panel-simple.c | 28 +++--- > drivers/gpu/drm/tidss/tidss_dispc.c | 4 +- > include/drm/drm_connector.h | 124 > ++ > 6 files changed, 104 insertions(+), 58 deletions(-) -- Regards, Laurent Pinchart ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v9 1/2] of_graph: add of_graph_is_present()
Hi Dmitry,
Thank you for the patch.
On Wed, Jul 01, 2020 at 05:16:16AM +0300, Dmitry Osipenko wrote:
> In some case, like a DRM display code for example, it's useful to silently
> check whether port node exists at all in a device-tree before proceeding
> with parsing of the graph.
>
> This patch adds of_graph_is_present() which returns true if given
> device-tree node contains OF graph port.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/of/property.c| 52 +---
> include/linux/of_graph.h | 6 +
> 2 files changed, 49 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/of/property.c b/drivers/of/property.c
> index 6a5760f0d6cd..e12b8b491837 100644
> --- a/drivers/of/property.c
> +++ b/drivers/of/property.c
> @@ -29,6 +29,48 @@
>
> #include "of_private.h"
>
> +/**
> + * of_graph_get_first_local_port() - get first local port node
> + * @node: pointer to a local endpoint device_node
It's not an endpoint.
> + *
> + * Return: First local port node associated with local endpoint node linked
> + * to @node. Use of_node_put() on it when done.
> + */
> +static struct device_node *
> +of_graph_get_first_local_port(const struct device_node *node)
> +{
> + struct device_node *ports, *port;
> +
> + ports = of_get_child_by_name(node, "ports");
> + if (ports)
> + node = ports;
> +
> + port = of_get_child_by_name(node, "port");
> + of_node_put(ports);
> +
> + return port;
> +}
> +
> +/**
> + * of_graph_is_present() - check graph's presence
> + * @node: pointer to a device_node checked for the graph's presence
> + *
> + * Return: True if @node has a port or ports sub-node, false otherwise.
> + */
> +bool of_graph_is_present(const struct device_node *node)
> +{
> + struct device_node *local;
> +
> + local = of_graph_get_first_local_port(node);
> + if (!local)
> + return false;
> +
> + of_node_put(local);
> +
> + return true;
> +}
> +EXPORT_SYMBOL(of_graph_is_present);
> +
> /**
> * of_property_count_elems_of_size - Count the number of elements in a
> property
> *
> @@ -608,15 +650,7 @@ struct device_node *of_graph_get_next_endpoint(const
> struct device_node *parent,
>* parent port node.
>*/
> if (!prev) {
> - struct device_node *node;
> -
> - node = of_get_child_by_name(parent, "ports");
> - if (node)
> - parent = node;
> -
> - port = of_get_child_by_name(parent, "port");
> - of_node_put(node);
> -
> + port = of_graph_get_first_local_port(parent);
I think this introduces a bug below in the function, where parent is
used and is expected to point to the ports node if available. I'd leave
this part of the change out, and inline +of_graph_get_first_local_port()
in of_graph_is_present().
> if (!port) {
> pr_err("graph: no port node found in %pOF\n", parent);
> return NULL;
> diff --git a/include/linux/of_graph.h b/include/linux/of_graph.h
> index 01038a6aade0..4d7756087b6b 100644
> --- a/include/linux/of_graph.h
> +++ b/include/linux/of_graph.h
> @@ -38,6 +38,7 @@ struct of_endpoint {
>child = of_graph_get_next_endpoint(parent, child))
>
> #ifdef CONFIG_OF
> +bool of_graph_is_present(const struct device_node *node);
> int of_graph_parse_endpoint(const struct device_node *node,
> struct of_endpoint *endpoint);
> int of_graph_get_endpoint_count(const struct device_node *np);
> @@ -56,6 +57,11 @@ struct device_node *of_graph_get_remote_node(const struct
> device_node *node,
>u32 port, u32 endpoint);
> #else
>
> +static inline bool of_graph_is_present(const struct device_node *node)
> +{
> + return false;
> +}
> +
> static inline int of_graph_parse_endpoint(const struct device_node *node,
> struct of_endpoint *endpoint)
> {
--
Regards,
Laurent Pinchart
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Re: [git pull] drm for 5.8-rc1
This implies something is trying to use one of the old DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK format modifiers with DRM-KMS without first checking whether it is supported by the kernel. I had tried to force an Xorg+Mesa stack without my userspace patches to hit this error when testing, but must have missed some permutation. If the stalled Mesa patches go in, this would stop happening of course, but those were held up for a long time in review, and are now waiting on me to make some modifications. Are you using the modesetting driver in X? If so, with glamor I presume? What version of Mesa? Any distro patches? Any non-default xorg.conf options that would affect modesetting, your X driver if it isn't modesetting, or glamour? Thanks, -James On 6/30/20 4:08 PM, Kirill A. Shutemov wrote: On Tue, Jun 02, 2020 at 04:06:32PM +1000, Dave Airlie wrote: James Jones (4): ... drm/nouveau/kms: Support NVIDIA format modifiers This commit is the first one that breaks Xorg startup for my setup: GTX 1080 + Dell UP2414Q (4K DP MST monitor). I believe this is the crucial part of dmesg (full dmesg is attached): [ 29.997140] [drm:nouveau_framebuffer_new] Unsupported modifier: 0x314 [ 29.997143] [drm:drm_internal_framebuffer_create] could not create framebuffer [ 29.997145] [drm:drm_ioctl] pid=3393, ret = -22 Any suggestions? ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [pull] amdgpu, amdkfd, radeon drm-next-5.9
commit 5fa689e66bf406ef3a1afe03d0139d90b0b13773 Author: Likun Gao Commit: Alex Deucher drm/amdgpu/powerplay: add smu block for sienna_cichlid Add SMU block for sienna_cichlid with psp load type. Signed-off-by: Likun Gao Reviewed-by: Jack Xiao Spot the missing signed-off-by. (hint dim warns about these generating pull requests :-) Dave. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: fix double free for gbo in drm_gem_vram_init and drm_gem_vram_create
Ping...
On 2020/6/20 14:21, Jia Yang wrote:
> I got a use-after-free report when doing some fuzz test:
>
> If ttm_bo_init() fails, the "gbo" and "gbo->bo.base" will be
> freed by ttm_buffer_object_destroy() in ttm_bo_init(). But
> then drm_gem_vram_create() and drm_gem_vram_init() will free
> "gbo" and "gbo->bo.base" again.
>
> BUG: KMSAN: use-after-free in drm_vma_offset_remove+0xb3/0x150
> CPU: 0 PID: 24282 Comm: syz-executor.1 Tainted: GB W
> 5.7.0-rc4-msan #2
> Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
> Ubuntu-1.8.2-1ubuntu1 04/01/2014
> Call Trace:
> __dump_stack
> dump_stack+0x1c9/0x220
> kmsan_report+0xf7/0x1e0
> __msan_warning+0x58/0xa0
> drm_vma_offset_remove+0xb3/0x150
> drm_gem_free_mmap_offset
> drm_gem_object_release+0x159/0x180
> drm_gem_vram_init
> drm_gem_vram_create+0x7c5/0x990
> drm_gem_vram_fill_create_dumb
> drm_gem_vram_driver_dumb_create+0x238/0x590
> drm_mode_create_dumb
> drm_mode_create_dumb_ioctl+0x41d/0x450
> drm_ioctl_kernel+0x5a4/0x710
> drm_ioctl+0xc6f/0x1240
> vfs_ioctl
> ksys_ioctl
> __do_sys_ioctl
> __se_sys_ioctl+0x2e9/0x410
> __x64_sys_ioctl+0x4a/0x70
> do_syscall_64+0xb8/0x160
> entry_SYSCALL_64_after_hwframe+0x44/0xa9
> RIP: 0033:0x4689b9
> Code: fd e0 fa ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 48 89 f8 48 89 f7 48
> 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 0f
> 83 cb e0 fa ff c3 66 2e 0f 1f 84 00 00 00 00
> RSP: 002b:7f368fa4dc98 EFLAGS: 0246 ORIG_RAX: 0010
> RAX: ffda RBX: 0076bf00 RCX: 004689b9
> RDX: 2240 RSI: c02064b2 RDI: 0003
> RBP: 0004 R08: R09:
> R10: R11: 0246 R12:
> R13: 004d17e0 R14: 7f368fa4e6d4 R15: 0076bf0c
>
> Uninit was created at:
> kmsan_save_stack_with_flags
> kmsan_internal_poison_shadow+0x66/0xd0
> kmsan_slab_free+0x6e/0xb0
> slab_free_freelist_hook
> slab_free
> kfree+0x571/0x30a0
> drm_gem_vram_destroy
> ttm_buffer_object_destroy+0xc8/0x130
> ttm_bo_release
> kref_put
> ttm_bo_put+0x117d/0x23e0
> ttm_bo_init_reserved+0x11c0/0x11d0
> ttm_bo_init+0x289/0x3f0
> drm_gem_vram_init
> drm_gem_vram_create+0x775/0x990
> drm_gem_vram_fill_create_dumb
> drm_gem_vram_driver_dumb_create+0x238/0x590
> drm_mode_create_dumb
> drm_mode_create_dumb_ioctl+0x41d/0x450
> drm_ioctl_kernel+0x5a4/0x710
> drm_ioctl+0xc6f/0x1240
> vfs_ioctl
> ksys_ioctl
> __do_sys_ioctl
> __se_sys_ioctl+0x2e9/0x410
> __x64_sys_ioctl+0x4a/0x70
> do_syscall_64+0xb8/0x160
> entry_SYSCALL_64_after_hwframe+0x44/0xa9
>
> If ttm_bo_init() fails, the "gbo" will be freed by
> ttm_buffer_object_destroy() in ttm_bo_init(). But then
> drm_gem_vram_create() and drm_gem_vram_init() will free
> "gbo" again.
>
> Reported-by: Hulk Robot
> Signed-off-by: Jia Yang
> ---
> drivers/gpu/drm/drm_gem_vram_helper.c | 28 +++
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
> b/drivers/gpu/drm/drm_gem_vram_helper.c
> index 8b2d5c945c95..1d85af9a481a 100644
> --- a/drivers/gpu/drm/drm_gem_vram_helper.c
> +++ b/drivers/gpu/drm/drm_gem_vram_helper.c
> @@ -175,6 +175,10 @@ static void drm_gem_vram_placement(struct
> drm_gem_vram_object *gbo,
> }
> }
>
> +/*
> + * Note that on error, drm_gem_vram_init will free the buffer object.
> + */
> +
> static int drm_gem_vram_init(struct drm_device *dev,
>struct drm_gem_vram_object *gbo,
>size_t size, unsigned long pg_align)
> @@ -184,15 +188,19 @@ static int drm_gem_vram_init(struct drm_device *dev,
> int ret;
> size_t acc_size;
>
> - if (WARN_ONCE(!vmm, "VRAM MM not initialized"))
> + if (WARN_ONCE(!vmm, "VRAM MM not initialized")) {
> + kfree(gbo);
> return -EINVAL;
> + }
> bdev = >bdev;
>
> gbo->bo.base.funcs = _gem_vram_object_funcs;
>
> ret = drm_gem_object_init(dev, >bo.base, size);
> - if (ret)
> + if (ret) {
> + kfree(gbo);
> return ret;
> + }
>
> acc_size = ttm_bo_dma_acc_size(bdev, size, sizeof(*gbo));
>
> @@ -203,13 +211,13 @@ static int drm_gem_vram_init(struct drm_device *dev,
> >placement, pg_align, false, acc_size,
> NULL, NULL, ttm_buffer_object_destroy);
> if (ret)
> - goto err_drm_gem_object_release;
> + /*
> + * A failing ttm_bo_init will call ttm_buffer_object_destroy
> + * to release gbo->bo.base and kfree gbo.
> + */
> + return ret;
>
> return 0;
> -
> -err_drm_gem_object_release:
> - drm_gem_object_release(>bo.base);
> - return ret;
> }
>
> /**
> @@ -243,13 +251,9 @@ struct drm_gem_vram_object *drm_gem_vram_create(struct
Re: [PATCH 3/3] drm/edid: Clean up some curly braces
On Wed, 2020-05-27 at 16:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Drop some pointless curly braces, and add some across the
> else when the if has them too.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index dcb23563d29d..8a951e2bfb41 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5836,22 +5836,21 @@ static void drm_parse_tiled_block(struct
> drm_connector *connector,
> DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0],
> tile->topology_id[1], tile->topology_id[2]);
>
> tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
> - if (!tg) {
> + if (!tg)
> tg = drm_mode_create_tile_group(connector->dev,
> tile->topology_id);
> - }
> if (!tg)
> return;
>
> if (connector->tile_group != tg) {
> /* if we haven't got a pointer,
> take the reference, drop ref to old tile group */
> - if (connector->tile_group) {
> + if (connector->tile_group)
> drm_mode_put_tile_group(connector->dev,
> connector->tile_group);
> - }
> connector->tile_group = tg;
> - } else
> + } else {
> /* if same tile group, then release the ref we just took. */
> drm_mode_put_tile_group(connector->dev, tg);
> + }
> }
>
> static void drm_displayid_parse_tiled(struct drm_connector *connector,
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Re: [Intel-gfx] [PATCH 2/3] drm/edid: Iterate through all DispID ext blocks
On Wed, 2020-05-27 at 16:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apparently there are EDIDs in the wild with multiple DispID extension
> blocks. Iterate through them all.
>
> In one particular case the tile information is specicied in the
> second DispID ext block, and since the current parser only looks
> at the first DispID ext block we don't notice that we're dealing
> with a tiled display.
>
> While at it change a few functions to return void since we have
> no use for the errno.
With the change in the previous patch:
Reviewed-by: José Roberto de Souza
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/27
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 84 +-
> 1 file changed, 38 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index f2531d51dfa2..dcb23563d29d 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3248,6 +3248,7 @@ static u8 *drm_find_cea_extension(const struct edid
> *edid)
> int ext_index;
>
> /* Look for a top level CEA extension block */
> + /* FIXME: make callers iterate through multiple CEA ext blocks? */
> ext_index = 0;
> cea = drm_find_edid_extension(edid, CEA_EXT, _index);
> if (cea)
> @@ -3255,20 +3256,20 @@ static u8 *drm_find_cea_extension(const struct edid
> *edid)
>
> /* CEA blocks can also be found embedded in a DisplayID block */
> ext_index = 0;
> - displayid = drm_find_displayid_extension(edid, , ,
> - _index);
> - if (!displayid)
> - return NULL;
> + for (;;) {
> + displayid = drm_find_displayid_extension(edid, , ,
> + _index);
> + if (!displayid)
> + return NULL;
>
> - idx += sizeof(struct displayid_hdr);
> - for_each_displayid_db(displayid, block, idx, length) {
> - if (block->tag == DATA_BLOCK_CTA) {
> - cea = (u8 *)block;
> - break;
> + idx += sizeof(struct displayid_hdr);
> + for_each_displayid_db(displayid, block, idx, length) {
> + if (block->tag == DATA_BLOCK_CTA)
> + return (u8 *)block;
> }
> }
>
> - return cea;
> + return NULL;
> }
>
> static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8
> vic)
> @@ -5205,19 +5206,22 @@ static int add_displayid_detailed_modes(struct
> drm_connector *connector,
> int num_modes = 0;
> int ext_index = 0;
>
> - displayid = drm_find_displayid_extension(edid, , ,
> - _index);
> - if (!displayid)
> - return 0;
> -
> - idx += sizeof(struct displayid_hdr);
> - for_each_displayid_db(displayid, block, idx, length) {
> - switch (block->tag) {
> - case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
> - num_modes += add_displayid_detailed_1_modes(connector,
> block);
> + for (;;) {
> + displayid = drm_find_displayid_extension(edid, , ,
> + _index);
> + if (!displayid)
> break;
> +
> + idx += sizeof(struct displayid_hdr);
> + for_each_displayid_db(displayid, block, idx, length) {
> + switch (block->tag) {
> + case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
> + num_modes +=
> add_displayid_detailed_1_modes(connector, block);
> + break;
> + }
> }
> }
> +
> return num_modes;
> }
>
> @@ -5797,8 +5801,8 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
> hdmi_vendor_infoframe *frame,
> }
> EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
>
> -static int drm_parse_tiled_block(struct drm_connector *connector,
> - const struct displayid_block *block)
> +static void drm_parse_tiled_block(struct drm_connector *connector,
> + const struct displayid_block *block)
> {
> const struct displayid_tiled_block *tile = (struct
> displayid_tiled_block *)block;
> u16 w, h;
> @@ -5836,7 +5840,7 @@ static int drm_parse_tiled_block(struct drm_connector
> *connector,
> tg = drm_mode_create_tile_group(connector->dev,
> tile->topology_id);
> }
> if (!tg)
> - return -ENOMEM;
> + return;
>
> if (connector->tile_group != tg) {
> /* if we haven't got a pointer,
> @@ -5848,14 +5852,12 @@ static int drm_parse_tiled_block(struct drm_connector
> *connector,
> } else
> /* if same tile group, then release the ref we just took. */
Re: [Intel-gfx] [PATCH 1/3] drm/edid: Allow looking for ext blocks starting from a specified index
On Wed, 2020-05-27 at 16:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apparently EDIDs with multiple DispID ext blocks is a thing, so prepare
> for iterating through multiple ext blocks of the same type by
> passing the starting ext block index to drm_find_edid_extension(). Well
> also have drm_find_edid_extension() update the index to point to the
> next ext block on success. Thus we should be able to call
> drm_find_edid_extension() in loop.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 30 +-
> 1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index d8372d63851b..f2531d51dfa2 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3188,7 +3188,8 @@ add_detailed_modes(struct drm_connector *connector,
> struct edid *edid,
> /*
> * Search EDID for CEA extension block.
> */
> -static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
> +static u8 *drm_find_edid_extension(const struct edid *edid,
> +int ext_id, int *ext_index)
> {
> u8 *edid_ext = NULL;
> int i;
> @@ -3198,23 +3199,26 @@ static u8 *drm_find_edid_extension(const struct edid
> *edid, int ext_id)
> return NULL;
>
> /* Find CEA extension */
> - for (i = 0; i < edid->extensions; i++) {
> + for (i = *ext_index; i < edid->extensions; i++) {
> edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
> if (edid_ext[0] == ext_id)
> break;
> }
>
> - if (i == edid->extensions)
> + if (i >= edid->extensions)
> return NULL;
>
> + *ext_index = i + 1;
> +
> return edid_ext;
> }
>
I would add something like drm_find_edid_n_extension() with the implementation
above and then implement drm_find_edid_extension() calling
drm_find_edid_n_extension() but it is just one caller that is not using
ext_index so LGTM.
>
> static u8 *drm_find_displayid_extension(const struct edid *edid,
> - int *length, int *idx)
> + int *length, int *idx,
> + int *ext_index)
> {
> - u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT);
> + u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index);
> struct displayid_hdr *base;
> int ret;
>
> @@ -3241,14 +3245,18 @@ static u8 *drm_find_cea_extension(const struct edid
> *edid)
> struct displayid_block *block;
> u8 *cea;
> u8 *displayid;
> + int ext_index;
>
> /* Look for a top level CEA extension block */
> - cea = drm_find_edid_extension(edid, CEA_EXT);
> + ext_index = 0;
In 2 places ext_index is initialized in the variable declaration and in 2 other
places is not, all of it could be done in the declaration or if you
really want to leave the context close to the users, initialize it in the "for
(;;)" in the next patch.
With the change above:
Reviewed-by: José Roberto de Souza
> + cea = drm_find_edid_extension(edid, CEA_EXT, _index);
> if (cea)
> return cea;
>
> /* CEA blocks can also be found embedded in a DisplayID block */
> - displayid = drm_find_displayid_extension(edid, , );
> + ext_index = 0;
> + displayid = drm_find_displayid_extension(edid, , ,
> + _index);
> if (!displayid)
> return NULL;
>
> @@ -5195,8 +5203,10 @@ static int add_displayid_detailed_modes(struct
> drm_connector *connector,
> int length, idx;
> struct displayid_block *block;
> int num_modes = 0;
> + int ext_index = 0;
>
> - displayid = drm_find_displayid_extension(edid, , );
> + displayid = drm_find_displayid_extension(edid, , ,
> + _index);
> if (!displayid)
> return 0;
>
> @@ -5870,11 +5880,13 @@ void drm_update_tile_info(struct drm_connector
> *connector,
> const struct edid *edid)
> {
> const void *displayid = NULL;
> + int ext_index = 0;
> int length, idx;
> int ret;
>
> connector->has_tile = false;
> - displayid = drm_find_displayid_extension(edid, , );
> + displayid = drm_find_displayid_extension(edid, , ,
> + _index);
> if (!displayid) {
> /* drop reference to any tile group we had */
> goto out_drop_ref;
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Re: [RESEND PATCH v4 0/7] Convert mtk-dsi to drm_bridge API and get EDID for ps8640 bridge
Hi, Enric: Enric Balletbo i Serra 於 2020年7月1日 週三 上午5:02寫道： > > Hi Chun-Kuang, > > On 30/6/20 18:26, Chun-Kuang Hu wrote: > > Hi, Enric: > > > > Enric Balletbo i Serra 於 2020年6月30日 週二 > > 下午10:34寫道： > >> > >> Hi Sam, Chun-Kuan, > >> > >> On 20/6/20 23:33, Sam Ravnborg wrote: > >>> Hi Enric > >>> > >>> On Mon, Jun 15, 2020 at 10:31:01PM +0200, Enric Balletbo i Serra wrote: > (This resend is to fix some trivial conflicts due the merge window) > > The PS8640 dsi-to-eDP bridge driver is using the panel bridge API, > however, not all the components in the chain have been ported to the > drm_bridge API. Actually, when a panel is attached the default panel's > mode > is used, but in some cases we can't get display up if mode getting from > eDP control EDID is not chosen. > > This series address that problem, first implements the .get_edid() > callback in the PS8640 driver (which is not used until the conversion is > done) and then, converts the Mediatek DSI driver to use the drm_bridge > API. > > As far as I know, we're the only users of the mediatek dsi driver in > mainline, so should be safe to switch to the new chain of drm_bridge API > unconditionally. > > The patches has been tested on a Acer Chromebook R13 (Elm) running a > Chrome OS userspace and checking that the valid EDID mode reported by > the bridge is selected. > > Changes in v4: > - Remove double call to drm_encoder_init(). (Chun-Kuang Hu) > - Cleanup the encoder in mtk_dsi_unbind(). (Chun-Kuang Hu) > > Changes in v3: > - Replace s/bridge/next bridge/ for comment. (Laurent Pinchart) > - Add the bridge.type. (Laurent Pinchart) > - Use next_bridge field to store the panel bridge. (Laurent Pinchart) > - Add the bridge.type field. (Laurent Pinchart) > - This patch requires https://lkml.org/lkml/2020/4/16/2080 to work > properly. > - Move the bridge.type line to the patch that adds drm_bridge support. > (Laurent Pinchart) > > Changes in v2: > - Do not set connector_type for panel here. (Sam Ravnborg) > > Enric Balletbo i Serra (7): > drm/bridge: ps8640: Get the EDID from eDP control > drm/bridge_connector: Set default status connected for eDP connectors > drm/mediatek: mtk_dsi: Rename bridge to next_bridge > drm/mediatek: mtk_dsi: Convert to bridge driver > drm/mediatek: mtk_dsi: Use simple encoder > drm/mediatek: mtk_dsi: Use the drm_panel_bridge API > drm/mediatek: mtk_dsi: Create connector for bridges > >>> > >>> Patch seems ready to apply. Will they be applied to a mediatek tree > >>> or to drm-misc-next? > >>> Or shall we take the first two patches via drm-misc-next, and the > >>> remaning via a mediatek tree? (I hope not) > >>> > >> > >> I think the only concern is from Chun-Kuan regarding patch 7/7 > >> "drm/mediatek: > >> mtk_dsi: Create connector for bridges" whether we should support the old > >> API or > >> not, but the discussion stalled. > >> > > > > I get more clear now. In patch 7/7, > > > > ret = drm_bridge_attach(>encoder, >bridge, NULL, > > DRM_BRIDGE_ATTACH_NO_CONNECTOR); > > > > this would call into mtk_dsi_bridge_attach() first, and then call into > > panel_bridge_attach() next. So panel_bridge_attach() would receive > > DRM_BRIDGE_ATTACH_NO_CONNECTOR and it return immediately so it does > > not call drm_panel_attach(). So where do you call drm_panel_attach()? > > > > Why I need to call drm_panel_attach? > > I believe drm_panel_attach() was to attach a panel to a connector, but we > don't > need to do this with the new API as the connector is already created and > attached to the "dummy" encoder. > > Makes that sense to you? What do you think will not work if I don't call > drm_panel_attach? > > [1] > https://elixir.bootlin.com/linux/v5.8-rc3/source/drivers/gpu/drm/drm_panel.c#L101 > Sorry, I do not notice this. So for patch 7/7, Reviewed-by: Chun-Kuang Hu and I would take this series into my tree later, thanks. Regards, Chun-Kuang. > Regards, > Enric > > > > Regards, > > Chun-Kuang. > > > >> Thanks, > >> Enric > >> > >> > >> > >>> Sam > >>> > >>> > > drivers/gpu/drm/bridge/parade-ps8640.c | 12 ++ > drivers/gpu/drm/drm_bridge_connector.c | 1 + > drivers/gpu/drm/mediatek/mtk_dsi.c | 269 - > 3 files changed, 97 insertions(+), 185 deletions(-) > > -- > 2.27.0 > > ___ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel > >>> > > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v1 1/7] drm/tidss: drop use of legacy drm_bus_flags
On 30/06/2020 21:05, Sam Ravnborg wrote: > Use the more descriptive _DRIVE_ variants thus avoiding the > legacy drm_bus_flags values. > > Signed-off-by: Sam Ravnborg > Cc: Laurent Pinchart > Cc: Jyri Sarha > Cc: Tomi Valkeinen Acked-by: Jyri Sarha > --- > drivers/gpu/drm/tidss/tidss_dispc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c > b/drivers/gpu/drm/tidss/tidss_dispc.c > index 629dd06393f6..772a497e8c57 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -997,12 +997,12 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 > hw_videoport, > > ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); > > - ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE); > + ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); > > /* always use the 'rf' setting */ > onoff = true; > > - rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_POSEDGE); > + rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); > > /* always use aligned syncs */ > align = true; > -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 56/59] kmb/drm: Prune unsupported modes
KMB display pipeline is LCD->Mipi->HDMI. Mipi->HDMI converter chip only
accepts 4-lane input from mipi.
With 4-lane mipi, KMB hardware can only support 1080p resolution.
Therefore, limit supported mode to 1080p.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 4 ++--
drivers/gpu/drm/kmb/kmb_drv.h | 8 +---
drivers/gpu/drm/kmb/kmb_dsi.c | 11 +++
drivers/gpu/drm/kmb/kmb_plane.c | 2 ++
4 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index f8894d3..68e7b5c 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -359,8 +359,8 @@ static const struct drm_mode_config_funcs
kmb_mode_config_funcs = {
static void kmb_setup_mode_config(struct drm_device *drm)
{
drm_mode_config_init(drm);
- drm->mode_config.min_width = 0;
- drm->mode_config.min_height = 0;
+ drm->mode_config.min_width = KMB_MIN_WIDTH;
+ drm->mode_config.min_height = KMB_MIN_HEIGHT;
drm->mode_config.max_width = KMB_MAX_WIDTH;
drm->mode_config.max_height = KMB_MAX_HEIGHT;
drm->mode_config.funcs = _mode_config_funcs;
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 83824f7..eef2d8b 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -28,10 +28,12 @@
#include "kmb_regs.h"
-#define FCCTEST
+//#define FCCTEST
#define LCD_TEST
-#define KMB_MAX_WIDTH 1920/*max width in pixels */
-#define KMB_MAX_HEIGHT 1080/*max height in pixels */
+#define KMB_MAX_WIDTH 1920 /*max width in pixels */
+#define KMB_MAX_HEIGHT 1080 /*max height in pixels */
+#define KMB_MIN_WIDTH 1920 /*max width in pixels */
+#define KMB_MIN_HEIGHT 1080 /*max height in pixels */
#define KMB_LCD_DEFAULT_CLK25000
#define KMB_MIPI_DEFAULT_CLK 2400
#define KMB_MIPI_DEFAULT_CFG_CLK 2400
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 8a12d6d..ec974da 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -216,6 +216,17 @@ static enum drm_mode_status
kmb_dsi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct drm_device *dev = connector->dev;
+ struct drm_mode_config *mode_config = >mode_config;
+
+ if (mode->hdisplay < mode_config->min_width ||
+ mode->hdisplay > mode_config->max_width)
+ return MODE_BAD_HVALUE;
+
+ if (mode->vdisplay < mode_config->min_height ||
+ mode->vdisplay > mode_config->max_height)
+ return MODE_BAD_VVALUE;
+
return MODE_OK;
}
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 81250e1..5e040f7 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -77,6 +77,8 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT)
return -EINVAL;
+ if (state->crtc_w < KMB_MIN_WIDTH || state->crtc_h < KMB_MIN_HEIGHT)
+ return -EINVAL;
return 0;
}
--
2.7.4
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[PATCH 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable
Also moved num_planes init before load, time out for dsi
fixed kmb regs read/write to only pass dev_p and few other minor
changes.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 32 ++--
drivers/gpu/drm/kmb/kmb_drv.h | 34 +-
drivers/gpu/drm/kmb/kmb_dsi.c | 37 -
drivers/gpu/drm/kmb/kmb_plane.c | 27 +--
drivers/gpu/drm/kmb/kmb_regs.h | 1 +
5 files changed, 77 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 1aedcf8..1fc0b2e 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -78,11 +78,12 @@ static int kmb_display_clk_enable(void)
return ret;
}
- ret = clk_prepare_enable(clk_msscam);
+/* ret = clk_prepare_enable(clk_msscam);
if (ret) {
DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret);
return ret;
}
+ */
ret = clk_prepare_enable(clk_mipi_ecfg);
if (ret) {
@@ -136,6 +137,8 @@ static void __iomem *kmb_map_mmio(struct platform_device
*pdev, char *name)
release_mem_region(res->start, size);
return ERR_PTR(-ENOMEM);
}
+ DRM_INFO("%s : %d mapped %s mmio size = %d\n", __func__, __LINE__,
+ name, size);
return mem;
}
@@ -150,13 +153,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
int ret = 0;
unsigned long clk;
- /* Map LCD MMIO registers */
- dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs");
- if (IS_ERR(dev_p->lcd_mmio)) {
- DRM_ERROR("failed to map LCD registers\n");
- return -ENOMEM;
- }
-
/* Map MIPI MMIO registers */
dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs");
if (IS_ERR(dev_p->mipi_mmio)) {
@@ -165,6 +161,13 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
return -ENOMEM;
}
+ /* Map LCD MMIO registers */
+ dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs");
+ if (IS_ERR(dev_p->lcd_mmio)) {
+ DRM_ERROR("failed to map LCD registers\n");
+ return -ENOMEM;
+ }
+
/* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and MSS_CAM_CLK_CTRL
* register
*/
@@ -189,12 +192,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
goto setup_fail;
}
- clk_msscam = clk_get(>dev, "clk_msscam");
- if (IS_ERR(clk_msscam)) {
- DRM_ERROR("clk_get() failed clk_msscam\n");
- goto setup_fail;
- }
-
clk_mipi_ecfg = clk_get(>dev, "clk_mipi_ecfg");
if (IS_ERR(clk_mipi_ecfg)) {
DRM_ERROR("clk_get() failed clk_mipi_ecfg\n");
@@ -215,7 +212,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
if (clk_get_rate(clk_lcd) != KMB_LCD_DEFAULT_CLK) {
DRM_ERROR("failed to set to clk_lcd to %d\n",
KMB_LCD_DEFAULT_CLK);
- goto setup_fail;
}
DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n",
KMB_LCD_DEFAULT_CLK/100, ret);
@@ -265,8 +261,8 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
}
/* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */
- kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, LCD | MIPI_COMMON |
- MIPI_TX0);
+ kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0xfff);
+ kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xfff);
#ifdef WIP
/* Register irqs here - section 17.3 in databook
* lists LCD at 79 and 82 for MIPI under MSS CPU -
@@ -528,6 +524,7 @@ static int kmb_probe(struct platform_device *pdev)
dev_set_drvdata(dev, drm);
/* Load driver */
+ lcd->n_layers = KMB_MAX_PLANES;
ret = kmb_load(drm, 0);
if (ret == -EPROBE_DEFER) {
DRM_INFO("wait for external bridge driver DT\n");
@@ -550,7 +547,6 @@ static int kmb_probe(struct platform_device *pdev)
/* Register graphics device with the kernel */
ret = drm_dev_register(drm, 0);
- lcd->n_layers = KMB_MAX_PLANES;
if (ret)
goto err_register;
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 596f4fe..1511cd1 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -28,9 +28,9 @@
#include "kmb_regs.h"
-#define KMB_MAX_WIDTH 16384 /*max width in pixels */
-#define KMB_MAX_HEIGHT 16384 /*max height in pixels */
-#define KMB_LCD_DEFAULT_CLK2
+#define KMB_MAX_WIDTH 1920 /*max width in pixels */
+#define KMB_MAX_HEIGHT 1080 /*max
[PATCH 51/59] drm/kmb: Write to LCD_LAYERn_CFG only once
From: Edmund Dea
Video artifacts appear during playback as horizontal lines that
sporadically appear every few frames. Issue was caused by writing to
LCD_LAYERn_CFG register twice during plane updates. Issue is fixed by
writing to LCD_LAYERn_CFG only once.
Removed plane_init_status so that there are no initialization
dependencies during plane updates.
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 81 +++--
1 file changed, 38 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 8aa48b5..ebf29b2 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -118,7 +118,6 @@ static const u32 csc_coef_lcd[] = {
};
/*plane initialization status */
-static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 };
static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
{
@@ -321,7 +320,6 @@ static void config_csc(struct kmb_drm_private *dev_p, int
plane_id)
kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]);
kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]);
kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]);
- kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_CFG(plane_id), LCD_LAYER_CSC_EN);
}
#endif
@@ -410,19 +408,27 @@ static void kmb_plane_atomic_update(struct drm_plane
*plane,
addr[V_PLANE]);
}
}
- if (plane_init_status[plane_id] != INITIALIZED) {
- kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1);
- kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1);
- kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x);
- kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y);
-
- val = set_pixel_format(fb->format->format);
- val |= set_bits_per_pixel(fb->format);
- /*CHECKME Leon drvr sets it to 100 try this for now */
- val |= LCD_LAYER_FIFO_100;
- kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val);
-
- switch (plane_id) {
+
+ kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1);
+ kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1);
+ kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x);
+ kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y);
+
+ val = set_pixel_format(fb->format->format);
+ val |= set_bits_per_pixel(fb->format);
+ /*CHECKME Leon drvr sets it to 100 try this for now */
+ val |= LCD_LAYER_FIFO_100;
+
+ if (val & LCD_LAYER_PLANAR_STORAGE) {
+ val |= LCD_LAYER_CSC_EN;
+
+ /*enable CSC if input is planar and output is RGB */
+ config_csc(dev_p, plane_id);
+ }
+
+ kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val);
+
+ switch (plane_id) {
case LAYER_0:
ctrl = LCD_CTRL_VL1_ENABLE;
break;
@@ -435,36 +441,28 @@ static void kmb_plane_atomic_update(struct drm_plane
*plane,
case LAYER_3:
ctrl = LCD_CTRL_GL2_ENABLE;
break;
- }
+ }
- ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
- | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;
+ ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
+ | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;
- /*LCD is connected to MIPI on kmb
-* Therefore this bit is required for DSI Tx
-*/
- ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL;
+ /*LCD is connected to MIPI on kmb
+* Therefore this bit is required for DSI Tx
+*/
+ ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL;
- kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl);
+ kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl);
- /* FIXME no doc on how to set output format,these values are
-* taken from the Myriadx tests
-*/
- out_format |= LCD_OUTF_FORMAT_RGB888;
+ /* FIXME no doc on how to set output format,these values are
+* taken from the Myriadx tests
+*/
+ out_format |= LCD_OUTF_FORMAT_RGB888;
- if (val & LCD_LAYER_PLANAR_STORAGE) {
- /*enable CSC if input is planar and output is RGB */
- config_csc(dev_p, plane_id);
- }
-
- /*set background color to white */
- // kmb_write_lcd(dev_p, LCD_BG_COLOUR_LS, 0xff);
- /*leave RGB order,conversion mode and clip mode to default */
- /* do not interleave RGB channels for mipi Tx compatibility */
- out_format |=
[PATCH 55/59] drm/kmb: Added useful messages in LCD ISR
Print messages for LCD DMA FIFO errors.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 68 +++--
drivers/gpu/drm/kmb/kmb_plane.h | 2 ++
2 files changed, 60 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 79ab0bc..f8894d3 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -383,15 +383,15 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev)
* disabled but actually disable the plane when EOF irq is
* being handled.
*/
- for (plane_id = LAYER_0; plane_id < KMB_MAX_PLANES;
- plane_id++) {
+ for (plane_id = LAYER_0; plane_id < KMB_MAX_PLANES; plane_id++)
{
if (plane_status[plane_id].disable) {
kmb_clr_bitmask_lcd(dev_p,
- LCD_LAYERn_DMA_CFG(plane_id),
- LCD_DMA_LAYER_ENABLE);
+ LCD_LAYERn_DMA_CFG
+ (plane_id),
+ LCD_DMA_LAYER_ENABLE);
kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL,
- plane_status[plane_id].ctrl);
+ plane_status[plane_id].ctrl);
plane_status[plane_id].disable = false;
}
@@ -403,11 +403,6 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev)
kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LINE_CMP);
}
- if (status & LCD_INT_LAYER) {
- /* Clear layer interrupts */
- kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LAYER);
- }
-
if (status & LCD_INT_VERT_COMP) {
/* Read VSTATUS */
val = kmb_read_lcd(dev_p, LCD_VSTATUS);
@@ -425,6 +420,59 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev)
}
}
+ if (status & LCD_INT_DMA_ERR) {
+ val = (status & LCD_INT_DMA_ERR);
+ /* LAYER0 - VL0 */
+ if (val & LAYER0_DMA_FIFO_UNDEFLOW)
+ DRM_INFO("LAYER0:VL0 DMA UNDERFLOW val = 0x%lx", val);
+ if (val & LAYER0_DMA_FIFO_OVERFLOW)
+ DRM_INFO("LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val);
+ if (val & LAYER0_DMA_CB_FIFO_OVERFLOW)
+ DRM_INFO("LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val);
+ if (val & LAYER0_DMA_CB_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER0:VL0 DMA CB UNDERFLOW val = 0x%lx",
+val);
+ if (val & LAYER0_DMA_CR_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER0:VL0 DMA CR UNDERFLOW val = 0x%lx",
+val);
+ if (val & LAYER0_DMA_CR_FIFO_OVERFLOW)
+ DRM_INFO("LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val);
+
+ /* LAYER1 - VL1 */
+ if (val & LAYER1_DMA_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER1:VL1 DMA UNDERFLOW val = 0x%lx", val);
+ if (val & LAYER1_DMA_FIFO_OVERFLOW)
+ DRM_INFO("LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val);
+ if (val & LAYER1_DMA_CB_FIFO_OVERFLOW)
+ DRM_INFO("LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val);
+ if (val & LAYER1_DMA_CB_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER1:VL1 DMA CB UNDERFLOW val = 0x%lx",
+val);
+ if (val & LAYER1_DMA_CR_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER1:VL1 DMA CR UNDERFLOW val = 0x%lx",
+val);
+ if (val & LAYER1_DMA_CR_FIFO_OVERFLOW)
+ DRM_INFO("LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val);
+
+ /* LAYER2 - GL0 */
+ if (val & LAYER2_DMA_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val);
+ if (val & LAYER2_DMA_FIFO_OVERFLOW)
+ DRM_INFO("LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val);
+
+ /* LAYER3 - GL1 */
+ if (val & LAYER3_DMA_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
+ if (val & LAYER3_DMA_FIFO_UNDERFLOW)
+ DRM_INFO("LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
+
+ }
+
+ if (status & LCD_INT_LAYER) {
+ /* Clear layer interrupts */
+ kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LAYER);
+ }
+
/* Clear all interrupts */
kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, 1);
return IRQ_HANDLED;
diff
[PATCH 19/59] drm/kmb: Added ioremap/iounmap for register access
Register physical addresses are remapped and the register mmio
addresses for lcd,mipi and msscam are saved in drm_private.
All register reads/writes are updated to get the mmio offset
from this structure. We are using hardcoded values for register
physical addresses and this will be modified to read from device
tree in the future.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 56 +++---
drivers/gpu/drm/kmb/kmb_drv.c | 103 ---
drivers/gpu/drm/kmb/kmb_drv.h | 64 ---
drivers/gpu/drm/kmb/kmb_dsi.c | 401 +---
drivers/gpu/drm/kmb/kmb_plane.c | 35 ++--
drivers/gpu/drm/kmb/kmb_regs.h | 106 ++-
6 files changed, 437 insertions(+), 328 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 8e127ae..b2b50cc 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -52,21 +52,26 @@ static void kmb_crtc_cleanup(struct drm_crtc *crtc)
static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
{
+ struct drm_device *dev = crtc->dev;
+
/*clear interrupt */
- kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP);
+ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
/*set which interval to generate vertical interrupt */
- kmb_write_lcd(LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC);
+ kmb_write_lcd(dev->dev_private, LCD_VSTATUS_COMPARE,
+ LCD_VSTATUS_COMPARE_VSYNC);
/* enable vertical interrupt */
- kmb_write_lcd(LCD_INT_ENABLE, LCD_INT_VERT_COMP);
+ kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, LCD_INT_VERT_COMP);
return 0;
}
static void kmb_crtc_disable_vblank(struct drm_crtc *crtc)
{
+ struct drm_device *dev = crtc->dev;
+
/*clear interrupt */
- kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP);
+ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
/* disable vertical interrupt */
- kmb_write_lcd(LCD_INT_ENABLE, 0);
+ kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, 0);
/* TBD
* set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register
@@ -89,6 +94,7 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = {
static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct drm_display_mode *m = >state->adjusted_mode;
+ struct drm_device *dev = crtc->dev;
struct videomode vm;
int vsync_start_offset;
int vsync_end_offset;
@@ -104,30 +110,38 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
- kmb_write_lcd(LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1);
- kmb_write_lcd(LCD_V_BACKPORCH, vm.vback_porch - 1);
- kmb_write_lcd(LCD_V_FRONTPORCH, vm.vfront_porch - 1);
- kmb_write_lcd(LCD_VSYNC_WIDTH, vm.vsync_len - 1);
- kmb_write_lcd(LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1);
- kmb_write_lcd(LCD_H_BACKPORCH, vm.hback_porch - 1);
- kmb_write_lcd(LCD_H_FRONTPORCH, vm.hfront_porch - 1);
- kmb_write_lcd(LCD_HSYNC_WIDTH, vm.hsync_len - 1);
+ kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT,
+ m->crtc_vdisplay - 1);
+ kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch - 1);
+ kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch - 1);
+ kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
+ kmb_write_lcd(dev->dev_private, LCD_H_ACTIVEWIDTH,
+ m->crtc_hdisplay - 1);
+ kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch - 1);
+ kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch - 1);
+ kmb_write_lcd(dev->dev_private, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
if (m->flags == DRM_MODE_FLAG_INTERLACE) {
- kmb_write_lcd(LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
- kmb_write_lcd(LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1);
- kmb_write_lcd(LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
- kmb_write_lcd(LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1);
- kmb_write_lcd(LCD_VSYNC_START_EVEN, vsync_start_offset);
- kmb_write_lcd(LCD_VSYNC_END_EVEN, vsync_end_offset);
+ kmb_write_lcd(dev->dev_private,
+ LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
+ kmb_write_lcd(dev->dev_private,
+ LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1);
+ kmb_write_lcd(dev->dev_private,
+ LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
+ kmb_write_lcd(dev->dev_private,
+ LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1);
+ kmb_write_lcd(dev->dev_private,
[PATCH 16/59] drm/kmb: Part6 of Mipi Tx Initialization
This is part2 of DPHY initialization- sets up DPHY PLLs.
v2: simplified mipi_tx_get_vco_params() based on review
v3: added WARN_ON for invalid freq
v4: fixed bug in mipi_tx_get_vco_params
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 194 +++--
drivers/gpu/drm/kmb/kmb_regs.h | 2 +
2 files changed, 189 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index d6cd1f9..b7f23af 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -48,11 +48,33 @@
#define MIPI_TX_CFG_CLK_KHZ 24000
/*DPHY Tx test codes*/
-#define TEST_CODE_HS_FREQ_RANGE_CFG0x44
-#define TEST_CODE_PLL_ANALOG_PROG 0x1F
-#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0
-#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3
-#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4
+#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL0x0E
+#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL0x0F
+#define TEST_CODE_PLL_VCO_CTRL 0x12
+#define TEST_CODE_PLL_GMP_CTRL 0x13
+#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14
+#define TEST_CODE_PLL_LOCK_FILTER 0x15
+#define TEST_CODE_PLL_UNLOCK_FILTER0x16
+#define TEST_CODE_PLL_INPUT_DIVIDER0x17
+#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18
+#define PLL_FEEDBACK_DIVIDER_HIGH(1 << 7)
+#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19
+#define PLL_N_OVR_EN (1 << 4)
+#define PLL_M_OVR_EN (1 << 5)
+#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C
+#define TEST_CODE_PLL_LOCK_DETECTOR0x1D
+#define TEST_CODE_HS_FREQ_RANGE_CFG0x44
+#define TEST_CODE_PLL_ANALOG_PROG 0x1F
+#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0
+#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3
+#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4
+
+/* D-Phy params */
+#define PLL_N_MIN 0
+#define PLL_N_MAX 15
+#define PLL_M_MIN 62
+#define PLL_M_MAX 623
+#define PLL_FVCO_MAX 1250
/*
* These are added here only temporarily for testing,
@@ -800,8 +822,158 @@ static inline void
set_test_mode_src_osc_freq_target_hi_bits(u32 dphy_no,
test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data);
}
+struct vco_params {
+ u32 freq;
+ u32 range;
+ u32 divider;
+};
+
+static struct vco_params vco_table[] = {
+ {52, 0x3f, 8},
+ {80, 0x39, 8},
+ {105, 0x2f, 4},
+ {160, 0x29, 4},
+ {210, 0x1f, 2},
+ {320, 0x19, 2},
+ {420, 0x0f, 1},
+ {630, 0x09, 1},
+ {1100, 0x03, 1},
+ {0x, 0x01, 1},
+};
+
+static void mipi_tx_get_vco_params(struct vco_params *vco)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vco_table); i++) {
+ if (vco->freq < vco_table[i].freq) {
+ *vco = vco_table[i];
+ return;
+ }
+ }
+ WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq);
+}
+
+static void mipi_tx_pll_setup(u32 dphy_no, u32 ref_clk_mhz, u32
target_freq_mhz)
+{
+ /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz
+* Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY)
+* Fout: - valid range: 40~1250 MHz (Gen3 D-PHY)
+* n: - valid range [0 15]
+* N: - N = n + 1
+* -valid range: [1 16]
+* -conditions: - (pll_ref_clk / N) >= 2 MHz
+* -(pll_ref_clk / N) <= 8 MHz
+* m: valid range [62 623]
+* M: - M = m + 2
+* -valid range [64 625]
+* -Fvco = (M/N) * pll_ref_clk
+*/
+ struct vco_params vco_p = {
+ .range = 0,
+ .divider = 1,
+ };
+ u32 best_n = 0, best_m = 0;
+ u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq;
+ u32 best_freq_delta = 3000;
+
+ vco_p.freq = target_freq_mhz;
+ mipi_tx_get_vco_params(_p);
+ /*search pll n parameter */
+ for (n = PLL_N_MIN; n <= PLL_N_MAX; n++) {
+ /*calculate the pll input frequency division ratio
+* multiply by 1000 for precision -
+* no floating point, add n for rounding
+*/
+ div = ((ref_clk_mhz * 1000) + n)/(n+1);
+ /*found a valid n parameter */
+ if ((div < 2000 || div > 8000))
+ continue;
+ /*search pll m parameter */
+ for (m = PLL_M_MIN; m <= PLL_M_MAX; m++) {
+ /*calculate the Fvco(DPHY PLL output frequency)
+* using the current n,m params
+
[PATCH 24/59] drm/kmb: Add ADV7535 bridge
Find ADV 7535 from the device tree and get the bridge driver and attach
it to the DRM and the MIPI encoder.
v2: check for valid encoder node
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 27 ++-
drivers/gpu/drm/kmb/kmb_dsi.c | 26 +-
drivers/gpu/drm/kmb/kmb_dsi.h | 3 ++-
3 files changed, 49 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index e5f4da1..0aa910b 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -55,10 +55,12 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
struct platform_device *pdev = to_platform_device(drm->dev);
+ struct drm_bridge *bridge;
/*struct resource *res;*/
/*u32 version;*/
int irq_lcd, irq_mipi;
int ret;
+ struct device_node *encoder_node;
/* TBD - not sure if clock_get needs to be called here */
/*
@@ -146,7 +148,30 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
goto setup_fail;
}
- kmb_dsi_init(drm);
+ /* find ADV7535 node and initialize it */
+ encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0);
+ if (!encoder_node) {
+ DRM_ERROR("failed to get bridge info from DT\n");
+ ret = -EPROBE_DEFER;
+ goto setup_fail;
+ }
+
+ /* Locate drm bridge from the hdmi encoder DT node */
+ bridge = of_drm_find_bridge(encoder_node);
+ if (!bridge) {
+ DRM_ERROR("failed to get bridge driver from DT\n");
+ ret = -EPROBE_DEFER;
+ goto setup_fail;
+ }
+
+ of_node_put(encoder_node);
+
+ ret = kmb_dsi_init(drm, bridge);
+ if (ret) {
+ DRM_ERROR("failed to initialize DSI\n");
+ goto setup_fail;
+ }
+
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
if (ret < 0) {
DRM_ERROR("failed to install IRQ handler\n");
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 684ddbc..01014c8 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1260,7 +1261,6 @@ static void mipi_tx_init_irqs(struct kmb_drm_private
*dev_p,
spin_unlock_irqrestore(_p->irq_lock, irqflags);
}
-
void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p)
{
uint32_t irq_ctrl_stat_0, hs_stat, hs_enable;
@@ -1293,7 +1293,7 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p)
}
-void kmb_dsi_init(struct drm_device *dev)
+int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge)
{
struct kmb_dsi *kmb_dsi;
struct drm_encoder *encoder;
@@ -1301,21 +1301,27 @@ void kmb_dsi_init(struct drm_device *dev)
struct drm_connector *connector;
struct kmb_dsi_host *host;
struct kmb_drm_private *dev_p = dev->dev_private;
+ int ret = 0;
kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL);
- if (!kmb_dsi)
- return;
+ if (!kmb_dsi) {
+ DRM_ERROR("failed to allocate kmb_dsi\n");
+ return -ENOMEM;
+ }
kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL);
if (!kmb_connector) {
kfree(kmb_dsi);
- return;
+ DRM_ERROR("failed to allocate kmb_connector\n");
+ return -ENOMEM;
}
kmb_dsi->attached_connector = kmb_connector;
connector = _connector->base;
encoder = _dsi->base;
+ encoder->possible_crtcs = 1;
+ encoder->possible_clones = 0;
drm_encoder_init(dev, encoder, _dsi_funcs, DRM_MODE_ENCODER_DSI,
"MIPI-DSI");
@@ -1333,6 +1339,14 @@ void kmb_dsi_init(struct drm_device *dev)
connector->encoder = encoder;
drm_connector_attach_encoder(connector, encoder);
+ /* Link drm_bridge to encoder */
+ ret = drm_bridge_attach(encoder, bridge, NULL, 0);
+ if (ret) {
+ DRM_ERROR("failed to attach bridge to MIPI\n");
+ drm_encoder_cleanup(encoder);
+ return ret;
+ }
+
/* initialize mipi controller */
mipi_tx_init_cntrl(dev_p, _tx_init_cfg);
@@ -1341,4 +1355,6 @@ void kmb_dsi_init(struct drm_device *dev)
/* irq initialization */
mipi_tx_init_irqs(dev_p, _cfg, _tx_init_cfg.tx_ctrl_cfg);
+
+ return 0;
}
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h
index 8f4e0b9..8135252 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.h
+++ b/drivers/gpu/drm/kmb/kmb_dsi.h
@@ -38,6 +38,7 @@ struct kmb_dsi {
struct drm_encoder base;
struct kmb_connector
[PATCH 57/59] drm/kmb: workaround for dma undeflow issue
Initial issue was that display remains shifted after undeflow, this fix is
to recover the dma after underflow so display is clean. Major changes are
reduce LCD_CLK to 200Mhz and some changes in the lcd timing params
run recovery sequence at the EOF after underflow happens
do nothing in plan_update() during recovery
reenable dma at the vsync interrupt after recovery is done
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 27 +++
drivers/gpu/drm/kmb/kmb_drv.c | 156 +++-
drivers/gpu/drm/kmb/kmb_drv.h | 33 +
drivers/gpu/drm/kmb/kmb_plane.c | 12 +++-
drivers/gpu/drm/kmb/kmb_plane.h | 29
drivers/gpu/drm/kmb/kmb_regs.h | 7 +-
6 files changed, 188 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index c01977b..c70928c 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -115,25 +115,25 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
vm.vfront_porch = 2;
// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
vm.vback_porch = 2;
-// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
- vm.vsync_len = 1;
+// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
+ vm.vsync_len = 8;
//vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
vm.hfront_porch = 0;
vm.hback_porch = 0;
//vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
- vm.hsync_len = 7;
-// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
+ vm.hsync_len = 28;
+// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
- vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
- vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
+ vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
+ vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
- DRM_DEBUG
- ("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d
h-bp=%d h-fp=%d hysnc-l=%d",
-__func__, __LINE__, m->crtc_vdisplay, vm.vback_porch,
-vm.vfront_porch, vm.vsync_len, m->crtc_hdisplay, vm.hback_porch,
-vm.hfront_porch, vm.hsync_len);
+ DRM_DEBUG("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d
h-active=%d h-bp=%d h-fp=%d hysnc-l=%d",
+ __func__, __LINE__,
+ m->crtc_vdisplay, vm.vback_porch, vm.vfront_porch,
+ vm.vsync_len, m->crtc_hdisplay, vm.hback_porch,
+ vm.hfront_porch, vm.hsync_len);
kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT,
- m->crtc_vdisplay - 1);
+ m->crtc_vdisplay - 1);
kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch);
kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch);
kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
@@ -145,7 +145,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
/*this is hardcoded as 0 in the Myriadx code */
kmb_write_lcd(dev->dev_private, LCD_VSYNC_START, 0);
kmb_write_lcd(dev->dev_private, LCD_VSYNC_END, 0);
-
+ /* back ground color */
+ kmb_write_lcd(dev->dev_private, LCD_BG_COLOUR_LS, 0x4);
if (m->flags == DRM_MODE_FLAG_INTERLACE) {
kmb_write_lcd(dev->dev_private,
LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 68e7b5c..bafc02a 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -51,10 +51,10 @@
#include "kmb_dsi.h"
//#define DEBUG
-
/* IRQ handler */
static irqreturn_t kmb_isr(int irq, void *arg);
+int under_flow = 0, flush_done = 0, layer_no = 0;
static struct clk *clk_lcd;
static struct clk *clk_mipi;
static struct clk *clk_mipi_ecfg;
@@ -133,6 +133,7 @@ static void __iomem *kmb_map_mmio(struct platform_device
*pdev, char *name)
return mem;
}
+//#define ICAM_LCD_QOS
static int kmb_load(struct drm_device *drm, unsigned long flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
@@ -140,6 +141,9 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
int irq_lcd;
int ret = 0;
unsigned long clk;
+#ifdef ICAM_LCD_QOS
+ int val = 0;
+#endif
/* Map MIPI MMIO registers */
dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs");
@@ -173,6 +177,13 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
iounmap(dev_p->mipi_mmio);
return -ENOMEM;
}
+#ifdef ICAM_LCD_QOS
+ dev_p->icamlcd_mmio = ioremap_nocache(ICAM_MMIO, ICAM_MMIO_SIZE);
+ if (IS_ERR(dev_p->icamlcd_mmio)) {
+ DRM_ERROR("failed to map ICAM registers\n");
+
[PATCH 44/59] drm/kmb: Mipi settings from input timings
Removed hardcoded timings, set timings based on the current mode's
input timings. Also calculate and set the lane rate based on the
timings.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 93 +++---
drivers/gpu/drm/kmb/kmb_dsi.h | 2 +-
3 files changed, 61 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index d9f6199..75e78d7 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -102,7 +102,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
int vsync_end_offset;
#endif
/* initialize mipi */
- kmb_dsi_hw_init(dev);
+ kmb_dsi_hw_init(dev, m);
+ DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n",
+ m->crtc_vsync_start - m->crtc_vdisplay,
+ m->crtc_vtotal - m->crtc_vsync_end,
+ m->crtc_vsync_end - m->crtc_vsync_start,
+ m->crtc_hsync_start - m->crtc_hdisplay,
+ m->crtc_htotal - m->crtc_hsync_end,
+ m->crtc_hsync_end - m->crtc_hsync_start);
#ifdef LCD_TEST
// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
vm.vfront_porch = 2;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 3b3bb0a..3368e97 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -47,19 +47,12 @@ static int hw_initialized;
//#define MIPI_TX_TEST_PATTERN_GENERATION
//#define MIPI_DMA
//#define RTL_TEST
-//#define IMG_WIDTH_PX 640
-//#define IMG_HEIGHT_LINES 10
-
-#define LCD_BYTESPP 1
/*MIPI TX CFG*/
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 800
#define MIPI_TX_LANE_DATA_RATE_MBPS 891
-//#define MIPI_TX_LANE_DATA_RATE_MBPS 80
#define MIPI_TX_REF_CLK_KHZ 24000
-//#define MIPI_TX_REF_CLK_KHZ 23809
#define MIPI_TX_CFG_CLK_KHZ 24000
+#define MIPI_TX_BPP24
/*DPHY Tx test codes*/
#define TEST_CODE_FSM_CONTROL 0x03
@@ -98,23 +91,12 @@ static struct mipi_dsi_host *dsi_host;
static struct mipi_dsi_device *dsi_device;
/*
- * These are added here only temporarily for testing,
- * these will eventually go to the device tree sections,
- * and can be used as a refernce later for device tree additions
+ * Default setting is 1080p, 4 lanes.
*/
-#define RES_1920x1080
-#ifdef RES_1920x1080
#define IMG_HEIGHT_LINES 1080
#define IMG_WIDTH_PX 1920
#define MIPI_TX_ACTIVE_LANES 4
-#endif
-//#define RES_1280x720
-#ifdef RES_1280x720
-#define IMG_HEIGHT_LINES 720
-#define IMG_WIDTH_PX 1280
-#define MIPI_TX_ACTIVE_LANES 2
-#endif
struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.width_pixels = IMG_WIDTH_PX,
.height_lines = IMG_HEIGHT_LINES,
@@ -124,7 +106,6 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.dma_packed = 0
};
-#ifdef RES_1920x1080
struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.sections[0] = _tx_frame0_sect_cfg,
.sections[1] = NULL,
@@ -137,22 +118,6 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
.h_backporch = 148,
.h_frontporch = 88
};
-#endif
-
-#ifdef RES_1280x720
-struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
- .sections[0] = _tx_frame0_sect_cfg,
- .sections[1] = NULL,
- .sections[2] = NULL,
- .sections[3] = NULL,
- .vsync_width = 5,
- .v_backporch = 20,
- .v_frontporch = 5,
- .hsync_width = 40,
- .h_backporch = 220,
- .h_frontporch = 110,
-};
-#endif
struct mipi_tx_dsi_cfg mipitx_dsi_cfg = {
.hfp_blank_en = 0,
@@ -1740,10 +1705,58 @@ int kmb_kernel_read(struct file *file, loff_t offset,
return ret;
}
-int kmb_dsi_hw_init(struct drm_device *dev)
+int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode)
{
struct kmb_drm_private *dev_p = dev->dev_private;
+ u64 data_rate;
+
+ mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES;
+ if (mode != NULL) {
+ mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay;
+ mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay;
+ mipitx_frame0_cfg.vsync_width =
+ mode->crtc_vsync_end - mode->crtc_vsync_start;
+ mipitx_frame0_cfg.v_backporch =
+ mode->crtc_vtotal - mode->crtc_vsync_end;
+ mipitx_frame0_cfg.v_frontporch =
+ mode->crtc_vsync_start - mode->crtc_vdisplay;
+ mipitx_frame0_cfg.hsync_width =
+ mode->crtc_hsync_end - mode->crtc_hsync_start;
+ mipitx_frame0_cfg.h_backporch =
+ mode->crtc_htotal - mode->crtc_hsync_end;
+
[PATCH 45/59] drm/kmb: Enable LCD interrupts
Enabled vblank interrupts for LCD.
Signed-off-by: Anitha Chrisanithus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 35 +++
drivers/gpu/drm/kmb/kmb_drv.c | 41 +
drivers/gpu/drm/kmb/kmb_plane.c | 6 +++---
drivers/gpu/drm/kmb/kmb_regs.h | 2 +-
4 files changed, 40 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 75e78d7..b617507 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -61,7 +61,8 @@ static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_VSTATUS_COMPARE,
LCD_VSTATUS_COMPARE_VSYNC);
/* enable vertical interrupt */
- kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, LCD_INT_VERT_COMP);
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE,
+ LCD_INT_VERT_COMP);
return 0;
}
@@ -72,13 +73,9 @@ static void kmb_crtc_disable_vblank(struct drm_crtc *crtc)
/*clear interrupt */
kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
/* disable vertical interrupt */
- kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, 0);
+ kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE,
+ LCD_INT_VERT_COMP);
-/* TBD
- * set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register
- * set the required bit LCD_VSTATUS_COMPARE register
- * Not sure if anything needs to be done in the ICB
- */
}
static const struct drm_crtc_funcs kmb_crtc_funcs = {
@@ -100,7 +97,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct videomode vm;
int vsync_start_offset;
int vsync_end_offset;
-#endif
+
/* initialize mipi */
kmb_dsi_hw_init(dev, m);
DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n",
@@ -110,7 +107,6 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
m->crtc_hsync_start - m->crtc_hdisplay,
m->crtc_htotal - m->crtc_hsync_end,
m->crtc_hsync_end - m->crtc_hsync_start);
-#ifdef LCD_TEST
// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
vm.vfront_porch = 2;
// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
@@ -174,7 +170,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc,
clk_prepare_enable(lcd->clk);
kmb_crtc_mode_set_nofb(crtc);
-// drm_crtc_vblank_on(crtc);
+ drm_crtc_vblank_on(crtc);
}
static void kmb_crtc_atomic_disable(struct drm_crtc *crtc,
@@ -185,33 +181,32 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc,
/* always disable planes on the CRTC that is being turned off */
drm_atomic_helper_disable_planes_on_crtc(old_state, false);
-// drm_crtc_vblank_off(crtc);
+ drm_crtc_vblank_off(crtc);
clk_disable_unprepare(lcd->clk);
}
static void kmb_crtc_atomic_begin(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
- /* TBD */
- /*disable vblank interrupts here
-* clear BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE
-*/
+ struct drm_device *dev = crtc->dev;
+
+ kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE,
+ LCD_INT_VERT_COMP);
}
static void kmb_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
- /* TBD */
- /*enable vblank interrupts after
-* set BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE
-*/
+ struct drm_device *dev = crtc->dev;
+
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE,
+ LCD_INT_VERT_COMP);
spin_lock_irq(>dev->event_lock);
if (crtc->state->event)
drm_crtc_send_vblank_event(crtc, crtc->state->event);
crtc->state->event = NULL;
spin_unlock_irq(>dev->event_lock);
-
}
static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 64e45e7..d987529 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -147,10 +147,8 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
struct platform_device *pdev = to_platform_device(drm->dev);
-#ifdef WIP
/*u32 version;*/
- int irq_lcd, irq_mipi;
-#endif
+ int irq_lcd;// irq_mipi;
int ret = 0;
unsigned long clk;
@@ -286,10 +284,9 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff);
kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0x);
#endif //KMB_CLOCKS
-#ifdef WIP
[PATCH 53/59] drm/kmb: disable the LCD layer in EOF irq handler
When disabling/enabling LCD layers, the change takes effect
immediately and does not wait for EOF (end of frame). If we
disable an LCD layer in kmb_plane_atomic_disable, then the frame
reappears with incorrect display offsets.
The solution is to mark the plane as disabled when
kmb_plane_atomic_disable is called but actually disable the LCD
layer when EOF irq is being handled.
Also only enable one plane (video plane0) as there is no use case for
multiple planes.
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 37 +++--
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
drivers/gpu/drm/kmb/kmb_plane.c | 24
drivers/gpu/drm/kmb/kmb_plane.h | 9 -
4 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index c699f01..79ab0bc 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -62,6 +62,8 @@ static struct clk *clk_mipi_cfg;
struct drm_bridge *adv_bridge;
+extern struct layer_status plane_status[KMB_MAX_PLANES];
+
int kmb_display_clk_enable(void)
{
int ret = 0;
@@ -367,25 +369,48 @@ static void kmb_setup_mode_config(struct drm_device *drm)
static irqreturn_t handle_lcd_irq(struct drm_device *dev)
{
unsigned long status, val;
+ int plane_id;
+ struct kmb_drm_private *dev_p = dev->dev_private;
status = kmb_read_lcd(dev->dev_private, LCD_INT_STATUS);
if (status & LCD_INT_EOF) {
/* TODO - handle EOF interrupt? */
- kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_EOF);
+ kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_EOF);
+
+ /* When disabling/enabling LCD layers, the change takes effect
+* immediately and does not wait for EOF (end of frame).
+* When kmb_plane_atomic_disable is called, mark the plane as
+* disabled but actually disable the plane when EOF irq is
+* being handled.
+*/
+ for (plane_id = LAYER_0; plane_id < KMB_MAX_PLANES;
+ plane_id++) {
+ if (plane_status[plane_id].disable) {
+ kmb_clr_bitmask_lcd(dev_p,
+ LCD_LAYERn_DMA_CFG(plane_id),
+ LCD_DMA_LAYER_ENABLE);
+
+ kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL,
+ plane_status[plane_id].ctrl);
+
+ plane_status[plane_id].disable = false;
+ }
+ }
}
+
if (status & LCD_INT_LINE_CMP) {
/* clear line compare interrupt */
- kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR,
- LCD_INT_LINE_CMP);
+ kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LINE_CMP);
}
+
if (status & LCD_INT_LAYER) {
/* Clear layer interrupts */
- kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LAYER);
+ kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LAYER);
}
if (status & LCD_INT_VERT_COMP) {
/* Read VSTATUS */
- val = kmb_read_lcd(dev->dev_private, LCD_VSTATUS);
+ val = kmb_read_lcd(dev_p, LCD_VSTATUS);
val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK);
switch (val) {
case LCD_VSTATUS_COMPARE_VSYNC:
@@ -401,7 +426,7 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev)
}
/* Clear all interrupts */
- kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0);
+ kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, 1);
return IRQ_HANDLED;
}
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 4916b217..83824f7 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -39,6 +39,7 @@
#define crtc_to_kmb_priv(x)container_of(x, struct kmb_drm_private, crtc)
+
struct kmb_drm_private {
struct drm_device drm;
void __iomem *lcd_mmio;
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 8d83238..81250e1 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -41,6 +41,8 @@
#include "kmb_regs.h"
#include "kmb_drv.h"
+struct layer_status plane_status[KMB_MAX_PLANES];
+
const uint32_t layer_irqs[] = {
LCD_INT_VL0,
LCD_INT_VL1,
@@ -82,34 +84,24 @@ static void kmb_plane_atomic_disable(struct drm_plane
*plane,
struct drm_plane_state *state)
{
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
- int ctrl = 0;
- struct kmb_drm_private *dev_p;
- int plane_id;
-
- dev_p = plane->dev->dev_private;
- plane_id
[PATCH 43/59] drm/kmb: Changed name of driver to kmb-drm
name change
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/Makefile | 4 ++--
drivers/gpu/drm/kmb/kmb_drv.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile
index 8102bc9..527d737 100644
--- a/drivers/gpu/drm/kmb/Makefile
+++ b/drivers/gpu/drm/kmb/Makefile
@@ -1,2 +1,2 @@
-kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o kmb_dsi.o
-obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-display.o
+kmb-drm-y := kmb_crtc.o kmb_drv.o kmb_plane.o kmb_dsi.o
+obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-drm.o
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 3b4b7a1..64e45e7 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -466,7 +466,7 @@ static struct drm_driver kmb_driver = {
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
.gem_prime_mmap = drm_gem_cma_prime_mmap,
.fops = ,
- .name = "kmb_display",
+ .name = "kmb-drm",
.desc = "KEEMBAY DISPLAY DRIVER ",
.date = "20190122",
.major = 1,
@@ -644,7 +644,7 @@ static struct platform_driver kmb_platform_driver = {
.probe = kmb_probe,
.remove = kmb_remove,
.driver = {
- .name = "kmb_display",
+ .name = "kmb-drm",
.pm = _pm_ops,
.of_match_table = kmb_of_match,
},
--
2.7.4
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[PATCH 27/59] drm/kmb: minor name change to match device tree
name change
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 1f0dcbe..b1cc8ad 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -475,7 +475,7 @@ static int kmb_remove(struct platform_device *pdev)
}
static const struct of_device_id kmb_of_match[] = {
- {.compatible = "kmb,display"},
+ {.compatible = "intel,kmb_display"},
{},
};
--
2.7.4
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[PATCH 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation
From: Edmund Dea
Added test pattern generator function. Enable this at compile time to
test if mipi is working. mipi->hdmi section
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 31 +++
drivers/gpu/drm/kmb/kmb_dsi.h | 7 +++
drivers/gpu/drm/kmb/kmb_regs.h | 11 +++
3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 8ab4de7..47ec2ab 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -764,6 +764,32 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private
*dev_p, u8 fg_id,
kmb_write_mipi(dev_p, MIPI_TXm_HS_CTRL(ctrl_no), ctrl);
}
+#ifdef MIPI_TX_TEST_PATTERN_GENERATION
+static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc,
+ int tp_sel, u32 stripe_width, u32 color0, u32 color1)
+{
+ u32 ctrl_no = MIPI_CTRL6;
+
+ /* Select test pattern mode on the virtual channel */
+ kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no),
+ TP_SEL_VCm(vc, tp_sel));
+
+ if (tp_sel == MIPI_TX_HS_TP_V_STRIPES ||
+ tp_sel == MIPI_TX_HS_TP_H_STRIPES) {
+ kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no),
+ TP_STRIPE_WIDTH(stripe_width));
+ }
+
+ /* Configure test pattern colors */
+ kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR0, color0);
+ kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR1, color1);
+
+ /* Enable test pattern generation on the virtual channel */
+ kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no),
+ TP_EN_VCm(vc));
+}
+#endif
+
static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,
struct mipi_ctrl_cfg *ctrl_cfg)
{
@@ -827,6 +853,11 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private
*dev_p,
/*Multi-Channel FIFO Configuration*/
mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id);
+#ifdef MIPI_TX_TEST_PATTERN_GENERATION
+ mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0, 0,
+ 0x, 0);
+#endif
+
/*Frame Generator Enable */
mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg);
return ret;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h
index e85625b..ef526b4 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.h
+++ b/drivers/gpu/drm/kmb/kmb_dsi.h
@@ -200,6 +200,13 @@ enum mipi_dsi_data_type {
DSI_LP_DT_RESERVED_3F = 0x3f
};
+enum mipi_tx_hs_tp_sel {
+ MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0 = 0,
+ MIPI_TX_HS_TP_WHOLE_FRAME_COLOR1,
+ MIPI_TX_HS_TP_V_STRIPES,
+ MIPI_TX_HS_TP_H_STRIPES,
+};
+
enum dphy_mode {
MIPI_DPHY_SLAVE = 0,
MIPI_DPHY_MASTER
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 20b331d..2377439 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -645,6 +645,17 @@
MIPI_TX_HS_IRQ_CLEAR \
+ HS_OFFSET(M), val)
+/* MIPI Test Pattern Generation */
+#define MIPI_TX_HS_TEST_PAT_CTRL (0x230)
+#define MIPI_TXm_HS_TEST_PAT_CTRL(M) \
+ (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M))
+#define TP_EN_VCm(M) ((M) * 0x04)
+#define TP_SEL_VCm(M, N) \
+ (N << (((M) * 0x04) + 1))
+#define TP_STRIPE_WIDTH(M) ((M) << 16)
+#define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234)
+#define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238)
+
/* D-PHY regs */
#define DPHY_ENABLE(0x100)
#define DPHY_INIT_CTRL0(0x104)
--
2.7.4
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[PATCH 50/59] drm/kmb: Do the layer initializations only once
The issue was video starts fine, but towards the end, the color disappers.
Do the layer initializations only once, but update the DMA registers
for every frame. Also changed DRM_INFO to DRM_DEBUG.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 150 ++--
1 file changed, 66 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 35dece3..8aa48b5 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -117,6 +117,9 @@ static const u32 csc_coef_lcd[] = {
-179, 125, -226
};
+/*plane initialization status */
+static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 };
+
static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
{
int i;
@@ -177,9 +180,9 @@ static void kmb_plane_atomic_disable(struct drm_plane
*plane,
kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id),
LCD_DMA_LAYER_ENABLE);
kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl);
- DRM_INFO("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n",
-__func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL),
-kmb_read_lcd(dev_p, LCD_INT_ENABLE));
+ DRM_DEBUG("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n",
+ __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL),
+ kmb_read_lcd(dev_p, LCD_INT_ENABLE));
}
unsigned int set_pixel_format(u32 format)
@@ -337,8 +340,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
unsigned int src_w, src_h, crtc_x, crtc_y;
unsigned char plane_id;
int num_planes;
- /*plane initialization status */
- static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 };
static dma_addr_t addr[MAX_SUB_PLANES] = { 0, 0, 0 };
if (!plane || !plane->state || !state)
@@ -359,9 +360,56 @@ static void kmb_plane_atomic_update(struct drm_plane
*plane,
crtc_x = plane->state->crtc_x;
crtc_y = plane->state->crtc_y;
- DRM_INFO
+ DRM_DEBUG
("%s : %d src_w=%d src_h=%d, fb->format->format=0x%x
fb->flags=0x%x",
__func__, __LINE__, src_w, src_h, fb->format->format, fb->flags);
+
+ width = fb->width;
+ height = fb->height;
+ dma_len = (width * height * fb->format->cpp[0]);
+ DRM_DEBUG("%s : %d dma_len=%d ", __func__, __LINE__, dma_len);
+ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len);
+ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len);
+
+ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id),
+ fb->pitches[0]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id),
+ (width * fb->format->cpp[0]));
+
+ addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0);
+ dev_p->fb_addr = (dma_addr_t) addr;
+ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id),
+ addr[Y_PLANE] + fb->offsets[0]);
+ /*program Cb/Cr for planar formats */
+ if (num_planes > 1) {
+ if (fb->format->format == DRM_FORMAT_YUV420 ||
+ fb->format->format == DRM_FORMAT_YVU420)
+ width /= 2;
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id),
+ fb->pitches[LAYER_1]);
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id),
+ (width * fb->format->cpp[0]));
+ addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state,
+ U_PLANE);
+ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id),
+ addr[U_PLANE]);
+ if (num_planes == 3) {
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id),
+ fb->pitches[LAYER_2]);
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id),
+ (width * fb->format->cpp[0]));
+ addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb,
+ plane->state,
+ V_PLANE);
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_START_CR_ADR(plane_id),
+ addr[V_PLANE]);
+ }
+ }
if (plane_init_status[plane_id] != INITIALIZED) {
kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1);
kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1);
[PATCH 17/59] drm/kmb: Part7 of Mipi Tx Initialization
This completes the DPHY initialization and Tx initialization.
v2: minor code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 65 ++
drivers/gpu/drm/kmb/kmb_dsi.h | 18
drivers/gpu/drm/kmb/kmb_regs.h | 15 --
3 files changed, 91 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index b7f23af..51bec35 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -48,6 +48,7 @@
#define MIPI_TX_CFG_CLK_KHZ 24000
/*DPHY Tx test codes*/
+#define TEST_CODE_FSM_CONTROL 0x03
#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL0x0E
#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL0x0F
#define TEST_CODE_PLL_VCO_CTRL 0x12
@@ -1081,10 +1082,10 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg
*cfg, u32 dphy_no,
cfg->lane_rate_mbps/2);
/*Set clksel */
- kmb_write_bits_mipi(DPHY_INIT_CTRL1, 18, 2, 0x01);
+ kmb_write_bits_mipi(DPHY_INIT_CTRL1, PLL_CLKSEL_0, 2, 0x01);
/*Set pll_shadow_control */
- kmb_write_bits_mipi(DPHY_INIT_CTRL1, 16, 1, 0x01);
+ kmb_set_bit_mipi(DPHY_INIT_CTRL1, PLL_SHADOW_CTRL);
}
/*Send NORMAL OPERATION test code */
@@ -1107,7 +1108,48 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg
*cfg, u32 dphy_no,
/* enable DATA LANES */
kmb_write_bits_mipi(DPHY_ENABLE, dphy_no * 2, 2,
- ((1 << cfg->active_lanes) - 1));
+ ((1 << cfg->active_lanes) - 1));
+
+ /*Take D-PHY out of shutdown mode */
+ /* deassert SHUTDOWNZ signal*/
+ SET_DPHY_INIT_CTRL0(dphy_no, SHUTDOWNZ);
+ /*deassert RSTZ signal */
+ SET_DPHY_INIT_CTRL0(dphy_no, RESETZ);
+}
+
+static void dphy_wait_fsm(u32 dphy_no, enum dphy_tx_fsm fsm_state)
+{
+ enum dphy_tx_fsm val = DPHY_TX_POWERDWN;
+
+ do {
+ test_mode_send(dphy_no, TEST_CODE_FSM_CONTROL, 0x80);
+ /*TODO-need to add a time out and return failure */
+ val = GET_TEST_DOUT0_3(dphy_no);
+ } while (val != fsm_state);
+
+}
+
+static u32 wait_init_done(u32 dphy_no, u32 active_lanes)
+{
+ u32 stopstatedata = 0;
+ u32 data_lanes = (1 << active_lanes) - 1;
+
+ do {
+ stopstatedata = GET_STOPSTATE_DATA(dphy_no);
+ /*TODO-need to add a time out and return failure */
+ } while (stopstatedata != data_lanes);
+
+ return 0;
+}
+
+static u32 wait_pll_lock(u32 dphy_no)
+{
+ do {
+ ;
+ /*TODO-need to add a time out and return failure */
+ } while (!GET_PLL_LOCK(dphy_no));
+
+ return 0;
}
static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg)
@@ -1133,9 +1175,22 @@ static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg)
*/
/*PHY #N+1 ('slave') */
dphy_init_sequence(cfg, dphy_no + 1, MIPI_DPHY_SLAVE);
- /*TODO PHY #N master */
+
+ dphy_wait_fsm(dphy_no + 1, DPHY_TX_LOCK);
+
+ /*PHY #N master*/
+ dphy_init_sequence(cfg, dphy_no, MIPI_DPHY_MASTER);
+ /* wait for DPHY init to complete */
+ wait_init_done(dphy_no, MIPI_DPHY_D_LANES);
+ wait_init_done(dphy_no + 1,
+ cfg->active_lanes - MIPI_DPHY_D_LANES);
+ wait_pll_lock(dphy_no);
+ wait_pll_lock(dphy_no + 1);
+ } else {/* Single DPHY */
+ dphy_init_sequence(cfg, dphy_no, MIPI_DPHY_MASTER);
+ wait_init_done(dphy_no, cfg->active_lanes);
+ wait_pll_lock(dphy_no);
}
- /*TODO- Single DPHY */
return 0;
}
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h
index d878d27..eb38ae7 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.h
+++ b/drivers/gpu/drm/kmb/kmb_dsi.h
@@ -204,12 +204,30 @@ enum dphy_mode {
MIPI_DPHY_MASTER
};
+enum dphy_tx_fsm {
+ DPHY_TX_POWERDWN = 0,
+ DPHY_TX_BGPON,
+ DPHY_TX_TERMCAL,
+ DPHY_TX_TERMCALUP,
+ DPHY_TX_OFFSETCAL,
+ DPHY_TX_LOCK,
+ DPHY_TX_SRCAL,
+ DPHY_TX_IDLE,
+ DPHY_TX_ULP,
+ DPHY_TX_LANESTART,
+ DPHY_TX_CLKALIGN,
+ DPHY_TX_DDLTUNNING,
+ DPHY_TX_ULP_FORCE_PLL,
+ DPHY_TX_LOCK_LOSS
+};
+
struct mipi_data_type_params {
uint8_t size_constraint_pixels;
uint8_t size_constraint_bytes;
uint8_t pixels_per_pclk;
uint8_t bits_per_pclk;
};
+
struct mipi_tx_dsi_cfg {
uint8_t hfp_blank_en; /*horizontal front porch blanking enable */
uint8_t eotp_en;/*End of transmission packet enable */
diff --git
[PATCH 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI
Enable clocks for LCD, mipi common and mipi tx0
Renamed MSS_CAM_CLK_CTRL and also fixed bug in the
call to set this register.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 8
drivers/gpu/drm/kmb/kmb_drv.h | 14 ++
drivers/gpu/drm/kmb/kmb_dsi.c | 6 --
drivers/gpu/drm/kmb/kmb_regs.h | 7 ++-
4 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 48c2b28..4eb472b 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -261,6 +261,9 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
DRM_INFO("Get clk_mipi_cfg after set = %ld\n", clk);
}
+ /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */
+ kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, LCD | MIPI_COMMON |
+ MIPI_TX0);
#ifdef WIP
/* Register irqs here - section 17.3 in databook
* lists LCD at 79 and 82 for MIPI under MSS CPU -
@@ -312,10 +315,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
/* Initialize MIPI DSI */
ret = kmb_dsi_init(drm, adv_bridge);
- if (ret == -EPROBE_DEFER) {
- DRM_INFO("%s: wait for external bridge driver DT", __func__);
- return -EPROBE_DEFER;
- } else if (ret) {
+ if (ret) {
DRM_ERROR("failed to initialize DSI\n");
goto setup_fail;
}
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 9e3bb83..596f4fe 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -108,6 +108,20 @@ static inline void kmb_write_msscam(struct kmb_drm_private
*dev_p,
writel(value, (dev_p->msscam_mmio + reg));
}
+static inline u32 kmb_read_msscam(struct kmb_drm_private *dev_p,
+ unsigned int reg)
+{
+ return readl(dev_p->msscam_mmio + reg);
+}
+
+static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p,
+ unsigned int reg, u32 mask)
+{
+ u32 reg_val = kmb_read_msscam(dev_p, reg);
+
+ kmb_write_msscam(dev_p, reg, (reg_val | mask));
+}
+
static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg)
{
return readl(dev_p->lcd_mmio + reg);
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index af04eb9..8ab4de7 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -814,9 +814,11 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private
*dev_p,
active_vchannels++;
/*connect lcd to mipi */
- kmb_write_msscam(dev_p, MSS_CAM_BASE_ADDR +
- MIPI_TX_MSS_LCD_MIPI_CFG, 1);
+ kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);
+ /*stop iterating as only one virtual channel shall be used for
+* LCD connection
+*/
break;
}
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index f8a7abf..20b331d 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -697,6 +697,11 @@
& (1 << (dphy - MIPI_DPHY6)))
#define DPHY_CFG_CLK_EN(0x18c)
-#define MIPI_TX_MSS_LCD_MIPI_CFG (0x04)
+#define MSS_LCD_MIPI_CFG (0x04)
+#define MSS_CAM_CLK_CTRL (0x10)
+#define LCD (1<<1)
+#define MIPI_COMMON (1<<2)
+#define MIPI_TX0 (1<<9)
+
#define BIT_MASK_16(0x)
#endif /* __KMB_REGS_H__ */
--
2.7.4
___
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[PATCH 15/59] drm/kmb: Part5 of Mipi Tx Intitialization
This is part1 of DPHY initialization.
v2: remove kmb_write() as the function provides no benefit over
calling writel() directly.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 5 -
drivers/gpu/drm/kmb/kmb_dsi.c | 346 ++---
drivers/gpu/drm/kmb/kmb_dsi.h | 10 ++
drivers/gpu/drm/kmb/kmb_regs.h | 48 +-
4 files changed, 376 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index ba5b3e0..434be1a 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -84,11 +84,6 @@ static inline void kmb_write_bits(struct kmb_drm_private
*lcd,
}
#endif
-static inline void kmb_write(void *reg, u32 value)
-{
- writel(value, reg);
-}
-
static inline void kmb_write_lcd(unsigned int reg, u32 value)
{
writel(value, (LCD_BASE_ADDR + reg));
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index adcfe81..d6cd1f9 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -47,6 +47,13 @@
#define MIPI_TX_REF_CLK_KHZ 24000
#define MIPI_TX_CFG_CLK_KHZ 24000
+/*DPHY Tx test codes*/
+#define TEST_CODE_HS_FREQ_RANGE_CFG0x44
+#define TEST_CODE_PLL_ANALOG_PROG 0x1F
+#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0
+#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3
+#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4
+
/*
* These are added here only temporarily for testing,
* these will eventually go to the device tree sections,
@@ -107,6 +114,77 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = {
};
+typedef struct{
+ uint16_t default_bit_rate_mbps;
+ uint8_t hsfreqrange_code;
+} mipi_hs_freq_range_cfg;
+
+static mipi_hs_freq_range_cfg
+ mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = {
+ {.default_bit_rate_mbps = 80, .hsfreqrange_code = 0x00},
+ {.default_bit_rate_mbps = 90, .hsfreqrange_code = 0x10},
+ {.default_bit_rate_mbps = 100, .hsfreqrange_code = 0x20},
+ {.default_bit_rate_mbps = 110, .hsfreqrange_code = 0x30},
+ {.default_bit_rate_mbps = 120, .hsfreqrange_code = 0x01},
+ {.default_bit_rate_mbps = 130, .hsfreqrange_code = 0x11},
+ {.default_bit_rate_mbps = 140, .hsfreqrange_code = 0x21},
+ {.default_bit_rate_mbps = 150, .hsfreqrange_code = 0x31},
+ {.default_bit_rate_mbps = 160, .hsfreqrange_code = 0x02},
+ {.default_bit_rate_mbps = 170, .hsfreqrange_code = 0x12},
+ {.default_bit_rate_mbps = 180, .hsfreqrange_code = 0x22},
+ {.default_bit_rate_mbps = 190, .hsfreqrange_code = 0x32},
+ {.default_bit_rate_mbps = 205, .hsfreqrange_code = 0x03},
+ {.default_bit_rate_mbps = 220, .hsfreqrange_code = 0x13},
+ {.default_bit_rate_mbps = 235, .hsfreqrange_code = 0x23},
+ {.default_bit_rate_mbps = 250, .hsfreqrange_code = 0x33},
+ {.default_bit_rate_mbps = 275, .hsfreqrange_code = 0x04},
+ {.default_bit_rate_mbps = 300, .hsfreqrange_code = 0x14},
+ {.default_bit_rate_mbps = 325, .hsfreqrange_code = 0x25},
+ {.default_bit_rate_mbps = 350, .hsfreqrange_code = 0x35},
+ {.default_bit_rate_mbps = 400, .hsfreqrange_code = 0x05},
+ {.default_bit_rate_mbps = 450, .hsfreqrange_code = 0x16},
+ {.default_bit_rate_mbps = 500, .hsfreqrange_code = 0x26},
+ {.default_bit_rate_mbps = 550, .hsfreqrange_code = 0x37},
+ {.default_bit_rate_mbps = 600, .hsfreqrange_code = 0x07},
+ {.default_bit_rate_mbps = 650, .hsfreqrange_code = 0x18},
+ {.default_bit_rate_mbps = 700, .hsfreqrange_code = 0x28},
+ {.default_bit_rate_mbps = 750, .hsfreqrange_code = 0x39},
+ {.default_bit_rate_mbps = 800, .hsfreqrange_code = 0x09},
+ {.default_bit_rate_mbps = 850, .hsfreqrange_code = 0x19},
+ {.default_bit_rate_mbps = 900, .hsfreqrange_code = 0x29},
+ {.default_bit_rate_mbps = 1000, .hsfreqrange_code = 0x0A},
+ {.default_bit_rate_mbps = 1050, .hsfreqrange_code = 0x1A},
+ {.default_bit_rate_mbps = 1100, .hsfreqrange_code = 0x2A},
+ {.default_bit_rate_mbps = 1150, .hsfreqrange_code = 0x3B},
+ {.default_bit_rate_mbps = 1200, .hsfreqrange_code = 0x0B},
+ {.default_bit_rate_mbps = 1250, .hsfreqrange_code = 0x1B},
+ {.default_bit_rate_mbps = 1300, .hsfreqrange_code = 0x2B},
+ {.default_bit_rate_mbps = 1350, .hsfreqrange_code = 0x3C},
+ {.default_bit_rate_mbps = 1400, .hsfreqrange_code = 0x0C},
+ {.default_bit_rate_mbps = 1450, .hsfreqrange_code = 0x1C},
+ {.default_bit_rate_mbps = 1500, .hsfreqrange_code = 0x2C},
+ {.default_bit_rate_mbps = 1550, .hsfreqrange_code = 0x3D},
+ {.default_bit_rate_mbps = 1600, .hsfreqrange_code = 0x0D},
+ {.default_bit_rate_mbps = 1650, .hsfreqrange_code = 0x1D},
+ {.default_bit_rate_mbps = 1700, .hsfreqrange_code = 0x2E},
+ {.default_bit_rate_mbps = 1750,
[PATCH 46/59] drm/kmb: Enable LCD interrupts during modeset
The issue was that spurious interrupts were happening before the LCD
controller was enabled and system hangs. Fix is to
clear LCD interrupts and disable them before modeset
and re enable them after enabling LCD controller.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 6 +-
drivers/gpu/drm/kmb/kmb_drv.c | 21 +++--
2 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index b617507..16f6c7f 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -97,6 +97,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct videomode vm;
int vsync_start_offset;
int vsync_end_offset;
+ unsigned int val = 0;
/* initialize mipi */
kmb_dsi_hw_init(dev, m);
@@ -107,6 +108,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
m->crtc_hsync_start - m->crtc_hdisplay,
m->crtc_htotal - m->crtc_hsync_end,
m->crtc_hsync_end - m->crtc_hsync_start);
+ val = kmb_read_lcd(dev->dev_private, LCD_INT_ENABLE);
+ kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, val);
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0);
// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
vm.vfront_porch = 2;
// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
@@ -155,9 +159,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, 10);
kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10);
}
- /* enable VL1 layer as default */
kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE);
kmb_set_bitmask_lcd(dev->dev_private, LCD_CONTROL, LCD_CTRL_ENABLE);
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, val);
#endif
/* TBD */
/* set clocks here */
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index d987529..26d004c 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -57,8 +57,6 @@ static irqreturn_t kmb_isr(int irq, void *arg);
static struct clk *clk_lcd;
static struct clk *clk_mipi;
-static struct clk *clk_msscam;
-static struct clk *clk_pll0out0;
static struct clk *clk_mipi_ecfg;
static struct clk *clk_mipi_cfg;
@@ -79,12 +77,6 @@ int kmb_display_clk_enable(void)
DRM_ERROR("Failed to enable MIPI clock: %d\n", ret);
return ret;
}
-/* ret = clk_prepare_enable(clk_msscam);
- if (ret) {
- DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret);
- return ret;
- }
- */
ret = clk_prepare_enable(clk_mipi_ecfg);
if (ret) {
@@ -107,8 +99,6 @@ static int kmb_display_clk_disable(void)
clk_disable_unprepare(clk_lcd);
if (clk_mipi)
clk_disable_unprepare(clk_mipi);
- if (clk_msscam)
- clk_disable_unprepare(clk_msscam);
if (clk_mipi_ecfg)
clk_disable_unprepare(clk_mipi_ecfg);
if (clk_mipi_cfg)
@@ -200,14 +190,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
DRM_ERROR("clk_get() failed clk_mipi\n");
goto setup_fail;
}
- clk_pll0out0 = clk_get(>dev, "clk_pll0_out0");
- if (IS_ERR(clk_pll0out0))
- DRM_ERROR("clk_get() failed clk_pll0_out0\n");
-
- if (clk_pll0out0)
- DRM_INFO("Get clk_pll0out0 = %ld\n",
- clk_get_rate(clk_pll0out0));
-
clk_mipi_ecfg = clk_get(>dev, "clk_mipi_ecfg");
if (IS_ERR(clk_mipi_ecfg)) {
DRM_ERROR("clk_get() failed clk_mipi_ecfg\n");
@@ -413,6 +395,9 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev)
break;
}
}
+
+ /* clear all interrupts */
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0);
return IRQ_HANDLED;
}
--
2.7.4
___
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[PATCH 54/59] drm/kmb: Initialize uninitialized variables
general cleaning
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 977fcb8..8a12d6d 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -330,7 +330,7 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct
drm_device *drm,
struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev)
{
- struct drm_bridge *bridge;
+ struct drm_bridge *bridge = NULL;
#ifndef FCCTEST
struct device_node *encoder_node;
#endif
@@ -838,7 +838,7 @@ static void mipi_tx_hs_tp_gen(struct kmb_drm_private
*dev_p, int vc,
static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,
struct mipi_ctrl_cfg *ctrl_cfg)
{
- u32 ret;
+ u32 ret = 0;
u8 active_vchannels = 0;
u8 frame_id, sect;
u32 bits_per_pclk = 0;
--
2.7.4
___
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[PATCH 42/59] drm/kmb: Update LCD programming to match MIPI
Mipi input expects the memory layout to be unpacked with 8 bits per
pixel in RGB (BRG) order. If the LCD is not configured properly,
corrupted output results, changed dma_unpacked to 0 in mipi FG.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 6 +++---
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
drivers/gpu/drm/kmb/kmb_dsi.c | 27 +--
drivers/gpu/drm/kmb/kmb_dsi.h | 1 +
drivers/gpu/drm/kmb/kmb_plane.c | 37 +++--
drivers/gpu/drm/kmb/kmb_regs.h | 1 +
6 files changed, 50 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index f8b4fde..d9f6199 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -105,16 +105,16 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_dsi_hw_init(dev);
#ifdef LCD_TEST
// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
- vm.vfront_porch = 0;
+ vm.vfront_porch = 2;
// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
- vm.vback_porch = 0;
+ vm.vback_porch = 2;
// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
vm.vsync_len = 1;
//vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
vm.hfront_porch = 0;
vm.hback_porch = 0;
//vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
- vm.hsync_len = 1;
+ vm.hsync_len = 7;
// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index c376944..b194139 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -50,6 +50,7 @@ struct kmb_drm_private {
spinlock_t irq_lock;
int irq_lcd;
int irq_mipi;
+ dma_addr_t fb_addr;
};
static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index f06fd92..3b3bb0a 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -45,6 +45,7 @@
static int hw_initialized;
#define IMAGE_PATH "/home/root/1280x720.pnm"
//#define MIPI_TX_TEST_PATTERN_GENERATION
+//#define MIPI_DMA
//#define RTL_TEST
//#define IMG_WIDTH_PX 640
//#define IMG_HEIGHT_LINES 10
@@ -53,6 +54,7 @@ static int hw_initialized;
/*MIPI TX CFG*/
//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782
+//#define MIPI_TX_LANE_DATA_RATE_MBPS 800
#define MIPI_TX_LANE_DATA_RATE_MBPS 891
//#define MIPI_TX_LANE_DATA_RATE_MBPS 80
#define MIPI_TX_REF_CLK_KHZ 24000
@@ -100,14 +102,14 @@ static struct mipi_dsi_device *dsi_device;
* these will eventually go to the device tree sections,
* and can be used as a refernce later for device tree additions
*/
-//#define RES_1920x1080
+#define RES_1920x1080
#ifdef RES_1920x1080
#define IMG_HEIGHT_LINES 1080
#define IMG_WIDTH_PX 1920
#define MIPI_TX_ACTIVE_LANES 4
#endif
-#define RES_1280x720
+//#define RES_1280x720
#ifdef RES_1280x720
#define IMG_HEIGHT_LINES 720
#define IMG_WIDTH_PX 1280
@@ -117,9 +119,9 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
.width_pixels = IMG_WIDTH_PX,
.height_lines = IMG_HEIGHT_LINES,
.data_type = DSI_LP_DT_PPS_RGB888_24B,
- //.data_mode = MIPI_DATA_MODE1,
- .data_mode = MIPI_DATA_MODE0,
- .dma_packed = 1
+ .data_mode = MIPI_DATA_MODE1,
+// .data_mode = MIPI_DATA_MODE0,
+ .dma_packed = 0
};
#ifdef RES_1920x1080
@@ -564,12 +566,15 @@ static u32 mipi_tx_fg_section_cfg_regs(struct
kmb_drm_private *dev_p,
<< MIPI_TX_SECT_VC_SHIFT); /* bits [23:22] */
/* data mode */
cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK)
- << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */
- cfg |= MIPI_TX_SECT_DMA_PACKED;
- DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x\n",
-__func__, __LINE__, ctrl_no, frame_id, section, cfg);
+ << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25]*/
+ if (ph_cfg->dma_packed)
+ cfg |= MIPI_TX_SECT_DMA_PACKED;
+ DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n",
+ __func__, __LINE__, ctrl_no, frame_id, section, cfg,
+ ph_cfg->dma_packed);
kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id,
- section)), cfg);
+ section)), cfg);
+
/*unpacked bytes */
/*there are 4 frame generators and each fg has 4 sections
*there are 2 registers for unpacked bytes -
@@ -621,6 +626,7 @@ static u32
[PATCH 32/59] drm/kmb: Revert dsi_host back to a static variable
From: Edmund Dea
revert dsi_host to static and instead add dsi_host_unregister.
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 6 +++---
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
drivers/gpu/drm/kmb/kmb_dsi.c | 9 +++--
drivers/gpu/drm/kmb/kmb_dsi.h | 1 +
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index f520ca9..0588bd0 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -398,7 +398,7 @@ static void kmb_drm_unload(struct device *dev)
dev_set_drvdata(dev, NULL);
/* Unregister DSI host */
- mipi_dsi_host_unregister(dsi_host);
+ dsi_host_unregister();
}
static int kmb_probe(struct platform_device *pdev)
@@ -434,7 +434,7 @@ static int kmb_probe(struct platform_device *pdev)
drm->dev_private = lcd;
kmb_setup_mode_config(drm);
- dev_set_drvdata(dev, drm);
+ dev_set_drvdata(dev, drm);
/* Load driver */
ret = kmb_load(drm, 0);
@@ -475,7 +475,7 @@ static int kmb_probe(struct platform_device *pdev)
drm_mode_config_cleanup(drm);
dev_set_drvdata(dev, NULL);
drm_dev_put(drm);
- mipi_dsi_host_unregister(dsi_host);
+ dsi_host_unregister();
return ret;
}
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index c87e608..6c1d687 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -31,7 +31,6 @@
#define KMB_MAX_WIDTH 16384 /*max width in pixels */
#define KMB_MAX_HEIGHT 16384 /*max height in pixels */
-extern struct mipi_dsi_host *dsi_host;
struct kmb_drm_private {
struct drm_device drm;
void __iomem*lcd_mmio;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 4b5adc7c..af04eb9 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -79,7 +79,7 @@
#define PLL_M_MAX 623
#define PLL_FVCO_MAX 1250
-struct mipi_dsi_host *dsi_host;
+static struct mipi_dsi_host *dsi_host;
static struct mipi_dsi_device *dsi_device;
/*
@@ -357,8 +357,13 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device
*dev)
return bridge;
}
+void dsi_host_unregister(void)
+{
+ mipi_dsi_host_unregister(dsi_host);
+}
+
u32 mipi_get_datatype_params(u32 data_type, u32 data_mode,
-struct mipi_data_type_params *params)
+ struct mipi_data_type_params *params)
{
struct mipi_data_type_params data_type_parameters;
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h
index cf234db..e85625b 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.h
+++ b/drivers/gpu/drm/kmb/kmb_dsi.h
@@ -333,6 +333,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device
*dev);
int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge);
void kmb_plane_destroy(struct drm_plane *plane);
void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p);
+void dsi_host_unregister(void);
#define to_kmb_connector(x) container_of(x, struct kmb_connector, base)
#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base)
--
2.7.4
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[PATCH 40/59] drm/kmb: Added LCD_TEST config
To run modetest without ADV driver, enable LCD_TEST and FCC_TEST.
Also made front porches 0, and some changes in the plane init.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++
drivers/gpu/drm/kmb/kmb_drv.c | 6 +--
drivers/gpu/drm/kmb/kmb_drv.h | 3 +-
drivers/gpu/drm/kmb/kmb_dsi.c | 85 +++--
drivers/gpu/drm/kmb/kmb_plane.c | 15 ++--
5 files changed, 78 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 01ad82e..9275f77 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -100,13 +100,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct videomode vm;
int vsync_start_offset;
int vsync_end_offset;
- unsigned int ctrl = 0;
#endif
/* initialize mipi */
kmb_dsi_hw_init(dev);
#ifdef LCD_TEST
- vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
- vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
+// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
+ vm.vfront_porch = 0;
+// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
+ vm.vback_porch = 0;
vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
//vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
vm.hfront_porch = 0;
@@ -149,12 +150,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10);
}
/* enable VL1 layer as default */
- ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
- ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
- | LCD_CTRL_OUTPUT_ENABLED;
- kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl);
-
kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE);
+ kmb_set_bitmask_lcd(dev->dev_private, LCD_CONTROL, LCD_CTRL_ENABLE);
#endif
/* TBD */
/* set clocks here */
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index e9dd879..e2d57ca 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -236,6 +236,8 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
#endif
/* Set MIPI clock to 24 Mhz*/
DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi));
+//#define MIPI_CLK
+#ifdef MIPI_CLK
ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK);
DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));
if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) {
@@ -243,6 +245,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
KMB_MIPI_DEFAULT_CLK);
goto setup_fail;
}
+#endif
DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n",
KMB_MIPI_DEFAULT_CLK/100, ret);
DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));
@@ -339,8 +342,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
DRM_ERROR("failed to initialize DSI\n");
goto setup_fail;
}
-
- DRM_INFO("%s : %d\n", __func__, __LINE__);
#ifdef WIP
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
if (ret < 0) {
@@ -355,7 +356,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
drm_crtc_cleanup(_p->crtc);
#endif
setup_fail:
- DRM_INFO("%s : %d\n", __func__, __LINE__);
of_reserved_mem_device_release(drm->dev);
return ret;
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index da1df5c..67ddf7a 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -28,7 +28,8 @@
#include "kmb_regs.h"
-/*#define FCCTEST*/
+#define FCCTEST
+#define LCD_TEST
#define KMB_MAX_WIDTH 1920 /*max width in pixels */
#define KMB_MAX_HEIGHT 1080 /*max height in pixels */
#define KMB_LCD_DEFAULT_CLK25000
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 5f7683e..91c6898 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -44,18 +44,19 @@
static int hw_initialized;
#define IMAGE_PATH "/home/root/1280x720.pnm"
-#define MIPI_TX_TEST_PATTERN_GENERATION
+//#define MIPI_TX_TEST_PATTERN_GENERATION
+//#define RTL_TEST
+//#define IMG_WIDTH_PX 640
+//#define IMG_HEIGHT_LINES 10
-#define IMG_HEIGHT_LINES 720
-#define IMG_WIDTH_PX 1280
#define LCD_BYTESPP 1
/*MIPI TX CFG*/
-#define MIPI_TX_ACTIVE_LANES 2
//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782
#define MIPI_TX_LANE_DATA_RATE_MBPS 891
//#define MIPI_TX_LANE_DATA_RATE_MBPS 80
#define MIPI_TX_REF_CLK_KHZ 24000
+//#define MIPI_TX_REF_CLK_KHZ 23809
#define MIPI_TX_CFG_CLK_KHZ 24000
/*DPHY Tx test
[PATCH 58/59] drm/kmb: Get System Clock from SCMI
System clock is different for A0 and B0 silicons, so get it directly
from clk_PLL0 through SCMI calls.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 11 +++
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
drivers/gpu/drm/kmb/kmb_dsi.c | 12 +---
3 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index bafc02a..74f57b3 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -59,6 +59,7 @@ static struct clk *clk_lcd;
static struct clk *clk_mipi;
static struct clk *clk_mipi_ecfg;
static struct clk *clk_mipi_cfg;
+static struct clk *clk_pll0;
struct drm_bridge *adv_bridge;
@@ -144,6 +145,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
#ifdef ICAM_LCD_QOS
int val = 0;
#endif
+ struct device_node *vpu_dev;
/* Map MIPI MMIO registers */
dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs");
@@ -210,6 +212,15 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
DRM_ERROR("clk_get() failed clk_mipi_cfg\n");
goto setup_fail;
}
+ vpu_dev = of_find_node_by_path("/soc/vpu-ipc");
+ DRM_INFO("vpu node = %pOF", vpu_dev);
+ clk_pll0 = of_clk_get_by_name(vpu_dev, "pll_0_out_0");
+ if (IS_ERR(clk_pll0)) {
+ DRM_ERROR("clk_get() failed clk_pll0 ");
+ goto setup_fail;
+ }
+ dev_p->sys_clk_mhz = clk_get_rate(clk_pll0)/100;
+ DRM_INFO("system clk = %d Mhz", dev_p->sys_clk_mhz);
#ifdef LCD_TEST
/* Set LCD clock to 200 Mhz */
DRM_DEBUG("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd));
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index a066aba..35872a5 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -58,6 +58,7 @@ struct kmb_drm_private {
spinlock_t irq_lock;
int irq_lcd;
int irq_mipi;
+ int sys_clk_mhz;
dma_addr_t fb_addr;
};
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index ec974da..81678a3 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -611,20 +611,10 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private
*dev_p, u8 frame_gen,
u32 ppl_llp_ratio;
u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset;
-#ifdef GET_SYS_CLK
- /* Get system clock for blanking period cnfigurations */
- sc = get_clock_frequency(CPR_CLK_SYSTEM, );
- if (sc)
- return sc;
-
- /* Convert to MHZ */
- sysclk /= 1000;
-#else
/* 500 Mhz system clock minus 50 to account for the difference in
* MIPI clock speed in RTL tests
*/
- sysclk = KMB_SYS_CLK_MHZ - 50;
-#endif
+ sysclk = dev_p->sys_clk_mhz - 50;
/* PPL-Pixel Packing Layer, LLP-Low Level Protocol
* Frame genartor timing parameters are clocked on the system clock,
--
2.7.4
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[PATCH 29/59] drm/kmb: Defer Probe
Register DSI host first and then defer probe until ADV bridge is
initialized.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 144 ++
drivers/gpu/drm/kmb/kmb_dsi.c | 46 --
drivers/gpu/drm/kmb/kmb_dsi.h | 3 +-
3 files changed, 89 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index b4e1e50..f1bf258 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -56,6 +56,8 @@ static irqreturn_t kmb_isr(int irq, void *arg);
static struct clk *clk_lcd;
static struct clk *clk_mipi;
+static int probe_deferred;
+
static int kmb_display_clk_enable(void)
{
clk_prepare_enable(clk_lcd);
@@ -76,12 +78,11 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
struct platform_device *pdev = to_platform_device(drm->dev);
- struct drm_bridge *bridge;
+/* struct drm_bridge *bridge;*/
/*struct resource *res;*/
/*u32 version;*/
- int irq_lcd, irq_mipi;
int ret;
- struct device_node *encoder_node;
+/* struct device_node *encoder_node;*/
/* TBD - not sure if clock_get needs to be called here */
/*
@@ -93,9 +94,10 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
* TBD call this in the future when device tree is ready,
* use hardcoded value for now
*/
- /*res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-*dev_p->lcd_mmio = devm_ioremap_resource(drm->dev, res);
-*
+ /*
+* res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+* dev_p->lcd_mmio = devm_ioremap_resource(drm->dev, res);
+
*if (IS_ERR(dev_p->lcd_mmio)) {
* DRM_ERROR("failed to map control registers area\n");
* ret = PTR_ERR(dev_p->lcd_mmio);
@@ -103,7 +105,10 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
* return ret;
*}
*/
-/* LCD mmio */
+ /* LCD mmio */
+ if (!probe_deferred) {
+ probe_deferred = 1;
+
if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) {
DRM_ERROR("failed to reserve LCD registers\n");
return -ENOMEM;
@@ -113,7 +118,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
DRM_ERROR("failed to map LCD registers\n");
return -ENOMEM;
}
-
/* Mipi mmio */
if (!request_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE, "kmb-mipi")) {
DRM_ERROR("failed to reserve MIPI registers\n");
@@ -126,35 +130,16 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
iounmap(dev_p->lcd_mmio);
return -ENOMEM;
}
-
/*this is only for MIPI_TX_MSS_LCD_MIPI_CFG register */
- dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR,
+ if (!dev_p->msscam_mmio) {
+ dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR,
MSS_CAM_MMIO_SIZE);
+ }
/* register irqs here - section 17.3 in databook
* lists LCD at 79 and 82 for MIPI under MSS CPU -
* firmware has to redirect it to A53
*/
- irq_lcd = platform_get_irq_byname(pdev, "irq_lcd");
- if (irq_lcd < 0) {
- DRM_ERROR("irq_lcd not found");
- return irq_lcd;
- }
- pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd);
- ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p);
- dev_p->irq_lcd = irq_lcd;
-
- irq_mipi = platform_get_irq_byname(pdev, "irq_mipi");
- if (irq_mipi < 0) {
- DRM_ERROR("irq_mipi not found");
- return irq_mipi;
- }
- pr_info("irq_mipi platform_get_irq = %d\n", irq_mipi);
- ret = request_irq(irq_mipi, kmb_isr, IRQF_SHARED, "irq_mipi", dev_p);
- dev_p->irq_mipi = irq_mipi;
-
-
-
/*TBD read and check for correct product version here */
/* Get the optional framebuffer memory resource */
@@ -169,52 +154,35 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
goto setup_fail;
}
- /* find ADV7535 node and initialize it */
- encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0);
- if (!encoder_node) {
- DRM_ERROR("failed to get bridge info from DT\n");
- ret = -EPROBE_DEFER;
- goto setup_fail;
- }
-
- /* Locate drm bridge from the hdmi encoder DT node */
- bridge = of_drm_find_bridge(encoder_node);
- if (!bridge) {
- DRM_ERROR("failed to get bridge driver from DT\n");
- ret = -EPROBE_DEFER;
- goto setup_fail;
- }
-
- of_node_put(encoder_node);
-
- ret =
[PATCH 18/59] drm/kmb: Part8 of Mipi Tx Initialization
This initializes the interrupts for DSI. This is the final part of mipi
DSI initialization.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 1 +
drivers/gpu/drm/kmb/kmb_drv.h | 30 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 46
drivers/gpu/drm/kmb/kmb_dsi.h | 13 +++
drivers/gpu/drm/kmb/kmb_regs.h | 81 ++
5 files changed, 163 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 0b99309..8945199 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -77,6 +77,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
if (ret && ret != -ENODEV)
return ret;
+ spin_lock_init(>irq_lock);
ret = kmb_setup_crtc(drm);
if (ret < 0) {
DRM_ERROR("failed to create crtc\n");
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 434be1a..0a38d63 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -32,14 +32,15 @@
#define KMB_MAX_HEIGHT 16384 /*max height in pixels */
struct kmb_drm_private {
- struct drm_device drm;
- void __iomem *mmio;
- unsigned char n_layers;
- struct clk *clk;
- struct drm_fbdev_cma *fbdev;
- struct drm_crtc crtc;
- struct kmb_plane *plane;
- struct drm_atomic_state *state;
+ struct drm_device drm;
+ void __iomem*mmio;
+ unsigned char n_layers;
+ struct clk *clk;
+ struct drm_fbdev_cma*fbdev;
+ struct drm_crtc crtc;
+ struct kmb_plane*plane;
+ struct drm_atomic_state *state;
+ spinlock_t irq_lock;
};
static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
@@ -131,6 +132,19 @@ static inline void kmb_clr_bit_mipi(unsigned int reg, u32
offset)
kmb_write_mipi(reg, reg_val & (~(1 << offset)));
}
+static inline void kmb_set_bitmask_mipi(unsigned int reg, u32 mask)
+{
+ u32 reg_val = kmb_read_mipi(reg);
+
+ kmb_write_mipi(reg, (reg_val | mask));
+}
+
+static inline void kmb_clr_bitmask_mipi(unsigned int reg, u32 mask)
+{
+ u32 reg_val = kmb_read_mipi(reg);
+
+ kmb_write_mipi(reg, (reg_val & (~mask)));
+}
int kmb_setup_crtc(struct drm_device *dev);
void kmb_set_scanout(struct kmb_drm_private *lcd);
#endif /* __KMB_DRV_H__ */
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 51bec35..898b54c 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include
#include "kmb_drv.h"
#include "kmb_regs.h"
@@ -208,6 +209,11 @@ static mipi_hs_freq_range_cfg
{.default_bit_rate_mbps = 2500, .hsfreqrange_code = 0x49}
};
+union mipi_irq_cfg int_cfg = {
+ .irq_cfg.frame_done = 1,
+ .irq_cfg.ctrl_error = 1,
+};
+
static enum drm_mode_status
kmb_dsi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -1194,6 +1200,43 @@ static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg)
return 0;
}
+static void mipi_tx_init_irqs(union mipi_irq_cfg *cfg,
+ struct kmb_drm_private *dev_priv,
+ struct mipi_tx_ctrl_cfg *tx_ctrl_cfg)
+{
+ unsigned long irqflags;
+ uint8_t vc;
+
+ /* clear all interrupts first */
+ /*local interrupts */
+ SET_MIPI_TX_HS_IRQ_CLEAR(MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL);
+ /*global interrupts */
+ SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_HS_IRQ);
+ SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ);
+ SET_MIPI_CTRL_IRQ_CLEAR1(MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ);
+
+ /*enable interrupts */
+ spin_lock_irqsave(_priv->irq_lock, irqflags);
+ for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) {
+ if (tx_ctrl_cfg->frames[vc] == NULL)
+ continue;
+ /*enable FRAME_DONE interrupt if VC is configured */
+ SET_HS_IRQ_ENABLE(MIPI_CTRL6,
+ MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc);
+ break; /*only one vc for LCD interface */
+ }
+
+ /*enable user enabled interrupts */
+ if (cfg->irq_cfg.dphy_error)
+ SET_MIPI_CTRL_IRQ_ENABLE0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ);
+ if (cfg->irq_cfg.line_compare)
+ SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_LINE_COMPARE);
+ if (cfg->irq_cfg.ctrl_error)
+ SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR);
+
+ spin_unlock_irqrestore(_priv->irq_lock, irqflags);
+}
+
void kmb_dsi_init(struct drm_device *dev)
{
struct kmb_dsi *kmb_dsi;
@@ -1239,4 +1282,7 @@ void
[PATCH 41/59] drm/kmb: Changes for LCD to Mipi
Also free dsi resources on driver unload. System clock frequency change
for llp ratio calculation.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 21 ---
drivers/gpu/drm/kmb/kmb_drv.c | 6 +-
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
drivers/gpu/drm/kmb/kmb_dsi.c | 135 +++-
drivers/gpu/drm/kmb/kmb_dsi.h | 2 +-
drivers/gpu/drm/kmb/kmb_plane.c | 24 +++
drivers/gpu/drm/kmb/kmb_regs.h | 2 +
7 files changed, 68 insertions(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 9275f77..f8b4fde 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -108,11 +108,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
vm.vfront_porch = 0;
// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
vm.vback_porch = 0;
- vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
+// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
+ vm.vsync_len = 1;
//vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
vm.hfront_porch = 0;
- vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
- vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
+ vm.hback_porch = 0;
+ //vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
+ vm.hsync_len = 1;
+// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
@@ -124,13 +127,13 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
vm.hback_porch, vm.hfront_porch, vm.hsync_len);
kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT,
m->crtc_vdisplay - 1);
- kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch - 1);
- kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch - 1);
+ kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch);
+ kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch);
kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
kmb_write_lcd(dev->dev_private, LCD_H_ACTIVEWIDTH,
m->crtc_hdisplay - 1);
- kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch - 1);
- kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch - 1);
+ kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch);
+ kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch);
kmb_write_lcd(dev->dev_private, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
/*this is hardcoded as 0 in the Myriadx code */
kmb_write_lcd(dev->dev_private, LCD_VSYNC_START, 0);
@@ -140,9 +143,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private,
LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
kmb_write_lcd(dev->dev_private,
- LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1);
+ LCD_V_BACKPORCH_EVEN, vm.vback_porch);
kmb_write_lcd(dev->dev_private,
- LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
+ LCD_V_FRONTPORCH_EVEN, vm.vfront_porch);
kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT_EVEN,
m->crtc_vdisplay - 1);
/*this is hardcoded as 10 in the Myriadx code*/
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index e2d57ca..3b4b7a1 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -236,7 +236,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
#endif
/* Set MIPI clock to 24 Mhz*/
DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi));
-//#define MIPI_CLK
+#define MIPI_CLK
#ifdef MIPI_CLK
ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK);
DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));
@@ -516,7 +516,7 @@ static void kmb_drm_unload(struct device *dev)
dev_set_drvdata(dev, NULL);
/* Unregister DSI host */
- dsi_host_unregister();
+ kmb_dsi_host_unregister();
}
static int kmb_probe(struct platform_device *pdev)
@@ -587,7 +587,7 @@ static int kmb_probe(struct platform_device *pdev)
drm_mode_config_cleanup(drm);
dev_set_drvdata(dev, NULL);
drm_dev_put(drm);
- dsi_host_unregister();
+ kmb_dsi_host_unregister();
return ret;
}
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 67ddf7a..c376944 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -35,6 +35,7 @@
#define KMB_LCD_DEFAULT_CLK25000
#define
[PATCH 14/59] drm/kmb: Correct address offsets for mipi registers
Mipi HS registers start at an additional offset of 0x400 which needs to be added at the register macro definition and not at the read/write function level. v2: replaced calculations with macro to make code simpler Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_dsi.c | 16 +++--- drivers/gpu/drm/kmb/kmb_regs.h | 116 - 2 files changed, 75 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 886a8ac..adcfe81 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -443,20 +443,20 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ - offset = (frame_gen % 2) * 16; - reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen); + offset = (frame_gen % 2)*16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width); - /*v backporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen); + /*v backporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch); - /*v frontporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen); + /*v frontporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch); - /*v active - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen); + /*v active - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active); /*hsyc width */ diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 9a5f371..4d6cf3d 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -395,10 +395,10 @@ *MIPI controller control register defines ***i/ #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) -#define MIPI_CTRL_HS_BASE_ADDR (0x400) +#define HS_OFFSET(M) ((M + 1) * 0x400) #define MIPI_TX_HS_CTRL(0x0) -#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M)) +#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) #define HS_CTRL_EN (1 << 0) #define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/ #define TX_SOURCE(1 << 3) /*1:LCD, 0:DMA*/ @@ -411,7 +411,7 @@ #define HSCLKIDLE_CNT(1 << 24) #define MIPI_TX_HS_SYNC_CFG(0x8) #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ - + (0x400*M)) + + HS_OFFSET(M)) #define LINE_SYNC_PKT_ENABLE (1 << 0) #define FRAME_COUNTER_ACTIVE (1 << 1) #define LINE_COUNTER_ACTIVE (1 << 2) @@ -428,75 +428,93 @@ #define FRAME_GEN_EN(f) ((f) << 23) #define HACT_WAIT_STOP(f)((f) << 28) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) -#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ - (0x400*M) + (0x2C*N) + (8*O)) -#define MIPI_TX_SECT_WC_MASK (0x) -#defineMIPI_TX_SECT_VC_MASK (3) -#define MIPI_TX_SECT_VC_SHIFT(22) -#define MIPI_TX_SECT_DT_MASK (0x3f) -#define MIPI_TX_SECT_DT_SHIFT(16) -#define MIPI_TX_SECT_DM_MASK (3) -#define MIPI_TX_SECT_DM_SHIFT(24) -#define MIPI_TX_SECT_DMA_PACKED (1<<26) +#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O)(MIPI_TX0_HS_FG0_SECT0_PH + \ + HS_OFFSET(M) + (0x2C*N) + (8*O)) +#define MIPI_TX_SECT_WC_MASK (0x) +#define MIPI_TX_SECT_VC_MASK (3) +#define MIPI_TX_SECT_VC_SHIFT(22) +#define MIPI_TX_SECT_DT_MASK (0x3f) +#define MIPI_TX_SECT_DT_SHIFT(16) +#define MIPI_TX_SECT_DM_MASK (3) +#define
[PATCH 28/59] drm/kmb: Changed MMIO size
Also added debug messages
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 19 +--
drivers/gpu/drm/kmb/kmb_regs.h | 6 +++---
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index b1cc8ad..b4e1e50 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -49,6 +49,7 @@
#include "kmb_plane.h"
#include "kmb_dsi.h"
+#define DEBUG
/*IRQ handler*/
static irqreturn_t kmb_isr(int irq, void *arg);
@@ -331,18 +332,22 @@ static int kmb_drm_bind(struct device *dev)
struct kmb_drm_private *lcd;
int ret;
+ DRM_DEBUG("kmb_bind : ENTER\n");
drm = drm_dev_alloc(_driver, dev);
if (IS_ERR(drm))
return PTR_ERR(drm);
+ DRM_DEBUG("kmb_bind : after alloc drm\n");
lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL);
if (!lcd)
return -ENOMEM;
+ DRM_DEBUG("kmb_bind : after alloc lcd\n");
drm->dev_private = lcd;
dev_set_drvdata(dev, drm);
kmb_setup_mode_config(drm);
+ DRM_DEBUG("kmb_bind : after kmb_setup_mode_config\n");
ret = kmb_load(drm, 0);
if (ret)
goto err_free;
@@ -455,17 +460,27 @@ static int kmb_probe(struct platform_device *pdev)
{
struct device_node *port;
struct component_match *match = NULL;
+ int ret;
/* there is only one output port inside each device, find it */
+ DRM_DEBUG("%s : ENTER", __func__);
+
port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
+ DRM_DEBUG("%s : port = 0x%pOF\n", __func__, port);
if (!port)
return -ENODEV;
+ DRM_DEBUG("%s : after get_remote", __func__);
+ DRM_DEBUG("Adding component %pOF\n", port);
drm_of_component_match_add(>dev, , compare_dev, port);
+ DRM_DEBUG("%s : after get_match", __func__);
of_node_put(port);
- return component_master_add_with_match(>dev, _master_ops,
- match);
+ret = component_master_add_with_match(>dev, _master_ops,
+ match);
+
+ DRM_DEBUG("%s : EXIT ret=%d\n", __func__, ret);
+ return ret;
}
static int kmb_remove(struct platform_device *pdev)
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index bb80bc5..f8a7abf 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -33,9 +33,9 @@
/*from Data Book section 12.11.6.1 page 4972 */
#define LCD_BASE_ADDR (0x2093)
#define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x1)
-#define LCD_MMIO_SIZE (0x1)
-#define MIPI_MMIO_SIZE (0x1)
-#define MSS_CAM_MMIO_SIZE (0x1)
+#define LCD_MMIO_SIZE (0x3000)
+#define MIPI_MMIO_SIZE (0x4000)
+#define MSS_CAM_MMIO_SIZE (0x10)
/***
*LCD controller control register defines
--
2.7.4
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[PATCH 49/59] drm/kmb: Disable ping pong mode
Disable ping pong mode otherwise video corruption results,
use continuous mode and also fetch the dma
addresses before disabling dma. For now, only initialize the dma and
planes once and for next plane updates only update the addresses for
dma.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 303
drivers/gpu/drm/kmb/kmb_plane.h | 8 ++
2 files changed, 159 insertions(+), 152 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 9f9ae57..35dece3 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -103,11 +103,12 @@ static const u32 kmb_formats_v[] = {
#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR)
const uint32_t layer_irqs[] = {
- LCD_INT_VL0,
- LCD_INT_VL1,
- LCD_INT_GL0,
- LCD_INT_GL1
- };
+ LCD_INT_VL0,
+ LCD_INT_VL1,
+ LCD_INT_GL0,
+ LCD_INT_GL1
+};
+
/*Conversion (yuv->rgb) matrix from myriadx */
static const u32 csc_coef_lcd[] = {
1024, 0, 1436,
@@ -116,7 +117,6 @@ static const u32 csc_coef_lcd[] = {
-179, 125, -226
};
-
static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
{
int i;
@@ -134,7 +134,6 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
struct drm_framebuffer *fb;
int ret;
-
fb = state->fb;
if (!fb || !state->crtc)
@@ -150,7 +149,7 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
}
static void kmb_plane_atomic_disable(struct drm_plane *plane,
- struct drm_plane_state *state)
+struct drm_plane_state *state)
{
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
int ctrl = 0;
@@ -176,14 +175,13 @@ static void kmb_plane_atomic_disable(struct drm_plane
*plane,
}
kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id),
- LCD_DMA_LAYER_ENABLE);
+ LCD_DMA_LAYER_ENABLE);
kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl);
DRM_INFO("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n",
- __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL),
- kmb_read_lcd(dev_p, LCD_INT_ENABLE));
+__func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL),
+kmb_read_lcd(dev_p, LCD_INT_ENABLE));
}
-
unsigned int set_pixel_format(u32 format)
{
unsigned int val = 0;
@@ -218,8 +216,8 @@ unsigned int set_pixel_format(u32 format)
val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE
| LCD_LAYER_CRCB_ORDER;
break;
- /* packed formats */
- /* looks hw requires B & G to be swapped when RGB */
+ /* packed formats */
+ /* looks hw requires B & G to be swapped when RGB */
case DRM_FORMAT_RGB332:
val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER;
break;
@@ -283,7 +281,7 @@ unsigned int set_bits_per_pixel(const struct
drm_format_info *format)
return val;
}
- bpp += 8*format->cpp[0];
+ bpp += 8 * format->cpp[0];
switch (bpp) {
case 8:
@@ -330,7 +328,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
#ifdef LCD_TEST
struct drm_framebuffer *fb;
struct kmb_drm_private *dev_p;
- dma_addr_t addr;
unsigned int width;
unsigned int height;
unsigned int dma_len;
@@ -340,6 +337,9 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
unsigned int src_w, src_h, crtc_x, crtc_y;
unsigned char plane_id;
int num_planes;
+ /*plane initialization status */
+ static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 };
+ static dma_addr_t addr[MAX_SUB_PLANES] = { 0, 0, 0 };
if (!plane || !plane->state || !state)
return;
@@ -352,8 +352,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
kmb_plane = to_kmb_plane(plane);
plane_id = kmb_plane->id;
-
-
dev_p = plane->dev->dev_private;
src_w = (plane->state->src_w >> 16);
@@ -361,146 +359,145 @@ static void kmb_plane_atomic_update(struct drm_plane
*plane,
crtc_x = plane->state->crtc_x;
crtc_y = plane->state->crtc_y;
- DRM_INFO("src_w=%d src_h=%d\n", src_w, src_h);
- kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1);
- kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1);
- kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x);
- kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y);
-
- val =
[PATCH 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi
From: Edmund Dea
Made it conditionally compiled.
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_drv.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 4eb472b..1aedcf8 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -143,7 +143,10 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
struct platform_device *pdev = to_platform_device(drm->dev);
+#ifdef WIP
/*u32 version;*/
+ int irq_lcd, irq_mipi;
+#endif
int ret = 0;
unsigned long clk;
@@ -297,9 +300,9 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
pr_info("irq_mipi platform_get_irq = %d\n", irq_mipi);
ret = request_irq(irq_mipi, kmb_isr, IRQF_SHARED, "irq_mipi", dev_p);
dev_p->irq_mipi = irq_mipi;
-#endif
- /* TBD read and check for correct product version here */
+ /* TBD read and check for correct product version here */
+#endif
/* Get the optional framebuffer memory resource */
ret = of_reserved_mem_device_init(drm->dev);
if (ret && ret != -ENODEV)
--
2.7.4
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[PATCH 26/59] drm/kmb: rebase to newer kernel version
cleanup code
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 5 +++--
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index b0ab40b..1f0dcbe 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -301,8 +301,7 @@ DEFINE_DRM_GEM_CMA_FOPS(fops);
static struct drm_driver kmb_driver = {
.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
- DRIVER_MODESET |
- DRIVER_ATOMIC,
+ DRIVER_MODESET | DRIVER_ATOMIC,
.irq_handler = kmb_isr,
.irq_preinstall = kmb_irq_reset,
.irq_uninstall = kmb_irq_reset,
@@ -378,6 +377,8 @@ static int kmb_drm_bind(struct device *dev)
if (ret)
goto err_register;
+ drm_fbdev_generic_setup(drm, 32);
+
return 0;
err_register:
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 50efa8a..6c1d687 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -38,7 +38,6 @@ struct kmb_drm_private {
void __iomem*msscam_mmio;
unsigned char n_layers;
struct clk *clk;
- struct drm_fbdev_cma*fbdev;
struct drm_crtc crtc;
struct kmb_plane*plane;
struct drm_atomic_state *state;
--
2.7.4
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[PATCH 30/59] drm/kmb: call bridge init in the very beginning
of probe and return probe_defer early on, so that all the other
initializations can be done after adv driver is loaded successfully.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 81 ++--
drivers/gpu/drm/kmb/kmb_dsi.c | 144 ++
drivers/gpu/drm/kmb/kmb_dsi.h | 6 +-
3 files changed, 141 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index f1bf258..81af972 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -57,11 +57,24 @@ static struct clk *clk_lcd;
static struct clk *clk_mipi;
static int probe_deferred;
+struct drm_bridge *adv_bridge;
static int kmb_display_clk_enable(void)
{
- clk_prepare_enable(clk_lcd);
- clk_prepare_enable(clk_mipi);
+ int ret;
+
+ ret = clk_prepare_enable(clk_lcd);
+ if (ret) {
+ DRM_ERROR("Failed to enable LCD clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(clk_mipi);
+ if (ret) {
+ DRM_ERROR("Failed to enable MIPI clock: %d\n", ret);
+ return ret;
+ }
+ DRM_INFO("SUCCESS : enabled LCD MIPI clocks\n");
return 0;
}
@@ -106,8 +119,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
*}
*/
/* LCD mmio */
- if (!probe_deferred) {
- probe_deferred = 1;
+ probe_deferred = 1;
if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) {
DRM_ERROR("failed to reserve LCD registers\n");
@@ -140,9 +152,10 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
* lists LCD at 79 and 82 for MIPI under MSS CPU -
* firmware has to redirect it to A53
*/
-/*TBD read and check for correct product version here */
- /* Get the optional framebuffer memory resource */
+ /*TBD read and check for correct product version here */
+
+ /* Get the optional framebuffer memory resource */
ret = of_reserved_mem_device_init(drm->dev);
if (ret && ret != -ENODEV)
return ret;
@@ -154,8 +167,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
goto setup_fail;
}
-/* ret = kmb_dsi_init(drm, bridge);*/
- ret = kmb_dsi_init(drm);
+ ret = kmb_dsi_init(drm, adv_bridge);
if (ret == -EPROBE_DEFER) {
DRM_INFO("%s: wait for external bridge driver DT", __func__);
return -EPROBE_DEFER;
@@ -163,7 +175,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
DRM_ERROR("failed to initialize DSI\n");
goto setup_fail;
}
-}
/* enable display clocks*/
clk_lcd = clk_get(>dev, "clk_lcd");
if (!clk_lcd) {
@@ -177,10 +188,9 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
goto setup_fail;
}
DRM_INFO("%s : %d\n", __func__, __LINE__);
- kmb_display_clk_enable();
-
- DRM_INFO("%s : %d\n", __func__, __LINE__);
+ ret = kmb_display_clk_enable();
+ DRM_INFO("%s : %d clk enabling ret=%d\n", __func__, __LINE__, ret);
return 0;
drm_crtc_cleanup(_p->crtc);
@@ -287,7 +297,7 @@ static struct drm_driver kmb_driver = {
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
.gem_prime_mmap = drm_gem_cma_prime_mmap,
.fops = ,
- .name = "kmb",
+ .name = "kmb_display",
.desc = "KEEMBAY DISPLAY DRIVER ",
.date = "20190122",
.major = 1,
@@ -296,26 +306,27 @@ static struct drm_driver kmb_driver = {
static int kmb_drm_bind(struct device *dev)
{
- struct drm_device *drm;
+ struct drm_device *drm = NULL;
struct kmb_drm_private *lcd;
int ret;
- DRM_DEBUG("kmb_bind : ENTER\n");
+ DRM_DEBUG("%s : ENTER", __func__);
drm = drm_dev_alloc(_driver, dev);
if (IS_ERR(drm))
return PTR_ERR(drm);
- DRM_DEBUG("kmb_bind : after alloc drm\n");
+ DRM_DEBUG("%s : after alloc drm", __func__);
lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL);
if (!lcd)
return -ENOMEM;
- DRM_DEBUG("kmb_bind : after alloc lcd\n");
+ DRM_DEBUG("%s : after alloc lcd", __func__);
drm->dev_private = lcd;
- dev_set_drvdata(dev, drm);
kmb_setup_mode_config(drm);
- DRM_DEBUG("kmb_bind : after kmb_setup_mode_config\n");
+ dev_set_drvdata(dev, drm);
+
+ /* load the driver */
ret = kmb_load(drm, 0);
DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret);
if (ret == -EPROBE_DEFER) {
@@ -356,7 +367,6 @@ static int kmb_drm_bind(struct device *dev)
drm_kms_helper_poll_fini(drm);
err_vblank:
pm_runtime_disable(drm->dev);
-
[PATCH 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg.
From: Edmund Dea
Note that we enable clk_msscam but do not set clk_msscam. However, we do
enable and set clk_mipi_ecfg and clk_mipi_cfg.
Verify that LCD and MIPI clocks are set successfully.
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_drv.c | 112 +-
drivers/gpu/drm/kmb/kmb_drv.h | 2 +
2 files changed, 102 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 0588bd0..48c2b28 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -56,6 +56,9 @@ static irqreturn_t kmb_isr(int irq, void *arg);
static struct clk *clk_lcd;
static struct clk *clk_mipi;
+static struct clk *clk_msscam;
+static struct clk *clk_mipi_ecfg;
+static struct clk *clk_mipi_cfg;
struct drm_bridge *adv_bridge;
@@ -74,6 +77,24 @@ static int kmb_display_clk_enable(void)
DRM_ERROR("Failed to enable MIPI clock: %d\n", ret);
return ret;
}
+
+ ret = clk_prepare_enable(clk_msscam);
+ if (ret) {
+ DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(clk_mipi_ecfg);
+ if (ret) {
+ DRM_ERROR("Failed to enable MIPI_ECFG clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(clk_mipi_cfg);
+ if (ret) {
+ DRM_ERROR("Failed to enable MIPI_CFG clock: %d\n", ret);
+ return ret;
+ }
DRM_INFO("SUCCESS : enabled LCD MIPI clocks\n");
return 0;
}
@@ -84,6 +105,12 @@ static int kmb_display_clk_disable(void)
clk_disable_unprepare(clk_lcd);
if (clk_mipi)
clk_disable_unprepare(clk_mipi);
+ if (clk_msscam)
+ clk_disable_unprepare(clk_msscam);
+ if (clk_mipi_ecfg)
+ clk_disable_unprepare(clk_mipi_ecfg);
+ if (clk_mipi_cfg)
+ clk_disable_unprepare(clk_mipi_cfg);
return 0;
}
@@ -118,6 +145,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
struct platform_device *pdev = to_platform_device(drm->dev);
/*u32 version;*/
int ret = 0;
+ unsigned long clk;
/* Map LCD MMIO registers */
dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs");
@@ -128,7 +156,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
/* Map MIPI MMIO registers */
dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs");
-
if (IS_ERR(dev_p->mipi_mmio)) {
DRM_ERROR("failed to map MIPI registers\n");
iounmap(dev_p->lcd_mmio);
@@ -146,33 +173,94 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
return -ENOMEM;
}
- /* enable display clocks*/
+ /* Enable display clocks*/
clk_lcd = clk_get(>dev, "clk_lcd");
- if (!clk_lcd) {
+ if (IS_ERR(clk_lcd)) {
DRM_ERROR("clk_get() failed clk_lcd\n");
goto setup_fail;
}
- DRM_INFO("%s : %d\n", __func__, __LINE__);
clk_mipi = clk_get(>dev, "clk_mipi");
- if (!clk_mipi) {
+ if (IS_ERR(clk_mipi)) {
DRM_ERROR("clk_get() failed clk_mipi\n");
goto setup_fail;
}
- DRM_INFO("%s : %d\n", __func__, __LINE__);
+
+ clk_msscam = clk_get(>dev, "clk_msscam");
+ if (IS_ERR(clk_msscam)) {
+ DRM_ERROR("clk_get() failed clk_msscam\n");
+ goto setup_fail;
+ }
+
+ clk_mipi_ecfg = clk_get(>dev, "clk_mipi_ecfg");
+ if (IS_ERR(clk_mipi_ecfg)) {
+ DRM_ERROR("clk_get() failed clk_mipi_ecfg\n");
+ goto setup_fail;
+ }
+
+ clk_mipi_cfg = clk_get(>dev, "clk_mipi_cfg");
+ if (IS_ERR(clk_mipi_cfg)) {
+ DRM_ERROR("clk_get() failed clk_mipi_cfg\n");
+ goto setup_fail;
+ }
+
ret = kmb_display_clk_enable();
- /* set LCD clock to 200 Mhz*/
+ /* Set LCD clock to 200 Mhz*/
DRM_INFO("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd));
- ret = clk_set_rate(clk_lcd, 2);
- DRM_INFO("Setting LCD clock tp 200Mhz ret = %d\n", ret);
+ ret = clk_set_rate(clk_lcd, KMB_LCD_DEFAULT_CLK);
+ if (clk_get_rate(clk_lcd) != KMB_LCD_DEFAULT_CLK) {
+ DRM_ERROR("failed to set to clk_lcd to %d\n",
+ KMB_LCD_DEFAULT_CLK);
+ goto setup_fail;
+ }
+ DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n",
+ KMB_LCD_DEFAULT_CLK/100, ret);
DRM_INFO("Get clk_lcd after set = %ld\n", clk_get_rate(clk_lcd));
- /* set MIPI clock to 24 Mhz*/
+
+ /* Set MIPI clock to 24 Mhz*/
DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi));
- ret = clk_set_rate(clk_mipi, 2400);
-
[PATCH 52/59] drm/kmb: Cleaned up code
From: Edmund Dea
to remove compiler warnings and general clean up
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_crtc.c | 48 +-
drivers/gpu/drm/kmb/kmb_crtc.h |6 +-
drivers/gpu/drm/kmb/kmb_drv.c | 115 +++--
drivers/gpu/drm/kmb/kmb_drv.h | 107 ++--
drivers/gpu/drm/kmb/kmb_dsi.c | 1073 +--
drivers/gpu/drm/kmb/kmb_dsi.h | 84 ++-
drivers/gpu/drm/kmb/kmb_plane.c | 155 ++
drivers/gpu/drm/kmb/kmb_plane.h | 74 ++-
drivers/gpu/drm/kmb/kmb_regs.h | 29 +-
9 files changed, 898 insertions(+), 793 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 16f6c7f..c01977b 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -59,10 +59,10 @@ static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
/*set which interval to generate vertical interrupt */
kmb_write_lcd(dev->dev_private, LCD_VSTATUS_COMPARE,
- LCD_VSTATUS_COMPARE_VSYNC);
+ LCD_VSTATUS_COMPARE_VSYNC);
/* enable vertical interrupt */
kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE,
- LCD_INT_VERT_COMP);
+ LCD_INT_VERT_COMP);
return 0;
}
@@ -74,7 +74,7 @@ static void kmb_crtc_disable_vblank(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
/* disable vertical interrupt */
kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE,
- LCD_INT_VERT_COMP);
+ LCD_INT_VERT_COMP);
}
@@ -102,38 +102,38 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
/* initialize mipi */
kmb_dsi_hw_init(dev, m);
DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n",
- m->crtc_vsync_start - m->crtc_vdisplay,
- m->crtc_vtotal - m->crtc_vsync_end,
- m->crtc_vsync_end - m->crtc_vsync_start,
- m->crtc_hsync_start - m->crtc_hdisplay,
- m->crtc_htotal - m->crtc_hsync_end,
- m->crtc_hsync_end - m->crtc_hsync_start);
+m->crtc_vsync_start - m->crtc_vdisplay,
+m->crtc_vtotal - m->crtc_vsync_end,
+m->crtc_vsync_end - m->crtc_vsync_start,
+m->crtc_hsync_start - m->crtc_hdisplay,
+m->crtc_htotal - m->crtc_hsync_end,
+m->crtc_hsync_end - m->crtc_hsync_start);
val = kmb_read_lcd(dev->dev_private, LCD_INT_ENABLE);
kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, val);
kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0);
-// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
+// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
vm.vfront_porch = 2;
-// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
+// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
vm.vback_porch = 2;
-// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
+// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
vm.vsync_len = 1;
//vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
vm.hfront_porch = 0;
vm.hback_porch = 0;
//vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
vm.hsync_len = 7;
-// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
+// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
- DRM_INFO("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d
h-bp=%d h-fp=%d hysnc-l=%d\n",
- __func__, __LINE__, m->crtc_vdisplay,
- vm.vback_porch, vm.vfront_porch,
- vm.vsync_len, m->crtc_hdisplay,
- vm.hback_porch, vm.hfront_porch, vm.hsync_len);
+ DRM_DEBUG
+ ("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d
h-bp=%d h-fp=%d hysnc-l=%d",
+__func__, __LINE__, m->crtc_vdisplay, vm.vback_porch,
+vm.vfront_porch, vm.vsync_len, m->crtc_hdisplay, vm.hback_porch,
+vm.hfront_porch, vm.hsync_len);
kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT,
- m->crtc_vdisplay - 1);
+ m->crtc_vdisplay - 1);
kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch);
kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch);
kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
@@ -148,14 +148,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
if (m->flags == DRM_MODE_FLAG_INTERLACE) {
[PATCH 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START
Myriadx code has it set to these values.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index b2b50cc..053da17 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -120,6 +120,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch - 1);
kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch - 1);
kmb_write_lcd(dev->dev_private, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
+ /*this is hardcoded as 0 in the Myriadx code */
+ kmb_write_lcd(dev->dev_private, LCD_VSYNC_START, 0);
+ kmb_write_lcd(dev->dev_private, LCD_VSYNC_END, 0);
if (m->flags == DRM_MODE_FLAG_INTERLACE) {
kmb_write_lcd(dev->dev_private,
@@ -128,12 +131,11 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1);
kmb_write_lcd(dev->dev_private,
LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
- kmb_write_lcd(dev->dev_private,
- LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1);
- kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN,
- vsync_start_offset);
- kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN,
- vsync_end_offset);
+ kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT_EVEN,
+ m->crtc_vdisplay - 1);
+ /*this is hardcoded as 10 in the Myriadx code*/
+ kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, 10);
+ kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10);
}
/* enable VL1 layer as default */
ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
--
2.7.4
___
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[PATCH 25/59] drm/kmb: Display clock enable/disable
Get clock info from DT and enable it during initialization.
Also changed name of the driver to "kmb,display" to match other
entries in the DT.
v2: fixed error in clk_disable
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 42 --
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 0aa910b..b0ab40b 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -51,6 +52,25 @@
/*IRQ handler*/
static irqreturn_t kmb_isr(int irq, void *arg);
+static struct clk *clk_lcd;
+static struct clk *clk_mipi;
+
+static int kmb_display_clk_enable(void)
+{
+ clk_prepare_enable(clk_lcd);
+ clk_prepare_enable(clk_mipi);
+ return 0;
+}
+
+static int kmb_display_clk_disable(void)
+{
+ if (clk_lcd)
+ clk_disable_unprepare(clk_lcd);
+ if (clk_mipi)
+ clk_disable_unprepare(clk_mipi);
+ return 0;
+}
+
static int kmb_load(struct drm_device *drm, unsigned long flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
@@ -172,6 +192,19 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
goto setup_fail;
}
+ /* enable display clocks*/
+ clk_lcd = clk_get(>dev, "clk_lcd");
+ if (!clk_lcd) {
+ DRM_ERROR("clk_get() failed clk_lcd\n");
+ goto setup_fail;
+ }
+ clk_mipi = clk_get(>dev, "clk_mipi");
+ if (!clk_mipi) {
+ DRM_ERROR("clk_get() failed clk_mipi\n");
+ goto setup_fail;
+ }
+ kmb_display_clk_enable();
+
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
if (ret < 0) {
DRM_ERROR("failed to install IRQ handler\n");
@@ -397,6 +430,11 @@ static void kmb_drm_unbind(struct device *dev)
of_reserved_mem_device_release(drm->dev);
drm_mode_config_cleanup(drm);
+ /*release clks */
+ kmb_display_clk_disable();
+ clk_put(clk_lcd);
+ clk_put(clk_mipi);
+
drm_dev_put(drm);
drm->dev_private = NULL;
dev_set_drvdata(dev, NULL);
@@ -435,8 +473,8 @@ static int kmb_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id kmb_of_match[] = {
- {.compatible = "lcd"},
+static const struct of_device_id kmb_of_match[] = {
+ {.compatible = "kmb,display"},
{},
};
--
2.7.4
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[PATCH 09/59] drm/kmb: Part 1 of Mipi Tx Initialization
Mipi TX frame section configuration
This is the first part in the MIPI controller initialization.
Compute and set the right values in MIPI TX frame section configuration
registers like packet header(PH), unpacked bytes and line config.
v2: added more comments to clarify assumptions
v3: improved code readability as per code review
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 14 ++
drivers/gpu/drm/kmb/kmb_dsi.c | 330 +
drivers/gpu/drm/kmb/kmb_dsi.h | 232 +
drivers/gpu/drm/kmb/kmb_regs.h | 25
4 files changed, 601 insertions(+)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 637e9a2..46be8cb 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -62,6 +62,20 @@ static inline u32 kmb_read(struct kmb_drm_private *lcd,
unsigned int reg)
return readl(lcd->mmio + reg);
}
+static inline void kmb_write_bits(struct kmb_drm_private *lcd,
+ unsigned int reg, u32 offset, u32 num_bits,
+ u32 value)
+{
+ u32 reg_val = kmb_read(lcd, reg);
+ u32 mask = (1 << num_bits) - 1;
+
+ value &= mask;
+ mask <<= offset;
+ reg_val &= (~mask);
+ reg_val |= (value << offset);
+ writel(reg_val, lcd->mmio + reg);
+}
+
int kmb_setup_crtc(struct drm_device *dev);
void kmb_set_scanout(struct kmb_drm_private *lcd);
#endif /* __KMB_DRV_H__ */
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 5e2aff1..17e1383 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -30,11 +30,83 @@
#include
#include
#include
+#include
#include
#include
#include "kmb_drv.h"
+#include "kmb_regs.h"
#include "kmb_dsi.h"
+#define IMG_WIDTH_PX 1920
+#define IMG_HEIGHT_LINES 1080
+#define LCD_BYTESPP 1
+
+/*MIPI TX CFG*/
+#define MIPI_TX_ACTIVE_LANES4
+#define MIPI_TX_LANE_DATA_RATE_MBPS 888
+#define MIPI_TX_REF_CLK_KHZ 24000
+#define MIPI_TX_CFG_CLK_KHZ 24000
+
+/*
+ * These are added here only temporarily for testing,
+ * these will eventually go to the device tree sections,
+ * and can be used as a refernce later for device tree additions
+ */
+struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
+ .width_pixels = IMG_WIDTH_PX,
+ .height_lines = IMG_HEIGHT_LINES,
+ .data_type = DSI_LP_DT_PPS_RGB888_24B,
+ .data_mode = MIPI_DATA_MODE1,
+ .dma_packed = 0
+};
+
+struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
+ .sections[0] = _tx_frame0_sect_cfg,
+ .sections[1] = NULL,
+ .sections[2] = NULL,
+ .sections[3] = NULL,
+ .vsync_width = 5,
+ .v_backporch = 36,
+ .v_frontporch = 4,
+ .hsync_width = 44,
+ .h_backporch = 148,
+ .h_frontporch = 88
+};
+
+struct mipi_tx_dsi_cfg mipitx_dsi_cfg = {
+ .hfp_blank_en = 0,
+ .eotp_en = 0,
+ .lpm_last_vfp_line = 0,
+ .lpm_first_vsa_line = 0,
+ .sync_pulse_eventn = DSI_VIDEO_MODE_NO_BURST_EVENT,
+ .hfp_blanking = SEND_BLANK_PACKET,
+ .hbp_blanking = SEND_BLANK_PACKET,
+ .hsa_blanking = SEND_BLANK_PACKET,
+ .v_blanking = SEND_BLANK_PACKET,
+};
+
+struct mipi_ctrl_cfg mipi_tx_init_cfg = {
+ .index = MIPI_CTRL6,
+ .type = MIPI_DSI,
+ .dir = MIPI_TX,
+ .active_lanes = MIPI_TX_ACTIVE_LANES,
+ .lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS,
+ .ref_clk_khz = MIPI_TX_REF_CLK_KHZ,
+ .cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ,
+ .data_if = MIPI_IF_PARALLEL,
+ .tx_ctrl_cfg = {
+ .frames[0] = _frame0_cfg,
+ .frames[1] = NULL,
+ .frames[2] = NULL,
+ .frames[3] = NULL,
+ .tx_dsi_cfg = _dsi_cfg,
+ .line_sync_pkt_en = 0,
+ .line_counter_active = 0,
+ .frame_counter_active = 0,
+ }
+
+};
+
static enum drm_mode_status
kmb_dsi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -131,6 +203,261 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct
kmb_dsi *kmb_dsi)
return host;
}
+u32 mipi_get_datatype_params(u32 data_type, u32 data_mode,
+struct mipi_data_type_params *params)
+{
+ struct mipi_data_type_params data_type_parameters;
+
+ switch (data_type) {
+ case DSI_LP_DT_PPS_YCBCR420_12B:
+ data_type_parameters.size_constraint_pixels = 2;
+ data_type_parameters.size_constraint_bytes = 3;
+ switch (data_mode) {
+ /* case 0 not supported according to MDK */
+ case 1:
+ case 2:
+ case 3:
+
[PATCH 39/59] drm/kmb: Fixed driver unload
unmap MSSCAM registers
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 15 +++
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
drivers/gpu/drm/kmb/kmb_regs.h | 2 +-
3 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index b5c8711..e9dd879 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -179,17 +179,6 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
iounmap(dev_p->mipi_mmio);
return -ENOMEM;
}
-/*testing*/
- if (!request_mem_region(CPR_BASE_ADDR, 100, "cpr")) {
- DRM_ERROR("failed to reserve %s registers\n", "cpr");
- return -ENOMEM;
- }
- dev_p->cpr_mmio = ioremap_cache(CPR_BASE_ADDR, 0x100);
- if (!dev_p->cpr_mmio) {
- DRM_ERROR("failed to ioremap %s registers\n", "CPR");
- release_mem_region(CPR_BASE_ADDR, 100);
- return -ENOMEM;
- }
if (IS_ERR(dev_p->msscam_mmio)) {
DRM_ERROR("failed to map MSSCAM registers\n");
@@ -509,8 +498,10 @@ static void kmb_drm_unload(struct device *dev)
release_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE);
}
- if (dev_p->msscam_mmio)
+ if (dev_p->msscam_mmio) {
iounmap(dev_p->msscam_mmio);
+ release_mem_region(MSS_CAM_BASE_ADDR, MSS_CAM_MMIO_SIZE);
+ }
of_reserved_mem_device_release(drm->dev);
drm_mode_config_cleanup(drm);
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 58bb967..da1df5c 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -40,7 +40,6 @@ struct kmb_drm_private {
void __iomem*lcd_mmio;
void __iomem*mipi_mmio;
void __iomem*msscam_mmio;
- void __iomem*cpr_mmio;
unsigned char n_layers;
struct clk *clk;
struct drm_crtc crtc;
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index eb84320..255c44d 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -36,7 +36,7 @@
#define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x1)
#define LCD_MMIO_SIZE (0x3000)
#define MIPI_MMIO_SIZE (0x4000)
-#define MSS_CAM_MMIO_SIZE (0x10)
+#define MSS_CAM_MMIO_SIZE (0x30)
/***
*LCD controller control register defines
--
2.7.4
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[PATCH 31/59] drm/kmb: Cleanup probe functions
From: Edmund Dea
- Removed deprecated code blocks within probe functions
- In kmb_remove, unregister MIPI DSI host
- In kmb_probe, if kmb_load fails, then unregister MIPI DSI host
- Change kmb_dsi_host_bridge_init to return error codes using ERR_PTR
- Do clock intitialization earlier
- Rename kmb_drm_unbind to kmb_drm_unload.
- Get mmio info from device tree
Signed-off-by: Edmund Dea
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 336 +++---
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
drivers/gpu/drm/kmb/kmb_dsi.c | 85 ---
3 files changed, 218 insertions(+), 204 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 81af972..f520ca9 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -50,18 +50,18 @@
#include "kmb_dsi.h"
#define DEBUG
+
/*IRQ handler*/
static irqreturn_t kmb_isr(int irq, void *arg);
static struct clk *clk_lcd;
static struct clk *clk_mipi;
-static int probe_deferred;
struct drm_bridge *adv_bridge;
static int kmb_display_clk_enable(void)
{
- int ret;
+ int ret = 0;
ret = clk_prepare_enable(clk_lcd);
if (ret) {
@@ -87,86 +87,142 @@ static int kmb_display_clk_disable(void)
return 0;
}
+static void __iomem *kmb_map_mmio(struct platform_device *pdev, char *name)
+{
+ struct resource *res;
+ u32 size;
+ void __iomem *mem;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+ if (!res) {
+ DRM_ERROR("failed to get resource for %s\n", name);
+ return ERR_PTR(-ENOMEM);
+ }
+ size = resource_size(res);
+ if (!request_mem_region(res->start, size, name)) {
+ DRM_ERROR("failed to reserve %s registers\n", name);
+ return ERR_PTR(-ENOMEM);
+ }
+ mem = ioremap_cache(res->start, size);
+ if (!mem) {
+ DRM_ERROR("failed to ioremap %s registers\n", name);
+ release_mem_region(res->start, size);
+ return ERR_PTR(-ENOMEM);
+ }
+ return mem;
+}
+
static int kmb_load(struct drm_device *drm, unsigned long flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
struct platform_device *pdev = to_platform_device(drm->dev);
-/* struct drm_bridge *bridge;*/
- /*struct resource *res;*/
/*u32 version;*/
- int ret;
-/* struct device_node *encoder_node;*/
-
- /* TBD - not sure if clock_get needs to be called here */
- /*
-*dev_p->clk = devm_clk_get(drm->dev, "pxlclk");
-*if (IS_ERR(dev_p->clk))
-* return PTR_ERR(dev_p->clk);
-*/
- /*
-* TBD call this in the future when device tree is ready,
-* use hardcoded value for now
-*/
- /*
-* res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-* dev_p->lcd_mmio = devm_ioremap_resource(drm->dev, res);
-
-*if (IS_ERR(dev_p->lcd_mmio)) {
-* DRM_ERROR("failed to map control registers area\n");
-* ret = PTR_ERR(dev_p->lcd_mmio);
-* dev_p->lcd_mmio = NULL;
-* return ret;
-*}
-*/
- /* LCD mmio */
- probe_deferred = 1;
+ int ret = 0;
- if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) {
- DRM_ERROR("failed to reserve LCD registers\n");
- return -ENOMEM;
- }
- dev_p->lcd_mmio = ioremap_cache(LCD_BASE_ADDR, LCD_MMIO_SIZE);
- if (!dev_p->lcd_mmio) {
+ /* Map LCD MMIO registers */
+ dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs");
+ if (IS_ERR(dev_p->lcd_mmio)) {
DRM_ERROR("failed to map LCD registers\n");
return -ENOMEM;
}
- /* Mipi mmio */
- if (!request_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE, "kmb-mipi")) {
- DRM_ERROR("failed to reserve MIPI registers\n");
+
+ /* Map MIPI MMIO registers */
+ dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs");
+
+ if (IS_ERR(dev_p->mipi_mmio)) {
+ DRM_ERROR("failed to map MIPI registers\n");
iounmap(dev_p->lcd_mmio);
return -ENOMEM;
}
- dev_p->mipi_mmio = ioremap_cache(MIPI_BASE_ADDR, MIPI_MMIO_SIZE);
- if (!dev_p->mipi_mmio) {
- DRM_ERROR("failed to map MIPI registers\n");
+
+ /* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and MSS_CAM_CLK_CTRL
+* register
+*/
+ dev_p->msscam_mmio = kmb_map_mmio(pdev, "msscam_regs");
+ if (IS_ERR(dev_p->msscam_mmio)) {
+ DRM_ERROR("failed to map MSSCAM registers\n");
iounmap(dev_p->lcd_mmio);
+ iounmap(dev_p->mipi_mmio);
return -ENOMEM;
}
- /*this is only for MIPI_TX_MSS_LCD_MIPI_CFG register */
- if (!dev_p->msscam_mmio) {
-
[PATCH 59/59] drm/kmb: work around for planar formats
Set the DMA Vstride and Line width for U and V planes to the same as the
Y plane and not the actual pitch.
Bit18 of layer config does not have any effect when U and V planes are
swapped, so swap it in the driver.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_plane.c | 50 -
1 file changed, 30 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index e278347..eb1652d 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -190,6 +190,8 @@ unsigned int set_pixel_format(u32 format)
val = LCD_LAYER_FORMAT_RGBA;
break;
}
+ DRM_INFO_ONCE("%s : %d format=0x%x val=0x%x\n",
+__func__, __LINE__, format, val);
return val;
}
@@ -300,38 +302,48 @@ static void kmb_plane_atomic_update(struct drm_plane
*plane,
dev_p->fb_addr = addr[Y_PLANE];
kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id),
addr[Y_PLANE] + fb->offsets[0]);
+ val = set_pixel_format(fb->format->format);
+ val |= set_bits_per_pixel(fb->format);
/* Program Cb/Cr for planar formats */
if (num_planes > 1) {
- if (fb->format->format == DRM_FORMAT_YUV420 ||
- fb->format->format == DRM_FORMAT_YVU420)
- width /= 2;
-
kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id),
- fb->pitches[LAYER_1]);
-
+ width*fb->format->cpp[0]);
kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id),
(width * fb->format->cpp[0]));
addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state,
- U_PLANE);
- kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id),
- addr[U_PLANE]);
+ U_PLANE);
+ /* check if Cb/Cr is swapped*/
+ if ((num_planes == 3) && (val & LCD_LAYER_CRCB_ORDER))
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_START_CR_ADR(plane_id),
+ addr[U_PLANE]);
+ else
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_START_CB_ADR(plane_id),
+ addr[U_PLANE]);
if (num_planes == 3) {
kmb_write_lcd(dev_p,
- LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id),
- fb->pitches[LAYER_2]);
+ LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id),
+ ((width)*fb->format->cpp[0]));
kmb_write_lcd(dev_p,
- LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id),
- (width * fb->format->cpp[0]));
+ LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id),
+ ((width)*fb->format->cpp[0]));
addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb,
- plane->state,
- V_PLANE);
- kmb_write_lcd(dev_p,
- LCD_LAYERn_DMA_START_CR_ADR(plane_id),
- addr[V_PLANE]);
+ plane->state, V_PLANE);
+
+ /* check if Cb/Cr is swapped*/
+ if (val & LCD_LAYER_CRCB_ORDER)
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_START_CB_ADR(plane_id),
+ addr[V_PLANE]);
+ else
+ kmb_write_lcd(dev_p,
+ LCD_LAYERn_DMA_START_CR_ADR(plane_id),
+ addr[V_PLANE]);
}
}
@@ -340,8 +352,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x);
kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y);
- val = set_pixel_format(fb->format->format);
- val |= set_bits_per_pixel(fb->format);
/*CHECKME Leon drvr sets it to 100 try this for now */
val |= LCD_LAYER_FIFO_100;
--
2.7.4
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[PATCH 20/59] drm/kmb: Register IRQ for LCD
This code is commented out until firmware is updated to
redirect LCD IRQ from MSSCPU to A53.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index a94d387..d35f1b2 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -48,12 +48,16 @@
#include "kmb_plane.h"
#include "kmb_dsi.h"
+/*IRQ handler*/
+static irqreturn_t kmb_isr(int irq, void *arg);
+
static int kmb_load(struct drm_device *drm, unsigned long flags)
{
struct kmb_drm_private *dev_p = drm->dev_private;
struct platform_device *pdev = to_platform_device(drm->dev);
/*struct resource *res;*/
/*u32 version;*/
+ /*int irq_lcd, irq_mipi; */
int ret;
/* TBD - not sure if clock_get needs to be called here */
@@ -104,6 +108,12 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR,
MSS_CAM_MMIO_SIZE);
+ /*TODO - register irqs here - section 17.3 in databook
+* lists LCD at 79 under MSS CPU - firmware has to redirect it to A53
+* May be 33 for LCD and 34 for MIPI? Will wait till firmware
+* finalizes the IRQ numbers for redirection
+*/
+
/*TBD read and check for correct product version here */
/* Get the optional framebuffer memory resource */
@@ -151,7 +161,7 @@ static void kmb_setup_mode_config(struct drm_device *drm)
drm->mode_config.funcs = _mode_config_funcs;
}
-static irqreturn_t kmb_irq(int irq, void *arg)
+static irqreturn_t kmb_isr(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *)arg;
unsigned long status, val;
@@ -196,8 +206,9 @@ DEFINE_DRM_GEM_CMA_FOPS(fops);
static struct drm_driver kmb_driver = {
.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
- DRIVER_MODESET | DRIVER_ATOMIC,
- .irq_handler = kmb_irq,
+ DRIVER_MODESET |
+ DRIVER_ATOMIC,
+ .irq_handler = kmb_isr,
.irq_preinstall = kmb_irq_reset,
.irq_uninstall = kmb_irq_reset,
.gem_free_object_unlocked = drm_gem_cma_free_object,
--
2.7.4
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[PATCH 11/59] drm/kmb: Use correct mmio offset from data book
Also added separate macros for lcd and mipi register accesses that
use the corrected mmio offset. mmio oofset will be read from the device
tree in the future.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 49 ++---
drivers/gpu/drm/kmb/kmb_drv.c | 18 ++-
drivers/gpu/drm/kmb/kmb_drv.h | 47 ---
drivers/gpu/drm/kmb/kmb_dsi.c | 41 +++---
drivers/gpu/drm/kmb/kmb_plane.c | 34 ++--
drivers/gpu/drm/kmb/kmb_regs.h | 6 -
6 files changed, 113 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 6f16410..8e127ae 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -52,25 +52,21 @@ static void kmb_crtc_cleanup(struct drm_crtc *crtc)
static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
{
- struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc);
-
/*clear interrupt */
- kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
+ kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP);
/*set which interval to generate vertical interrupt */
- kmb_write(lcd, LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC);
+ kmb_write_lcd(LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC);
/* enable vertical interrupt */
- kmb_write(lcd, LCD_INT_ENABLE, LCD_INT_VERT_COMP);
+ kmb_write_lcd(LCD_INT_ENABLE, LCD_INT_VERT_COMP);
return 0;
}
static void kmb_crtc_disable_vblank(struct drm_crtc *crtc)
{
- struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc);
-
/*clear interrupt */
- kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
+ kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP);
/* disable vertical interrupt */
- kmb_write(lcd, LCD_INT_ENABLE, 0);
+ kmb_write_lcd(LCD_INT_ENABLE, 0);
/* TBD
* set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register
@@ -92,7 +88,6 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = {
static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
- struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc);
struct drm_display_mode *m = >state->adjusted_mode;
struct videomode vm;
int vsync_start_offset;
@@ -109,30 +104,30 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
- kmb_write(lcd, LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1);
- kmb_write(lcd, LCD_V_BACKPORCH, vm.vback_porch - 1);
- kmb_write(lcd, LCD_V_FRONTPORCH, vm.vfront_porch - 1);
- kmb_write(lcd, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
- kmb_write(lcd, LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1);
- kmb_write(lcd, LCD_H_BACKPORCH, vm.hback_porch - 1);
- kmb_write(lcd, LCD_H_FRONTPORCH, vm.hfront_porch - 1);
- kmb_write(lcd, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
+ kmb_write_lcd(LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1);
+ kmb_write_lcd(LCD_V_BACKPORCH, vm.vback_porch - 1);
+ kmb_write_lcd(LCD_V_FRONTPORCH, vm.vfront_porch - 1);
+ kmb_write_lcd(LCD_VSYNC_WIDTH, vm.vsync_len - 1);
+ kmb_write_lcd(LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1);
+ kmb_write_lcd(LCD_H_BACKPORCH, vm.hback_porch - 1);
+ kmb_write_lcd(LCD_H_FRONTPORCH, vm.hfront_porch - 1);
+ kmb_write_lcd(LCD_HSYNC_WIDTH, vm.hsync_len - 1);
if (m->flags == DRM_MODE_FLAG_INTERLACE) {
- kmb_write(lcd, LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
- kmb_write(lcd, LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1);
- kmb_write(lcd, LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
- kmb_write(lcd, LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1);
- kmb_write(lcd, LCD_VSYNC_START_EVEN, vsync_start_offset);
- kmb_write(lcd, LCD_VSYNC_END_EVEN, vsync_end_offset);
+ kmb_write_lcd(LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
+ kmb_write_lcd(LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1);
+ kmb_write_lcd(LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
+ kmb_write_lcd(LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1);
+ kmb_write_lcd(LCD_VSYNC_START_EVEN, vsync_start_offset);
+ kmb_write_lcd(LCD_VSYNC_END_EVEN, vsync_end_offset);
}
/* enable VL1 layer as default */
ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
- | LCD_CTRL_OUTPUT_ENABLED;
- kmb_write(lcd, LCD_CONTROL, ctrl);
+ | LCD_CTRL_OUTPUT_ENABLED;
+ kmb_write_lcd(LCD_CONTROL, ctrl);
- kmb_write(lcd, LCD_TIMING_GEN_TRIG, ENABLE);
+ kmb_write_lcd(LCD_TIMING_GEN_TRIG, ENABLE);
/* TBD */
[PATCH 48/59] drm/kmb: SWAP R and B LCD Layer order
Set swap bit for the colors to display correctly
when the format is RGB and not set when its BGR.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index d87a3a2..9f9ae57 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -218,54 +218,55 @@ unsigned int set_pixel_format(u32 format)
val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE
| LCD_LAYER_CRCB_ORDER;
break;
- /* packed formats */
+ /* packed formats */
+ /* looks hw requires B & G to be swapped when RGB */
case DRM_FORMAT_RGB332:
- val = LCD_LAYER_FORMAT_RGB332;
+ val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_XBGR:
- val = LCD_LAYER_FORMAT_RGBX | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_RGBX;
break;
case DRM_FORMAT_ARGB:
- val = LCD_LAYER_FORMAT_RGBA;
+ val = LCD_LAYER_FORMAT_RGBA | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_ABGR:
- val = LCD_LAYER_FORMAT_RGBA | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_RGBA;
break;
case DRM_FORMAT_XRGB1555:
- val = LCD_LAYER_FORMAT_XRGB1555;
+ val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_XBGR1555:
- val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_XRGB1555;
break;
case DRM_FORMAT_ARGB1555:
- val = LCD_LAYER_FORMAT_RGBA1555;
+ val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_ABGR1555:
- val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_RGBA1555;
break;
case DRM_FORMAT_RGB565:
- val = LCD_LAYER_FORMAT_RGB565;
+ val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_BGR565:
- val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_RGB565;
break;
case DRM_FORMAT_RGB888:
- val = LCD_LAYER_FORMAT_RGB888;
+ val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_BGR888:
- val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_RGB888;
break;
case DRM_FORMAT_XRGB:
- val = LCD_LAYER_FORMAT_RGBX;
+ val = LCD_LAYER_FORMAT_RGBX | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_XBGR:
- val = LCD_LAYER_FORMAT_RGBX | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_RGBX;
break;
case DRM_FORMAT_ARGB:
- val = LCD_LAYER_FORMAT_RGBA;
+ val = LCD_LAYER_FORMAT_RGBA | LCD_LAYER_BGR_ORDER;
break;
case DRM_FORMAT_ABGR:
- val = LCD_LAYER_FORMAT_RGBA | LCD_LAYER_BGR_ORDER;
+ val = LCD_LAYER_FORMAT_RGBA;
break;
}
DRM_INFO("%s : %d layer format val=%d\n", __func__, __LINE__, val);
@@ -370,7 +371,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
val |= set_bits_per_pixel(fb->format);
/*CHECKME Leon drvr sets it to 100 try this for now */
val |= LCD_LAYER_FIFO_100;
- val |= LCD_LAYER_BGR_ORDER;
kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val);
/*re-initialize interrupts */
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 38/59] drm/kmb: Mipi DPHY initialization changes
Fix test_mode_send and dphy_wait_fsm for 2-lane MIPI
- Fix test_mode_send when sending normal mode test codes
- Change dphy_wait_fsm to check for IDLE status rather than LOCK
status for 2-lane MIPI
Signed-off-by: Anitha Chrisanthus
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_crtc.c | 23 +-
drivers/gpu/drm/kmb/kmb_drv.c | 90 ++--
drivers/gpu/drm/kmb/kmb_drv.h | 23 +-
drivers/gpu/drm/kmb/kmb_dsi.c | 904 +---
drivers/gpu/drm/kmb/kmb_dsi.h | 2 +-
drivers/gpu/drm/kmb/kmb_plane.c | 59 ++-
drivers/gpu/drm/kmb/kmb_regs.h | 34 +-
7 files changed, 840 insertions(+), 295 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index 053da17..01ad82e 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -41,6 +41,7 @@
#include "kmb_drv.h"
#include "kmb_plane.h"
#include "kmb_regs.h"
+#include "kmb_dsi.h"
static void kmb_crtc_cleanup(struct drm_crtc *crtc)
{
@@ -93,23 +94,33 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = {
static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
- struct drm_display_mode *m = >state->adjusted_mode;
struct drm_device *dev = crtc->dev;
+#ifdef LCD_TEST
+ struct drm_display_mode *m = >state->adjusted_mode;
struct videomode vm;
int vsync_start_offset;
int vsync_end_offset;
unsigned int ctrl = 0;
-
+#endif
+ /* initialize mipi */
+ kmb_dsi_hw_init(dev);
+#ifdef LCD_TEST
vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
- vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
+ //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
+ vm.hfront_porch = 0;
vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
+ DRM_INFO("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d
h-bp=%d h-fp=%d hysnc-l=%d\n",
+ __func__, __LINE__, m->crtc_vdisplay,
+ vm.vback_porch, vm.vfront_porch,
+ vm.vsync_len, m->crtc_hdisplay,
+ vm.hback_porch, vm.hfront_porch, vm.hsync_len);
kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT,
m->crtc_vdisplay - 1);
kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch - 1);
@@ -144,7 +155,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl);
kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE);
-
+#endif
/* TBD */
/* set clocks here */
}
@@ -156,7 +167,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc,
clk_prepare_enable(lcd->clk);
kmb_crtc_mode_set_nofb(crtc);
- drm_crtc_vblank_on(crtc);
+// drm_crtc_vblank_on(crtc);
}
static void kmb_crtc_atomic_disable(struct drm_crtc *crtc,
@@ -167,7 +178,7 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc,
/* always disable planes on the CRTC that is being turned off */
drm_atomic_helper_disable_planes_on_crtc(old_state, false);
- drm_crtc_vblank_off(crtc);
+// drm_crtc_vblank_off(crtc);
clk_disable_unprepare(lcd->clk);
}
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 1fc0b2e..b5c8711 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -57,27 +58,27 @@ static irqreturn_t kmb_isr(int irq, void *arg);
static struct clk *clk_lcd;
static struct clk *clk_mipi;
static struct clk *clk_msscam;
+static struct clk *clk_pll0out0;
static struct clk *clk_mipi_ecfg;
static struct clk *clk_mipi_cfg;
struct drm_bridge *adv_bridge;
-static int kmb_display_clk_enable(void)
+int kmb_display_clk_enable(void)
{
int ret = 0;
-
+#ifdef LCD_TEST
ret = clk_prepare_enable(clk_lcd);
if (ret) {
DRM_ERROR("Failed to enable LCD clock: %d\n", ret);
return ret;
}
-
+#endif
ret = clk_prepare_enable(clk_mipi);
if (ret) {
DRM_ERROR("Failed to enable MIPI clock: %d\n", ret);
return ret;
}
-
/* ret = clk_prepare_enable(clk_msscam);
if (ret) {
DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret);
@@ -178,19 +179,47 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
iounmap(dev_p->mipi_mmio);
return -ENOMEM;
}
+/*testing*/
+ if
[PATCH 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi
Added handlers for lcd and mipi, it only finds and clears the interrupt
as of now, more functionality can be added as needed.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 51 --
drivers/gpu/drm/kmb/kmb_drv.h | 2 ++
drivers/gpu/drm/kmb/kmb_dsi.c | 37 --
drivers/gpu/drm/kmb/kmb_dsi.h | 1 +
drivers/gpu/drm/kmb/kmb_regs.h | 35 +
5 files changed, 108 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index d35f1b2..e5f4da1 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -57,7 +57,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
struct platform_device *pdev = to_platform_device(drm->dev);
/*struct resource *res;*/
/*u32 version;*/
- /*int irq_lcd, irq_mipi; */
+ int irq_lcd, irq_mipi;
int ret;
/* TBD - not sure if clock_get needs to be called here */
@@ -108,11 +108,29 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR,
MSS_CAM_MMIO_SIZE);
- /*TODO - register irqs here - section 17.3 in databook
-* lists LCD at 79 under MSS CPU - firmware has to redirect it to A53
-* May be 33 for LCD and 34 for MIPI? Will wait till firmware
-* finalizes the IRQ numbers for redirection
+ /* register irqs here - section 17.3 in databook
+* lists LCD at 79 and 82 for MIPI under MSS CPU -
+* firmware has to redirect it to A53
*/
+ irq_lcd = platform_get_irq_byname(pdev, "irq_lcd");
+ if (irq_lcd < 0) {
+ DRM_ERROR("irq_lcd not found");
+ return irq_lcd;
+ }
+ pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd);
+ ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p);
+ dev_p->irq_lcd = irq_lcd;
+
+ irq_mipi = platform_get_irq_byname(pdev, "irq_mipi");
+ if (irq_mipi < 0) {
+ DRM_ERROR("irq_mipi not found");
+ return irq_mipi;
+ }
+ pr_info("irq_mipi platform_get_irq = %d\n", irq_mipi);
+ ret = request_irq(irq_mipi, kmb_isr, IRQF_SHARED, "irq_mipi", dev_p);
+ dev_p->irq_mipi = irq_mipi;
+
+
/*TBD read and check for correct product version here */
@@ -161,9 +179,9 @@ static void kmb_setup_mode_config(struct drm_device *drm)
drm->mode_config.funcs = _mode_config_funcs;
}
-static irqreturn_t kmb_isr(int irq, void *arg)
+
+static irqreturn_t handle_lcd_irq(struct drm_device *dev)
{
- struct drm_device *dev = (struct drm_device *)arg;
unsigned long status, val;
status = kmb_read_lcd(dev->dev_private, LCD_INT_STATUS);
@@ -192,10 +210,29 @@ static irqreturn_t kmb_isr(int irq, void *arg)
break;
}
}
+ return IRQ_HANDLED;
+}
+static irqreturn_t handle_mipi_irq(struct drm_device *dev)
+{
+ mipi_tx_handle_irqs(dev->dev_private);
return IRQ_HANDLED;
}
+static irqreturn_t kmb_isr(int irq, void *arg)
+{
+ struct drm_device *dev = (struct drm_device *)arg;
+ struct kmb_drm_private *dev_p = dev->dev_private;
+ irqreturn_t ret = IRQ_NONE;
+
+ if (irq == dev_p->irq_lcd)
+ ret = handle_lcd_irq(dev);
+ else if (irq == dev_p->irq_mipi)
+ ret = handle_mipi_irq(dev);
+
+ return ret;
+}
+
static void kmb_irq_reset(struct drm_device *drm)
{
kmb_write_lcd(drm->dev_private, LCD_INT_CLEAR, 0x);
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index ad5f214..dcaeb11 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -43,6 +43,8 @@ struct kmb_drm_private {
struct kmb_plane*plane;
struct drm_atomic_state *state;
spinlock_t irq_lock;
+ int irq_lcd;
+ int irq_mipi;
};
static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 4d2790f..684ddbc 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -1234,7 +1234,7 @@ static void mipi_tx_init_irqs(struct kmb_drm_private
*dev_p,
SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL);
/*global interrupts */
SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ);
- SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DHY_ERR_IRQ);
+ SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ);
SET_MIPI_CTRL_IRQ_CLEAR1(dev_p, MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ);
/*enable interrupts */
@@ -1250,7 +1250,7 @@ static void
[PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization
This initializes the mipi high speed transmitter CTRL and SYNC
configuration registers.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 55 --
drivers/gpu/drm/kmb/kmb_regs.h | 29 +-
2 files changed, 81 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 92a62e5..886a8ac 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -553,6 +553,55 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes,
u8 vchannel_id)
kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id);
}
+static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg)
+{
+ u32 sync_cfg = 0, ctrl = 0, fg_en;
+ u32 ctrl_no = MIPI_CTRL6;
+
+ /*MIPI_TX_HS_SYNC_CFG*/
+ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en)
+ sync_cfg |= LINE_SYNC_PKT_ENABLE;
+ if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active)
+ sync_cfg |= FRAME_COUNTER_ACTIVE;
+ if (ctrl_cfg->tx_ctrl_cfg.line_counter_active)
+ sync_cfg |= LINE_COUNTER_ACTIVE;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->v_blanking)
+ sync_cfg |= DSI_V_BLANKING;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking)
+ sync_cfg |= DSI_HSA_BLANKING;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking)
+ sync_cfg |= DSI_HBP_BLANKING;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking)
+ sync_cfg |= DSI_HFP_BLANKING;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->sync_pulse_eventn)
+ sync_cfg |= DSI_SYNC_PULSE_EVENTN;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_first_vsa_line)
+ sync_cfg |= DSI_LPM_FIRST_VSA_LINE;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line)
+ sync_cfg |= DSI_LPM_LAST_VFP_LINE;
+ /* enable frame generator */
+ fg_en = 1 << fg_id;
+ sync_cfg |= FRAME_GEN_EN(fg_en);
+ if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact)
+ sync_cfg |= ALWAYS_USE_HACT(fg_en);
+ if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop)
+ sync_cfg |= HACT_WAIT_STOP(fg_en);
+
+ /* MIPI_TX_HS_CTRL*/
+ ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en)
+ ctrl |= DSI_EOTP_EN;
+ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en)
+ ctrl |= DSI_CMD_HFP_EN;
+ ctrl |= LCD_VC(fg_id);
+ ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1);
+ /*67 ns stop time*/
+ ctrl |= HSEXIT_CNT(0x43);
+
+ kmb_write_mipi(MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg);
+ kmb_write_mipi(MIPI_TXm_HS_CTRL(ctrl_no), ctrl);
+}
+
static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv,
struct mipi_ctrl_cfg *ctrl_cfg)
{
@@ -596,8 +645,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private
*dev_priv,
/* set frame specific parameters */
mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes,
bits_per_pclk,
- word_count,
- ctrl_cfg->lane_rate_mbps,
+ word_count, ctrl_cfg->lane_rate_mbps,
ctrl_cfg->tx_ctrl_cfg.frames[frame_id]);
active_vchannels++;
@@ -612,6 +660,9 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private
*dev_priv,
return -EINVAL;
/*Multi-Channel FIFO Configuration*/
mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id);
+
+ /*Frame Generator Enable */
+ mipi_tx_ctrl_cfg(frame_id, ctrl_cfg);
return ret;
}
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index d6fcead..9a5f371 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -398,7 +398,35 @@
#define MIPI_CTRL_HS_BASE_ADDR (0x400)
#define MIPI_TX_HS_CTRL(0x0)
+#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M))
+#define HS_CTRL_EN (1 << 0)
+#define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/
+#define TX_SOURCE(1 << 3) /*1:LCD, 0:DMA*/
+#define ACTIVE_LANES(n) ((n) << 4)
+#define LCD_VC(ch) ((ch) << 8)
+#define DSI_EOTP_EN (1 << 11)
+#define DSI_CMD_HFP_EN (1 << 12)
+#define CRC_EN (1 << 14)
+#define HSEXIT_CNT(n)((n) << 16)
+#define HSCLKIDLE_CNT(1 << 24)
#define MIPI_TX_HS_SYNC_CFG(0x8)
+#define MIPI_TXm_HS_SYNC_CFG(M)
[PATCH 47/59] drm/kmb: Don’t inadvertantly disable LCD controller
setbits instead of write dword for LCD_CONTROL register
this was inadvertantly disabling the LCD controller.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 1990e8c..d87a3a2 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -178,6 +178,9 @@ static void kmb_plane_atomic_disable(struct drm_plane
*plane,
kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id),
LCD_DMA_LAYER_ENABLE);
kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl);
+ DRM_INFO("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n",
+ __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL),
+ kmb_read_lcd(dev_p, LCD_INT_ENABLE));
}
@@ -476,7 +479,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
*/
ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL;
- kmb_write_lcd(dev_p, LCD_CONTROL, ctrl);
+ kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl);
/* FIXME no doc on how to set output format,these values are taken
* from the Myriadx tests
--
2.7.4
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 23/59] drm/kmb: Additional register programming to update_plane
These changes are ported from Myriadx which has additional registers
updated for planes. This change does the following
reinitialize plane interrupts
program Cb/Cr for planar formats
set LCD_CTRL_VHSYNC_IDLE_LVL
set output format and configure csc
v2: code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 16
drivers/gpu/drm/kmb/kmb_plane.c | 183
drivers/gpu/drm/kmb/kmb_regs.h | 72 ++--
3 files changed, 210 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index dcaeb11..50efa8a 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -112,6 +112,22 @@ static inline u32 kmb_read_lcd(struct kmb_drm_private
*dev_p, unsigned int reg)
return readl(dev_p->lcd_mmio + reg);
}
+static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p,
+ unsigned int reg, u32 mask)
+{
+ u32 reg_val = kmb_read_lcd(dev_p->lcd_mmio, reg);
+
+ kmb_write_lcd(dev_p->lcd_mmio, reg, (reg_val | mask));
+}
+
+static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p,
+ unsigned int reg, u32 mask)
+{
+ u32 reg_val = kmb_read_lcd(dev_p->lcd_mmio, reg);
+
+ kmb_write_lcd(dev_p->lcd_mmio, reg, (reg_val & (~mask)));
+}
+
static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int
reg)
{
return readl(dev_p->mipi_mmio + reg);
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 3841d96..026df49 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -76,6 +76,46 @@ static const u32 kmb_formats_v[] = {
DRM_FORMAT_NV12, DRM_FORMAT_NV21,
};
+#define LCD_INT_VL0_ERR (LAYER0_DMA_FIFO_UNDEFLOW | \
+ LAYER0_DMA_FIFO_OVERFLOW | \
+ LAYER0_DMA_CB_FIFO_OVERFLOW | \
+ LAYER0_DMA_CB_FIFO_UNDERFLOW | \
+ LAYER0_DMA_CR_FIFO_OVERFLOW | \
+ LAYER0_DMA_CR_FIFO_UNDERFLOW)
+
+#define LCD_INT_VL1_ERR (LAYER1_DMA_FIFO_UNDERFLOW | \
+ LAYER1_DMA_FIFO_OVERFLOW | \
+ LAYER1_DMA_CB_FIFO_OVERFLOW | \
+ LAYER1_DMA_CB_FIFO_UNDERFLOW | \
+ LAYER1_DMA_CR_FIFO_OVERFLOW | \
+ LAYER1_DMA_CR_FIFO_UNDERFLOW)
+
+#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW)
+
+#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW)
+
+#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR)
+
+#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR)
+
+#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR)
+
+#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR)
+
+const uint32_t layer_irqs[] = {
+ LCD_INT_VL0,
+ LCD_INT_VL1,
+ LCD_INT_GL0,
+ LCD_INT_GL1
+ };
+/*Conversion (yuv->rgb) matrix from myriadx */
+static const u32 csc_coef_lcd[] = {
+ 1024, 0, 1436,
+ 1024, -352, -731,
+ 1024, 1814, 0,
+ -179, 125, -226
+};
+
static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
{
int i;
@@ -217,6 +257,24 @@ unsigned int set_bits_per_pixel(const struct
drm_format_info *format)
return val;
}
+static void config_csc(struct kmb_drm_private *dev_p, int plane_id)
+{
+ /*YUV to RGB conversion using the fixed matrix csc_coef_lcd */
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]);
+ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]);
+ kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_CFG(plane_id), LCD_LAYER_CSC_EN);
+}
+
static void kmb_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *state)
{
@@ -231,6 +289,7 @@ static void kmb_plane_atomic_update(struct drm_plane
[PATCH 12/59] drm/kmb: Part3 of Mipi Tx initialization
This initializes the multichannel fifo in the mipi transmitter and
sets the LCD to mipi interconnect which connects LCD to MIPI ctrl #6
v2: code review changes to make code simpler
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 25 +++---
drivers/gpu/drm/kmb/kmb_dsi.c | 58 ++
drivers/gpu/drm/kmb/kmb_dsi.h | 3 +++
drivers/gpu/drm/kmb/kmb_regs.h | 30 +++---
4 files changed, 99 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index a431785..ba5b3e0 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -28,8 +28,8 @@
#include "kmb_regs.h"
-#define KMB_MAX_WIDTH 16384 /*max width in pixels */
-#define KMB_MAX_HEIGHT 16384 /*max height in pixels */
+#define KMB_MAX_WIDTH 16384 /*max width in pixels */
+#define KMB_MAX_HEIGHT 16384 /*max height in pixels */
struct kmb_drm_private {
struct drm_device drm;
@@ -84,6 +84,11 @@ static inline void kmb_write_bits(struct kmb_drm_private
*lcd,
}
#endif
+static inline void kmb_write(void *reg, u32 value)
+{
+ writel(value, reg);
+}
+
static inline void kmb_write_lcd(unsigned int reg, u32 value)
{
writel(value, (LCD_BASE_ADDR + reg));
@@ -105,7 +110,7 @@ static inline u32 kmb_read_mipi(unsigned int reg)
}
static inline void kmb_write_bits_mipi(unsigned int reg, u32 offset,
- u32 num_bits, u32 value)
+ u32 num_bits, u32 value)
{
u32 reg_val = kmb_read_mipi(reg);
u32 mask = (1 << num_bits) - 1;
@@ -117,6 +122,20 @@ static inline void kmb_write_bits_mipi(unsigned int reg,
u32 offset,
kmb_write_mipi(reg, reg_val);
}
+static inline void kmb_set_bit_mipi(unsigned int reg, u32 offset)
+{
+ u32 reg_val = kmb_read_mipi(reg);
+
+ kmb_write_mipi(reg, reg_val | (1 << offset));
+}
+
+static inline void kmb_clr_bit_mipi(unsigned int reg, u32 offset)
+{
+ u32 reg_val = kmb_read_mipi(reg);
+
+ kmb_write_mipi(reg, reg_val & (~(1 << offset)));
+}
+
int kmb_setup_crtc(struct drm_device *dev);
void kmb_set_scanout(struct kmb_drm_private *lcd);
#endif /* __KMB_DRV_H__ */
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 109c83b..92a62e5 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -523,10 +523,41 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private
*dev_priv, u8 frame_gen,
mipi_tx_fg_cfg_regs(dev_priv, frame_gen, _t_cfg);
}
+static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id)
+{
+ u32 fifo_size, fifo_rthreshold;
+ u32 ctrl_no = MIPI_CTRL6;
+
+ /*clear all mc fifo channel sizes and thresholds*/
+ kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CTRL_EN, 0);
+ kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0);
+ kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0);
+ kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0);
+ kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0);
+
+ fifo_size = (active_lanes > MIPI_D_LANES_PER_DPHY) ?
+ MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC :
+ MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC;
+ /*MC fifo size for virtual channels 0-3 */
+ /*
+*REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1
+*REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3
+*/
+ SET_MC_FIFO_CHAN_ALLOC(ctrl_no, vchannel_id, fifo_size);
+
+ /*set threshold to half the fifo size, actual size=size*16*/
+ fifo_rthreshold = ((fifo_size + 1) * 8) & BIT_MASK_16;
+ SET_MC_FIFO_RTHRESHOLD(ctrl_no, vchannel_id, fifo_rthreshold);
+
+ /*enable the MC FIFO channel corresponding to the Virtual Channel */
+ kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id);
+}
+
static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv,
- struct mipi_ctrl_cfg *ctrl_cfg)
+ struct mipi_ctrl_cfg *ctrl_cfg)
{
u32 ret;
+ u8 active_vchannels = 0;
u8 frame_id, sect;
u32 bits_per_pclk = 0;
u32 word_count = 0;
@@ -564,18 +595,23 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private
*dev_priv,
/* set frame specific parameters */
mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes,
- bits_per_pclk,
- word_count,
- ctrl_cfg->lane_rate_mbps,
- ctrl_cfg->tx_ctrl_cfg.frames[frame_id]);
- /*function for setting frame sepecific parameters will be
-* called here
-*/
- /*bits_per_pclk and word_count will be passed in to this
-* function
-*/
+
[PATCH 02/59] drm/kmb: Added id to kmb_plane
This is to keep track of the id of the plane as there are 4 planes in
Kmb and when update() is called, we need to know which plane need to be
updated so that the corresponding plane's registers can be programmed.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 13 ---
drivers/gpu/drm/kmb/kmb_crtc.h | 2 +-
drivers/gpu/drm/kmb/kmb_drv.h | 2 +-
drivers/gpu/drm/kmb/kmb_plane.c | 80 +++--
drivers/gpu/drm/kmb/kmb_plane.h | 28 +--
5 files changed, 79 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
index ab1fff8..6f16410 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.c
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -126,9 +126,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
kmb_write(lcd, LCD_VSYNC_START_EVEN, vsync_start_offset);
kmb_write(lcd, LCD_VSYNC_END_EVEN, vsync_end_offset);
}
- /* enable all 4 layers */
- ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE
- | LCD_CTRL_VL2_ENABLE | LCD_CTRL_GL1_ENABLE | LCD_CTRL_GL2_ENABLE;
+ /* enable VL1 layer as default */
+ ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
| LCD_CTRL_OUTPUT_ENABLED;
kmb_write(lcd, LCD_CONTROL, ctrl);
@@ -196,17 +195,17 @@ static const struct drm_crtc_helper_funcs
kmb_crtc_helper_funcs = {
int kmb_setup_crtc(struct drm_device *drm)
{
struct kmb_drm_private *lcd = drm->dev_private;
- struct drm_plane *primary;
+ struct kmb_plane *primary;
int ret;
primary = kmb_plane_init(drm);
if (IS_ERR(primary))
return PTR_ERR(primary);
- ret = drm_crtc_init_with_planes(drm, >crtc, primary, NULL,
- _crtc_funcs, NULL);
+ ret = drm_crtc_init_with_planes(drm, >crtc, >base_plane,
+ NULL, _crtc_funcs, NULL);
if (ret) {
- kmb_plane_destroy(primary);
+ kmb_plane_destroy(>base_plane);
return ret;
}
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.h b/drivers/gpu/drm/kmb/kmb_crtc.h
index 0952733..5fe8890 100644
--- a/drivers/gpu/drm/kmb/kmb_crtc.h
+++ b/drivers/gpu/drm/kmb/kmb_crtc.h
@@ -55,5 +55,5 @@ struct kmb_crtc_state {
#define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base)
#define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base)
extern void kmb_plane_destroy(struct drm_plane *plane);
-extern struct drm_plane *kmb_plane_init(struct drm_device *drm);
+extern struct kmb_plane *kmb_plane_init(struct drm_device *drm);
#endif /* __KMB_CRTC_H__ */
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 05e9791..637e9a2 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -36,7 +36,7 @@ struct kmb_drm_private {
struct clk *clk;
struct drm_fbdev_cma *fbdev;
struct drm_crtc crtc;
- struct drm_plane *plane;
+ struct kmb_plane *plane;
struct drm_atomic_state *state;
};
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 9ab3873..b9d8d38 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -61,46 +61,69 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
dma_addr_t addr;
unsigned int width;
unsigned int height;
- unsigned int i;
unsigned int dma_len;
- struct kmb_plane_state *kmb_state = to_kmb_plane_state(plane->state);
+ struct kmb_plane *kmb_plane = to_kmb_plane(plane);
unsigned int dma_cfg;
+ unsigned int ctrl = 0;
+ unsigned char plane_id = kmb_plane->id;
if (!fb)
return;
lcd = plane->dev->dev_private;
+ switch (plane_id) {
+ case LAYER_0:
+ ctrl = LCD_CTRL_VL1_ENABLE;
+ break;
+ case LAYER_1:
+ ctrl = LCD_CTRL_VL2_ENABLE;
+ break;
+ case LAYER_2:
+ ctrl = LCD_CTRL_GL1_ENABLE;
+ break;
+ case LAYER_3:
+ ctrl = LCD_CTRL_GL2_ENABLE;
+ break;
+ }
+
+ ctrl |= LCD_CTRL_ENABLE;
+ ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
+ | LCD_CTRL_OUTPUT_ENABLED;
+ kmb_write(lcd, LCD_CONTROL, ctrl);
+
/* TBD */
/*set LCD_LAYERn_WIDTH, LCD_LAYERn_HEIGHT, LCD_LAYERn_COL_START,
* LCD_LAYERn_ROW_START, LCD_LAYERn_CFG
* CFG should set the pixel format, FIFO level and BPP
*/
+ /*TBD check visible? */
+
/* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */
dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE
| LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1;
-
[PATCH 00/59] Add support for Keem Bay DRM driver
This is a new DRM driver for Intel's KeemBay SOC. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This driver is tested with the KMB EVM board which is the refernce baord for Keem Bay SOC. The SOC's display pipeline is as follows +--++-++---+ |LCD controller| -> |Mipi DSI | -> |Mipi to HDMI Converter | +--++-++---+ LCD controller and Mipi DSI transmitter are part of the SOC and mipi to HDMI converter is ADV7535 for KMB EVM board. The DRM driver is a basic KMS atomic modesetting display driver and has no 2D or 3D graphics.It calls into the ADV bridge driver at the connector level. Only 1080p resolution and single plane is supported at this time. The usecase is for debugging video and camera outputs. Since we are just starting the upstream process, the KMB EVM board is not in mainline and so Device tree changes are missing. Anitha Chrisanthus (52): drm/kmb: Add support for KeemBay Display drm/kmb: Added id to kmb_plane drm/kmb: Set correct values in the LAYERn_CFG register drm/kmb: Use biwise operators for register definitions drm/kmb: Updated kmb_plane_atomic_check drm/kmb: Initial check-in for Mipi DSI drm/kmb: Set OUT_FORMAT_CFG register drm/kmb: Added mipi_dsi_host initialization drm/kmb: Part 1 of Mipi Tx Initialization drm/kmb: Part 2 of Mipi Tx Initialization drm/kmb: Use correct mmio offset from data book drm/kmb: Part3 of Mipi Tx initialization drm/kmb: Part4 of Mipi Tx Initialization drm/kmb: Correct address offsets for mipi registers drm/kmb: Part5 of Mipi Tx Intitialization drm/kmb: Part6 of Mipi Tx Initialization drm/kmb: Part7 of Mipi Tx Initialization drm/kmb: Part8 of Mipi Tx Initialization drm/kmb: Added ioremap/iounmap for register access drm/kmb: Register IRQ for LCD drm/kmb: IRQ handlers for LCD and mipi dsi drm/kmb: Set hardcoded values to LCD_VSYNC_START drm/kmb: Additional register programming to update_plane drm/kmb: Add ADV7535 bridge drm/kmb: Display clock enable/disable drm/kmb: rebase to newer kernel version drm/kmb: minor name change to match device tree drm/kmb: Changed MMIO size drm/kmb: Defer Probe drm/kmb: call bridge init in the very beginning drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable drm/kmb: Mipi DPHY initialization changes drm/kmb: Fixed driver unload drm/kmb: Added LCD_TEST config drm/kmb: Changes for LCD to Mipi drm/kmb: Update LCD programming to match MIPI drm/kmb: Changed name of driver to kmb-drm drm/kmb: Mipi settings from input timings drm/kmb: Enable LCD interrupts drm/kmb: Enable LCD interrupts during modeset drm/kmb: Don’t inadvertantly disable LCD controller drm/kmb: SWAP R and B LCD Layer order drm/kmb: Disable ping pong mode drm/kmb: Do the layer initializations only once drm/kmb: disable the LCD layer in EOF irq handler drm/kmb: Initialize uninitialized variables drm/kmb: Added useful messages in LCD ISR kmb/drm: Prune unsupported modes drm/kmb: workaround for dma undeflow issue drm/kmb: Get System Clock from SCMI drm/kmb: work around for planar formats Edmund Dea (7): drm/kmb: Cleanup probe functions drm/kmb: Revert dsi_host back to a static variable drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg. drm/kmb: Remove declaration of irq_lcd/irq_mipi drm/kmb: Enable MIPI TX HS Test Pattern Generation drm/kmb: Write to LCD_LAYERn_CFG only once drm/kmb: Cleaned up code drivers/gpu/drm/Kconfig |2 + drivers/gpu/drm/Makefile|1 + drivers/gpu/drm/kmb/Kconfig | 12 + drivers/gpu/drm/kmb/Makefile|2 + drivers/gpu/drm/kmb/kmb_crtc.c | 243 + drivers/gpu/drm/kmb/kmb_crtc.h | 61 ++ drivers/gpu/drm/kmb/kmb_drv.c | 828 + drivers/gpu/drm/kmb/kmb_drv.h | 196 drivers/gpu/drm/kmb/kmb_dsi.c | 1950 +++ drivers/gpu/drm/kmb/kmb_dsi.h | 390 drivers/gpu/drm/kmb/kmb_plane.c | 538 +++ drivers/gpu/drm/kmb/kmb_plane.h | 142 +++ drivers/gpu/drm/kmb/kmb_regs.h | 758 +++ 13 files changed, 5123 insertions(+) create mode 100644 drivers/gpu/drm/kmb/Kconfig create mode 100644 drivers/gpu/drm/kmb/Makefile create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.c create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.h create mode 100644 drivers/gpu/drm/kmb/kmb_drv.c create mode 100644 drivers/gpu/drm/kmb/kmb_drv.h create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.c create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.h create mode 100644 drivers/gpu/drm/kmb/kmb_plane.c create mode 100644 drivers/gpu/drm/kmb/kmb_plane.h create mode 100644 drivers/gpu/drm/kmb/kmb_regs.h -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org
[PATCH 10/59] drm/kmb: Part 2 of Mipi Tx Initialization
Mipi TX Frame generator timing configuration
Compute and set frame generator timings like hactive, front porch,
back porch etc.
v2: minor code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 132 -
drivers/gpu/drm/kmb/kmb_regs.h | 37
2 files changed, 166 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 17e1383..1435ed8 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -411,6 +411,123 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private
*dev_priv,
return 0;
}
+static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv,
+ u8 frame_gen,
+ struct mipi_tx_frame_timing_cfg *fg_cfg)
+{
+ u32 sysclk;
+ /*float ppl_llp_ratio; */
+ u32 ppl_llp_ratio;
+ u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset;
+
+ /*Get system clock for blanking period cnfigurations */
+ /*TODO need to get system clock from clock driver */
+ /* Assume 700 Mhz system clock for now */
+ sysclk = 700;
+
+ /*ppl-pixel packing layer, llp-low level protocol
+* frame genartor timing parameters are clocked on the system clock
+* whereas as the equivalent parameters in the LLP blocks are clocked
+* on LLP Tx clock from the D-PHY - BYTE clock
+*/
+
+ /*multiply by 1000 to keep the precision */
+ ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) /
+ ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);
+
+ /*frame generator number of lines */
+ reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen);
+ kmb_write(dev_priv, reg_adr, fg_cfg->v_active);
+
+ /*vsync width */
+ /*
+*there are 2 registers for vsync width -VSA in lines for channels 0-3
+*REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1
+*REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3
+*/
+ offset = (frame_gen % 2) * 16;
+ reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen);
+ kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->vsync_width);
+
+ /*v backporch - same register config like vsync width */
+ reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen);
+ kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_backporch);
+
+ /*v frontporch - same register config like vsync width */
+ reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen);
+ kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_frontporch);
+
+ /*v active - same register config like vsync width */
+ reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen);
+ kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_active);
+
+ /*hsyc width */
+ reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen);
+ kmb_write(dev_priv, reg_adr,
+ (fg_cfg->hsync_width * ppl_llp_ratio) / 1000);
+
+ /*h backporch */
+ reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen);
+ kmb_write(dev_priv, reg_adr,
+ (fg_cfg->h_backporch * ppl_llp_ratio) / 1000);
+
+ /*h frontporch */
+ reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen);
+ kmb_write(dev_priv, reg_adr,
+ (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000);
+
+ /*h active */
+ reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen);
+ /*convert h_active which is wc in bytes to cycles */
+ val = (fg_cfg->h_active * sysclk * 1000) /
+ ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);
+ val /= 1000;
+ kmb_write(dev_priv, reg_adr, val);
+
+ /* llp hsync width */
+ reg_adr = MIPI_TXm_HS_LLP_HSYNC_WIDTHn(ctrl_no, frame_gen);
+ kmb_write(dev_priv, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8));
+
+ /* llp h backporch */
+ reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen);
+ kmb_write(dev_priv, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8));
+
+ /* llp h frontporch */
+ reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen);
+ kmb_write(dev_priv, reg_adr, fg_cfg->h_frontporch * (fg_cfg->bpp / 8));
+}
+
+static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen,
+ u8 active_lanes, u32 bpp, u32 wc,
+ u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg)
+{
+ u32 i, fg_num_lines = 0;
+ struct mipi_tx_frame_timing_cfg fg_t_cfg;
+
+ /*calculate the total frame generator number of lines based on it's
+* active sections
+*/
+ for (i = 0; i < MIPI_TX_FRAME_GEN_SECTIONS; i++) {
+ if (fg_cfg->sections[i] != NULL)
+ fg_num_lines += fg_cfg->sections[i]->height_lines;
+
[PATCH 08/59] drm/kmb: Added mipi_dsi_host initialization
Added mipi DSI host initialization functions
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 59 +++
drivers/gpu/drm/kmb/kmb_dsi.h | 4 +++
2 files changed, 63 insertions(+)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index b5c57e1..5e2aff1 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -85,12 +85,59 @@ static const struct drm_connector_funcs
kmb_dsi_connector_funcs = {
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
+static ssize_t kmb_dsi_host_transfer(struct mipi_dsi_host *host,
+const struct mipi_dsi_msg *msg)
+{
+ return 0;
+}
+
+static int kmb_dsi_host_attach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *dev)
+{
+ return 0;
+}
+
+static int kmb_dsi_host_detach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *dev)
+{
+ return 0;
+}
+
+static const struct mipi_dsi_host_ops kmb_dsi_host_ops = {
+ .attach = kmb_dsi_host_attach,
+ .detach = kmb_dsi_host_detach,
+ .transfer = kmb_dsi_host_transfer,
+};
+
+static struct kmb_dsi_host *kmb_dsi_host_init(struct kmb_dsi *kmb_dsi)
+{
+ struct kmb_dsi_host *host;
+ struct mipi_dsi_device *device;
+
+ host = kzalloc(sizeof(*host), GFP_KERNEL);
+ if (!host)
+ return NULL;
+
+ host->base.ops = _dsi_host_ops;
+ host->kmb_dsi = kmb_dsi;
+
+ device = kzalloc(sizeof(*device), GFP_KERNEL);
+ if (!device) {
+ kfree(host);
+ return NULL;
+ }
+ device->host = >base;
+ host->device = device;
+ return host;
+}
+
void kmb_dsi_init(struct drm_device *dev)
{
struct kmb_dsi *kmb_dsi;
struct drm_encoder *encoder;
struct kmb_connector *kmb_connector;
struct drm_connector *connector;
+ struct kmb_dsi_host *host;
kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL);
if (!kmb_dsi)
@@ -108,7 +155,19 @@ void kmb_dsi_init(struct drm_device *dev)
encoder = _dsi->base;
drm_encoder_init(dev, encoder, _dsi_funcs, DRM_MODE_ENCODER_DSI,
"MIPI-DSI");
+
+ host = kmb_dsi_host_init(kmb_dsi);
+ if (!host) {
+ drm_encoder_cleanup(encoder);
+ kfree(kmb_dsi);
+ kfree(kmb_connector);
+ }
+
drm_connector_init(dev, connector, _dsi_connector_funcs,
DRM_MODE_CONNECTOR_DSI);
drm_connector_helper_add(connector, _dsi_connector_helper_funcs);
+
+ connector->encoder = encoder;
+ drm_connector_attach_encoder(connector, encoder);
+
}
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h
index 3829360..88810ee 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.h
+++ b/drivers/gpu/drm/kmb/kmb_dsi.h
@@ -32,19 +32,23 @@
#include "kmb_drv.h"
struct kmb_connector;
+struct kmb_dsi_host;
struct kmb_dsi {
struct drm_encoder base;
struct kmb_connector *attached_connector;
+ struct kmb_dsi_host *dsi_host;
};
struct kmb_dsi_host {
struct mipi_dsi_host base;
struct kmb_dsi *kmb_dsi;
+ struct mipi_dsi_device *device;
};
struct kmb_connector {
struct drm_connector base;
+ struct drm_encoder *encoder;
struct drm_display_mode *fixed_mode;
};
--
2.7.4
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[PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register
During update plane, set the layer format, bpp, fifo level,
RGB order, Cb/Cr order etc. in the LAYER_CFG register.
v2: Return val in set_pixel and set_bpp instead of passing in pointer,
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 145 ++
drivers/gpu/drm/kmb/kmb_regs.h | 167
2 files changed, 298 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index b9d8d38..9f1e44f 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -53,6 +53,119 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
return 0;
}
+unsigned int set_pixel_format(u32 format)
+{
+ unsigned int val = 0;
+
+ switch (format) {
+ /*planar formats */
+ case DRM_FORMAT_YUV444:
+ val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU444:
+ val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_YUV422:
+ val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU422:
+ val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_YUV420:
+ val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_YVU420:
+ val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ case DRM_FORMAT_NV12:
+ val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE;
+ break;
+ case DRM_FORMAT_NV21:
+ val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE
+ | LCD_LAYER_CRCB_ORDER;
+ break;
+ /* packed formats */
+ case DRM_FORMAT_RGB332:
+ val = LCD_LAYER_FORMAT_RGB332;
+ break;
+ case DRM_FORMAT_XBGR:
+ val = LCD_LAYER_FORMAT_RGBX | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB:
+ val = LCD_LAYER_FORMAT_RGBA;
+ break;
+ case DRM_FORMAT_ABGR:
+ val = LCD_LAYER_FORMAT_RGBA | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_XRGB1555:
+ val = LCD_LAYER_FORMAT_XRGB1555;
+ break;
+ case DRM_FORMAT_XBGR1555:
+ val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB1555:
+ val = LCD_LAYER_FORMAT_RGBA1555;
+ break;
+ case DRM_FORMAT_ABGR1555:
+ val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_RGB565:
+ val = LCD_LAYER_FORMAT_RGB565;
+ break;
+ case DRM_FORMAT_BGR565:
+ val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_RGB888:
+ val = LCD_LAYER_FORMAT_RGB888;
+ break;
+ case DRM_FORMAT_BGR888:
+ val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_XRGB:
+ val = LCD_LAYER_FORMAT_RGBX;
+ break;
+ case DRM_FORMAT_XBGR:
+ val = LCD_LAYER_FORMAT_RGBX | LCD_LAYER_BGR_ORDER;
+ break;
+ case DRM_FORMAT_ARGB:
+ val = LCD_LAYER_FORMAT_RGBA;
+ break;
+ case DRM_FORMAT_ABGR:
+ val = LCD_LAYER_FORMAT_RGBA | LCD_LAYER_BGR_ORDER;
+ break;
+ }
+ return val;
+}
+
+unsigned int set_bits_per_pixel(const struct drm_format_info *format)
+{
+ int i;
+ u32 bpp = 0;
+ unsigned int val = 0;
+
+ for (i = 0; i < format->num_planes; i++)
+ bpp += 8*format->cpp[i];
+
+ switch (bpp) {
+ case 8:
+ val = LCD_LAYER_8BPP;
+ break;
+ case 16:
+ val = LCD_LAYER_16BPP;
+ break;
+ case 24:
+ val = LCD_LAYER_24BPP;
+ break;
+ case 32:
+ val = LCD_LAYER_32BPP;
+ break;
+ }
+ return val;
+}
+
static void kmb_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *state)
{
@@ -64,7 +177,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
unsigned int dma_len;
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
unsigned int dma_cfg;
- unsigned int
[PATCH 01/59] drm/kmb: Add support for KeemBay Display
Initial check-in for basic display driver for KeemBay family of SOCs.
This is not tested and does not work and also there are many TBDs in the
code which will be implemented in future commits.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile| 1 +
drivers/gpu/drm/kmb/Kconfig | 12 ++
drivers/gpu/drm/kmb/Makefile| 2 +
drivers/gpu/drm/kmb/kmb_crtc.c | 215 +++
drivers/gpu/drm/kmb/kmb_crtc.h | 59 ++
drivers/gpu/drm/kmb/kmb_drv.c | 372
drivers/gpu/drm/kmb/kmb_drv.h | 67 ++
drivers/gpu/drm/kmb/kmb_plane.c | 252 ++
drivers/gpu/drm/kmb/kmb_plane.h | 52 +
drivers/gpu/drm/kmb/kmb_regs.h | 460
11 files changed, 1494 insertions(+)
create mode 100644 drivers/gpu/drm/kmb/Kconfig
create mode 100644 drivers/gpu/drm/kmb/Makefile
create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.c
create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.h
create mode 100644 drivers/gpu/drm/kmb/kmb_drv.c
create mode 100644 drivers/gpu/drm/kmb/kmb_drv.h
create mode 100644 drivers/gpu/drm/kmb/kmb_plane.c
create mode 100644 drivers/gpu/drm/kmb/kmb_plane.h
create mode 100644 drivers/gpu/drm/kmb/kmb_regs.h
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index c4fd57d..5292574 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -275,6 +275,8 @@ source "drivers/gpu/drm/nouveau/Kconfig"
source "drivers/gpu/drm/i915/Kconfig"
+source "drivers/gpu/drm/kmb/Kconfig"
+
config DRM_VGEM
tristate "Virtual GEM provider"
depends on DRM
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 2c0e5a7..bdbdc63 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
obj-$(CONFIG_DRM_MGA) += mga/
obj-$(CONFIG_DRM_I810) += i810/
obj-$(CONFIG_DRM_I915) += i915/
+obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb/
obj-$(CONFIG_DRM_MGAG200) += mgag200/
obj-$(CONFIG_DRM_V3D) += v3d/
obj-$(CONFIG_DRM_VC4) += vc4/
diff --git a/drivers/gpu/drm/kmb/Kconfig b/drivers/gpu/drm/kmb/Kconfig
new file mode 100644
index 000..005a9962
--- /dev/null
+++ b/drivers/gpu/drm/kmb/Kconfig
@@ -0,0 +1,12 @@
+config DRM_KMB_DISPLAY
+ tristate "KEEMBAY DISPLAY"
+ depends on DRM && OF && (ARM || ARM64)
+ depends on COMMON_CLK
+ select DRM_KMS_HELPER
+ select DRM_KMS_CMA_HELPER
+ select DRM_GEM_CMA_HELPER
+ select VIDEOMODE_HELPERS
+ help
+ Choose this option if you have an KEEMBAY DISPLAY controller.
+
+ If M is selected the module will be called kmb-display.
diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile
new file mode 100644
index 000..be9f19c
--- /dev/null
+++ b/drivers/gpu/drm/kmb/Makefile
@@ -0,0 +1,2 @@
+kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o
+obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-display.o
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c
new file mode 100644
index 000..ab1fff8
--- /dev/null
+++ b/drivers/gpu/drm/kmb/kmb_crtc.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE
+ * SOFTWARE.
+ *
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "kmb_crtc.h"
+#include "kmb_drv.h"
+#include "kmb_plane.h"
+#include "kmb_regs.h"
+
+static void kmb_crtc_cleanup(struct drm_crtc *crtc)
+{
+ struct kmb_crtc *l_crtc = to_kmb_crtc(crtc);
+
+ drm_crtc_cleanup(crtc);
+ kfree(l_crtc);
+}
+
+static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+ struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc);
+
+
[PATCH 07/59] drm/kmb: Set OUT_FORMAT_CFG register
v2: code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 14 +-
drivers/gpu/drm/kmb/kmb_regs.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 886229a..f609283 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -228,7 +228,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
unsigned int dma_len;
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
unsigned int dma_cfg;
- unsigned int ctrl = 0, val = 0;
+ unsigned int ctrl = 0, val = 0, out_format = 0;
unsigned int src_w, src_h, crtc_x, crtc_y;
unsigned char plane_id = kmb_plane->id;
@@ -299,6 +299,18 @@ static void kmb_plane_atomic_update(struct drm_plane
*plane,
/* enable DMA */
kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
+ /* FIXME no doc on how to set output format - may need to change
+* this later
+*/
+ if (val & LCD_LAYER_BGR_ORDER)
+ out_format |= LCD_OUTF_BGR_ORDER;
+ else if (val & LCD_LAYER_CRCB_ORDER)
+ out_format |= LCD_OUTF_CRCB_ORDER;
+ /* do not interleave RGB channels for mipi Tx compatibility */
+ out_format |= LCD_OUTF_MIPI_RGB_MODE;
+ /* pixel format from LCD_LAYER_CFG */
+ out_format |= ((val >> 9) & 0x1F);
+ kmb_write(lcd, LCD_OUT_FORMAT_CFG, out_format);
}
static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = {
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 14466b8..299ab99 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -340,6 +340,7 @@
#define LCD_OUTF_BGR_ORDER (1 << 5)
#define LCD_OUTF_Y_ORDER (1 << 6)
#define LCD_OUTF_CRCB_ORDER (1 << 7)
+#define LCD_OUTF_MIPI_RGB_MODE (1 << 18)
#define LCD_HSYNC_WIDTH(0x4 * 0x801)
#define LCD_H_BACKPORCH(0x4 * 0x802)
--
2.7.4
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[PATCH 04/59] drm/kmb: Use biwise operators for register definitions
Did some general clean up and organization.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 3 +-
drivers/gpu/drm/kmb/kmb_regs.h | 852 +++--
2 files changed, 307 insertions(+), 548 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index fced630..ee4e3bd 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -133,8 +133,7 @@ static irqreturn_t kmb_irq(int irq, void *arg)
if (status & LCD_INT_VERT_COMP) {
/* read VSTATUS */
val = kmb_read(lcd, LCD_VSTATUS);
- /* BITS 13 and 14 */
- val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK) >> 12;
+ val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK);
switch (val) {
case LCD_VSTATUS_COMPARE_VSYNC:
case LCD_VSTATUS_COMPARE_BACKPORCH:
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index 9bf2b9f..14466b8 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -26,35 +26,181 @@
#ifndef __KMB_REGS_H__
#define __KMB_REGS_H__
-/*LCD CONTROLLER REGISTERS */
-#define LCD_CONTROL(0x4 * 0x000)
-#define LCD_INT_STATUS (0x4 * 0x001)
-#define LCD_INT_ENABLE (0x4 * 0x002)
-#define LCD_INT_CLEAR (0x4 * 0x003)
-#define LCD_LINE_COUNT (0x4 * 0x004)
-#define LCD_LINE_COMPARE (0x4 * 0x005)
-#define LCD_VSTATUS(0x4 * 0x006)
-#define LCD_VSTATUS_COMPARE(0x4 * 0x007)
-#define LCD_SCREEN_WIDTH (0x4 * 0x008)
-#define LCD_SCREEN_HEIGHT (0x4 * 0x009)
-#define LCD_FIELD_INT_CFG (0x4 * 0x00a)
-#define LCD_FIFO_FLUSH (0x4 * 0x00b)
-#define LCD_BG_COLOUR_LS (0x4 * 0x00c)
-#define LCD_BG_COLOUR_MS (0x4 * 0x00d)
-#define LCD_RAM_CFG(0x4 * 0x00e)
+#define ENABLE 1
+/***
+ *LCD controller control register defines
+ ***/
+#define LCD_CONTROL(0x4 * 0x000)
+#define LCD_CTRL_PROGRESSIVE (0<<0)
+#define LCD_CTRL_INTERLACED (1<<0)
+#define LCD_CTRL_ENABLE (1<<1)
+#define LCD_CTRL_VL1_ENABLE (1<<2)
+#define LCD_CTRL_VL2_ENABLE (1<<3)
+#define LCD_CTRL_GL1_ENABLE (1<<4)
+#define LCD_CTRL_GL2_ENABLE (1<<5)
+#define LCD_CTRL_ALPHA_BLEND_VL1 (0<<6)
+#define LCD_CTRL_ALPHA_BLEND_VL2 (1<<6)
+#define LCD_CTRL_ALPHA_BLEND_GL1 (2<<6)
+#define LCD_CTRL_ALPHA_BLEND_GL2 (3<<6)
+#define LCD_CTRL_ALPHA_TOP_VL1 (0<<8)
+#define LCD_CTRL_ALPHA_TOP_VL2 (1<<8)
+#define LCD_CTRL_ALPHA_TOP_GL1 (2<<8)
+#define LCD_CTRL_ALPHA_TOP_GL2 (3<<8)
+#define LCD_CTRL_ALPHA_MIDDLE_VL1(0<<10)
+#define LCD_CTRL_ALPHA_MIDDLE_VL2(1<<10)
+#define LCD_CTRL_ALPHA_MIDDLE_GL1(2<<10)
+#define LCD_CTRL_ALPHA_MIDDLE_GL2(3<<10)
+#define LCD_CTRL_ALPHA_BOTTOM_VL1(0<<12)
+#define LCD_CTRL_ALPHA_BOTTOM_VL2(1<<12)
+#define LCD_CTRL_ALPHA_BOTTOM_GL1(2<<12)
+#define LCD_CTRL_ALPHA_BOTTOM_GL2(3<<12)
+#define LCD_CTRL_TIM_GEN_ENABLE (1<<14)
+#define LCD_CTRL_DISPLAY_MODE_ONE_SHOT (1<<15)
+#define LCD_CTRL_PWM0_EN (1<<16)
+#define LCD_CTRL_PWM1_EN (1<<17)
+#define LCD_CTRL_PWM2_EN (1<<18)
+#define LCD_CTRL_OUTPUT_DISABLED (0<<19)
+#define LCD_CTRL_OUTPUT_ENABLED (1<<19)
+#define LCD_CTRL_BPORCH_ENABLE (1<<21)
+#define LCD_CTRL_FPORCH_ENABLE (1<<22)
+#define LCD_CTRL_PIPELINE_DMA(1<<28)
+
+/*interrupts */
+#define LCD_INT_STATUS (0x4 * 0x001)
+#define LCD_INT_EOF (1<<0)
+#define LCD_INT_LINE_CMP (1<<1)
+#define LCD_INT_VERT_COMP(1<<2)
+#define LAYER0_DMA_DONE_BIT (1<<3)
+#define LAYER0_DMA_IDLE_BIT (1<<4)
+#define LAYER0_DMA_OVERFLOW_BIT (1<<5)
+#define LAYER0_DMA_FIFO_UNDEFLOW_BIT (1<<6)
+#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7)
+#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8)
+#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9)
+#define
[PATCH 05/59] drm/kmb: Updated kmb_plane_atomic_check
Check if format is supported and size is within limits.
v2: simplified the code as per code review
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 111 +++-
1 file changed, 65 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c
index 9f1e44f..886229a 100644
--- a/drivers/gpu/drm/kmb/kmb_plane.c
+++ b/drivers/gpu/drm/kmb/kmb_plane.c
@@ -41,15 +41,66 @@
#include "kmb_regs.h"
#include "kmb_drv.h"
+/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/
+static const u32 kmb_formats_g[] = {
+ DRM_FORMAT_RGB332,
+ DRM_FORMAT_XRGB, DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB, DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555,
+ DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_RGB565, DRM_FORMAT_BGR565,
+ DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
+ DRM_FORMAT_XRGB, DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB, DRM_FORMAT_ABGR,
+};
+
+#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g))
+#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v))
+
+/* video layer ( 0 & 1) formats, packed and planar formats are supported */
+static const u32 kmb_formats_v[] = {
+ /* packed formats */
+ DRM_FORMAT_RGB332,
+ DRM_FORMAT_XRGB, DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB, DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555,
+ DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_RGB565, DRM_FORMAT_BGR565,
+ DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
+ DRM_FORMAT_XRGB, DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB, DRM_FORMAT_ABGR,
+ /*planar formats */
+ DRM_FORMAT_YUV420, DRM_FORMAT_YVU420,
+ DRM_FORMAT_YUV422, DRM_FORMAT_YVU422,
+ DRM_FORMAT_YUV444, DRM_FORMAT_YVU444,
+ DRM_FORMAT_NV12, DRM_FORMAT_NV21,
+};
+
+static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
+{
+ int i;
+
+ for (i = 0; i < plane->format_count; i++) {
+ if (plane->format_types[i] == format)
+ return 0;
+ }
+ return -EINVAL;
+}
+
static int kmb_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
-/* TBD below structure will be used for implementation later
- * struct drm_crtc_state *crtc_state;
- */
- /* TBD */
- /* Plane based checking */
+ struct drm_framebuffer *fb;
+ int ret;
+
+ fb = state->fb;
+ ret = check_pixel_format(plane, fb->format->format);
+ if (ret)
+ return ret;
+
+ if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT)
+ return -EINVAL;
return 0;
}
@@ -58,36 +109,36 @@ unsigned int set_pixel_format(u32 format)
unsigned int val = 0;
switch (format) {
- /*planar formats */
+ /*planar formats */
case DRM_FORMAT_YUV444:
val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE;
break;
case DRM_FORMAT_YVU444:
val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE
- | LCD_LAYER_CRCB_ORDER;
+ | LCD_LAYER_CRCB_ORDER;
break;
case DRM_FORMAT_YUV422:
val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE;
break;
case DRM_FORMAT_YVU422:
val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE
- | LCD_LAYER_CRCB_ORDER;
+ | LCD_LAYER_CRCB_ORDER;
break;
case DRM_FORMAT_YUV420:
val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE;
break;
case DRM_FORMAT_YVU420:
val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE
- | LCD_LAYER_CRCB_ORDER;
+ | LCD_LAYER_CRCB_ORDER;
break;
case DRM_FORMAT_NV12:
val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE;
break;
case DRM_FORMAT_NV21:
val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE
- | LCD_LAYER_CRCB_ORDER;
+ | LCD_LAYER_CRCB_ORDER;
break;
- /* packed formats */
+ /* packed formats */
case DRM_FORMAT_RGB332:
val = LCD_LAYER_FORMAT_RGB332;
break;
@@ -147,7 +198,7 @@ unsigned int set_bits_per_pixel(const struct
drm_format_info *format)
unsigned int val = 0;
for (i = 0; i < format->num_planes; i++)
- bpp += 8*format->cpp[i];
+ bpp += 8 * format->cpp[i];
switch (bpp) {
case 8:
@@ -191,8 +242,8 @@ static void kmb_plane_atomic_update(struct
[PATCH 06/59] drm/kmb: Initial check-in for Mipi DSI
Basic frame work for mipi encoder and connector.
More hardware specific details will be added in the future commits.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/Makefile | 2 +-
drivers/gpu/drm/kmb/kmb_drv.c | 2 +
drivers/gpu/drm/kmb/kmb_dsi.c | 114 ++
drivers/gpu/drm/kmb/kmb_dsi.h | 58 +
4 files changed, 175 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.c
create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.h
diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile
index be9f19c..8102bc9 100644
--- a/drivers/gpu/drm/kmb/Makefile
+++ b/drivers/gpu/drm/kmb/Makefile
@@ -1,2 +1,2 @@
-kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o
+kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o kmb_dsi.o
obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-display.o
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index ee4e3bd..24e7c2b 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -47,6 +47,7 @@
#include "kmb_regs.h"
#include "kmb_crtc.h"
#include "kmb_plane.h"
+#include "kmb_dsi.h"
static int kmb_load(struct drm_device *drm, unsigned long flags)
{
@@ -83,6 +84,7 @@ static int kmb_load(struct drm_device *drm, unsigned long
flags)
goto setup_fail;
}
+ kmb_dsi_init(drm);
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
if (ret < 0) {
DRM_ERROR("failed to install IRQ handler\n");
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
new file mode 100644
index 000..b5c57e1
--- /dev/null
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE
+ * SOFTWARE.
+ *
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "kmb_drv.h"
+#include "kmb_dsi.h"
+
+static enum drm_mode_status
+kmb_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ return MODE_OK;
+}
+
+static int kmb_dsi_get_modes(struct drm_connector *connector)
+{
+ struct drm_display_mode *mode;
+ struct kmb_connector *kmb_connector = to_kmb_connector(connector);
+
+ mode = drm_mode_duplicate(connector->dev, kmb_connector->fixed_mode);
+ drm_mode_probed_add(connector, mode);
+ return 1;
+}
+
+static void kmb_dsi_connector_destroy(struct drm_connector *connector)
+{
+ struct kmb_connector *kmb_connector = to_kmb_connector(connector);
+
+ drm_connector_cleanup(connector);
+ kfree(kmb_connector);
+}
+
+static void kmb_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+ struct kmb_dsi *kmb_dsi = to_kmb_dsi(encoder);
+
+ drm_encoder_cleanup(encoder);
+ kfree(kmb_dsi);
+}
+
+static const struct drm_encoder_funcs kmb_dsi_funcs = {
+ .destroy = kmb_dsi_encoder_destroy,
+};
+
+static const struct
+drm_connector_helper_funcs kmb_dsi_connector_helper_funcs = {
+ .get_modes = kmb_dsi_get_modes,
+ .mode_valid = kmb_dsi_mode_valid,
+};
+
+static const struct drm_connector_funcs kmb_dsi_connector_funcs = {
+ .destroy = kmb_dsi_connector_destroy,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+};
+
+void kmb_dsi_init(struct drm_device *dev)
+{
+ struct kmb_dsi *kmb_dsi;
+ struct drm_encoder *encoder;
+ struct kmb_connector *kmb_connector;
+ struct drm_connector *connector;
+
+ kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL);
+ if (!kmb_dsi)
+ return;
+
+ kmb_connector =
[drm:not-butter 9/12] drivers/gpu/drm/i915/ttm/i915_ttm_bo_list.h:9:29: error: field 'tv' has incomplete type
tree: git://people.freedesktop.org/~airlied/linux.git not-butter
head: f9de02ab2d4b7fc8d05e5fff0d5b4d8e474bbba5
commit: 94b5191f7aeb937b75a085b9804da8072a2e1c96 [9/12] i915/ttm: start adding
execbuffer
config: i386-randconfig-m021-20200630 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:578: warning: Function
parameter or member 'clock_table' not described in 'renoir_get_dpm_clock_table'
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c: In function
'navi10_is_dpm_running':
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1141:6: warning:
variable 'ret' set but not used [-Wunused-but-set-variable]
1141 | int ret = 0;
| ^~~
In file included from
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:32:
At top level:
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smu_v11_0.h:68:43: warning:
'smu11_thermal_policy' defined but not used [-Wunused-const-variable=]
68 | static const struct smu_temperature_range smu11_thermal_policy[] =
| ^~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:26:
drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:190:18: warning:
'sched_policy' defined but not used [-Wunused-const-variable=]
190 | static const int sched_policy = KFD_SCHED_POLICY_HWS;
| ^~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33,
from
drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from
drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:65,
from
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:26:
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning:
'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
|^~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning:
'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=]
75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
|^~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning:
'dc_fixpt_e' defined but not used [-Wunused-const-variable=]
74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
|^~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning:
'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning:
'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning:
'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
|^
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c: In function
'vega20_is_dpm_running':
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:2852:6: warning:
variable 'ret' set but not used [-Wunused-but-set-variable]
2852 | int ret = 0;
| ^~~
In file included from
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:30:
At top level:
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smu_v11_0.h:68:43: warning:
'smu11_thermal_policy' defined but not used [-Wunused-const-variable=]
68 | static const struct smu_temperature_range smu11_thermal_policy[] =
| ^~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:25:
drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:190:18: warning:
'sched_policy' defined but not used [-Wunused-const-variable=]
190 | static const int sched_policy = KFD_SCHED_POLICY_HWS;
| ^~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33,
from
drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from
drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgp
Re: [PATCH v2] dt-bindings: backlight: Convert common backlight bindings to DT schema
On Tue, Jun 30, 2020 at 02:01:11PM -0600, Rob Herring wrote:
> Convert the common GPIO, LED, and PWM backlight bindings to DT schema
> format.
>
> Given there's only 2 common properties and the descriptions are slightly
> different, I opted to not create a common backlight schema.
>
> Cc: Lee Jones
> Cc: Daniel Thompson
> Cc: Jingoo Han
> Cc: Sam Ravnborg
> Signed-off-by: Rob Herring
Acked-by: Sam Ravnborg
> ---
> v2:
> - Reformat descriptions
> - drop default-brightness-level dependency on brightness-levels for
> led-backlight
> ---
> .../leds/backlight/gpio-backlight.txt | 16 ---
> .../leds/backlight/gpio-backlight.yaml| 41 +++
> .../bindings/leds/backlight/led-backlight.txt | 28 -
> .../leds/backlight/led-backlight.yaml | 57 ++
> .../bindings/leds/backlight/pwm-backlight.txt | 61 --
> .../leds/backlight/pwm-backlight.yaml | 104 ++
> 6 files changed, 202 insertions(+), 105 deletions(-)
> delete mode 100644
> Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
> create mode 100644
> Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
> delete mode 100644
> Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
> create mode 100644
> Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml
> delete mode 100644
> Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
> create mode 100644
> Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
> b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
> deleted file mode 100644
> index 321be6640533..
> --- a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -gpio-backlight bindings
> -
> -Required properties:
> - - compatible: "gpio-backlight"
> - - gpios: describes the gpio that is used for enabling/disabling the
> backlight.
> -refer to bindings/gpio/gpio.txt for more details.
> -
> -Optional properties:
> - - default-on: enable the backlight at boot.
> -
> -Example:
> - backlight {
> - compatible = "gpio-backlight";
> - gpios = < 4 GPIO_ACTIVE_HIGH>;
> - default-on;
> - };
> diff --git
> a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
> b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
> new file mode 100644
> index ..75cc569b9c55
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/leds/backlight/gpio-backlight.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: gpio-backlight bindings
> +
> +maintainers:
> + - Lee Jones
> + - Daniel Thompson
> + - Jingoo Han
> +
> +properties:
> + compatible:
> +const: gpio-backlight
> +
> + gpios:
> +description: The gpio that is used for enabling/disabling the backlight.
> +maxItems: 1
> +
> + default-on:
> +description: enable the backlight at boot.
> +type: boolean
> +
> +required:
> + - compatible
> + - gpios
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +backlight {
> +compatible = "gpio-backlight";
> +gpios = < 4 GPIO_ACTIVE_HIGH>;
> +default-on;
> +};
> +
> +...
> diff --git
> a/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
> b/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
> deleted file mode 100644
> index 4c7dfbe7f67a..
> --- a/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -led-backlight bindings
> -
> -This binding is used to describe a basic backlight device made of LEDs.
> -It can also be used to describe a backlight device controlled by the output
> of
> -a LED driver.
> -
> -Required properties:
> - - compatible: "led-backlight"
> - - leds: a list of LEDs
> -
> -Optional properties:
> - - brightness-levels: Array of distinct brightness levels. The levels must
> be
> - in the range accepted by the underlying LED devices.
> - This is used to translate a backlight brightness level
> - into a LED brightness level. If it is not provided,
> the
> - identity mapping is used.
> -
> - - default-brightness-level: The default brightness level.
> -
> -Example:
> -
> - backlight {
> - compatible = "led-backlight";
> -
> - leds = <>, <>;
> - brightness-levels = <0 4 8 16 32 64 128 255>;
> - default-brightness-level = <6>;
> - };
> diff --git
> a/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml
>
Re: [PATCH v2] dt-bindings: display: Convert connectors to DT schema
On Tue, Jun 30, 2020 at 02:02:16PM -0600, Rob Herring wrote:
> Convert the analog TV, DVI, HDMI, and VGA connector bindings to DT schema
> format.
>
> Cc: Sam Ravnborg
> Cc: Laurent Pinchart
> Cc: Maxime Ripard
> Signed-off-by: Rob Herring
Acked-by: Sam Ravnborg
> ---
> v2:
> - Make Laurent maintainer
> - Add missing port and compatible required
> - Drop copy-n-paste 'type' from dvi-connector
> - Use 4 space indent on examples
> ---
> .../display/connector/analog-tv-connector.txt | 31
> .../connector/analog-tv-connector.yaml| 52 ++
> .../display/connector/dvi-connector.txt | 36 --
> .../display/connector/dvi-connector.yaml | 70 +++
> .../display/connector/hdmi-connector.txt | 31
> .../display/connector/hdmi-connector.yaml | 64 +
> .../display/connector/vga-connector.txt | 36 --
> .../display/connector/vga-connector.yaml | 46
> 8 files changed, 232 insertions(+), 134 deletions(-)
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/dvi-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/dvi-connector.yaml
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml
> delete mode 100644
> Documentation/devicetree/bindings/display/connector/vga-connector.txt
> create mode 100644
> Documentation/devicetree/bindings/display/connector/vga-connector.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> deleted file mode 100644
> index 883bcb2604c7..
> ---
> a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -Analog TV Connector
> -===
> -
> -Required properties:
> -- compatible: "composite-video-connector" or "svideo-connector"
> -
> -Optional properties:
> -- label: a symbolic name for the connector
> -- sdtv-standards: limit the supported TV standards on a connector to the
> given
> - ones. If not specified all TV standards are allowed.
> - Possible TV standards are defined in
> - include/dt-bindings/display/sdtv-standards.h.
> -
> -Required nodes:
> -- Video port for TV input
> -
> -Example
>
> -#include
> -
> -tv: connector {
> - compatible = "composite-video-connector";
> - label = "tv";
> - sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
> -
> - port {
> - tv_connector_in: endpoint {
> - remote-endpoint = <_out>;
> - };
> - };
> -};
> diff --git
> a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
>
> b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
> new file mode 100644
> index ..eebe88fed999
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id:
> http://devicetree.org/schemas/display/connector/analog-tv-connector.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog TV Connector
> +
> +maintainers:
> + - Laurent Pinchart
> +
> +properties:
> + compatible:
> +enum:
> + - composite-video-connector
> + - svideo-connector
> +
> + label: true
> +
> + sdtv-standards:
> +description:
> + Limit the supported TV standards on a connector to the given ones. If
> + not specified all TV standards are allowed. Possible TV standards are
> + defined in include/dt-bindings/display/sdtv-standards.h.
> +$ref: /schemas/types.yaml#/definitions/uint32
> +
> + port:
> +description: Connection to controller providing analog TV signals
> +
> +required:
> + - compatible
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +
> +connector {
> +compatible = "composite-video-connector";
> +label = "tv";
> +sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
> +
> +port {
> +tv_connector_in: endpoint {
> +remote-endpoint = <_out>;
> +};
> +};
> +};
> +
> +...
> diff --git
> a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
> b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
> deleted file mode 100644
> index 207e42e9eba0..
> ---
RE: [RFC PATCH v2 0/3] RDMA: add dma-buf support
> -Original Message- > From: Jason Gunthorpe > Sent: Tuesday, June 30, 2020 12:17 PM > To: Xiong, Jianxin > Cc: linux-r...@vger.kernel.org; Doug Ledford ; Sumit > Semwal ; Leon Romanovsky > ; Vetter, Daniel ; Christian Koenig > ; dri- > de...@lists.freedesktop.org > Subject: Re: [RFC PATCH v2 0/3] RDMA: add dma-buf support > > > > > > > On Tue, Jun 30, 2020 at 05:21:33PM +, Xiong, Jianxin wrote: > > > > > > Heterogeneous Memory Management (HMM) utilizes > > > > > > mmu_interval_notifier and ZONE_DEVICE to support shared > > > > > > virtual address space and page migration between system memory > > > > > > and device memory. HMM doesn't support pinning device memory > > > > > > because pages located on device must be able to migrate to > > > > > > system memory when accessed by CPU. Peer-to-peer access is > > > > > > possible if the peer can handle page fault. For RDMA, that means > > > > > > the NIC must support on-demand paging. > > > > > > > > > > peer-peer access is currently not possible with hmm_range_fault(). > > > > > > > > Currently hmm_range_fault() always sets the cpu access flag and > > > > device private pages are migrated to the system RAM in the fault > > > > handler. > > > > However, it's possible to have a modified code flow to keep the > > > > device private page info for use with peer to peer access. > > > > > > Sort of, but only within the same device, RDMA or anything else generic > > > can't reach inside a DEVICE_PRIVATE and extract anything > useful. > > > > But pfn is supposed to be all that is needed. > > Needed for what? The PFN of the DEVICE_PRIVATE pages is useless for anything. Hmm. I thought the pfn corresponds to the address in the BAR range. I could be wrong here. > > > > Well, what do you want to happen here? The RDMA parts are > > > reasonable, but I don't want to add new functionality without a > > > purpose - the other parts need to be settled out first. > > > > At the RDMA side, we mainly want to check if the changes are > > acceptable. For example, the part about adding 'fd' to the device ops > > and the ioctl interface. All the previous comments are very helpful > > for us to refine the patch so that we can be ready when GPU side > > support becomes available. > > Well, I'm not totally happy with the way the umem and the fd is handled so > roughly and incompletely.. Yes, this feedback is very helpful. Will work on improving the code. > > > > Hum. This is not actually so hard to do. The whole dma buf proposal > > > would make a lot more sense if the 'dma buf MR' had to be the > > > dynamic kind and the driver had to provide the faulting. It would > > > not be so hard to change mlx5 to be able to work like this, perhaps. > > > (the locking might be a bit tricky though) > > > > The main issue is that not all NICs support ODP. > > Sure, but there is lots of infrastructure work here to be done on dma buf, > having a correct consumer in the form of ODP might be helpful to > advance it. Good point. Thanks. > > Jason ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2] dt-bindings: display: Convert connectors to DT schema
Convert the analog TV, DVI, HDMI, and VGA connector bindings to DT schema
format.
Cc: Sam Ravnborg
Cc: Laurent Pinchart
Cc: Maxime Ripard
Signed-off-by: Rob Herring
---
v2:
- Make Laurent maintainer
- Add missing port and compatible required
- Drop copy-n-paste 'type' from dvi-connector
- Use 4 space indent on examples
---
.../display/connector/analog-tv-connector.txt | 31
.../connector/analog-tv-connector.yaml| 52 ++
.../display/connector/dvi-connector.txt | 36 --
.../display/connector/dvi-connector.yaml | 70 +++
.../display/connector/hdmi-connector.txt | 31
.../display/connector/hdmi-connector.yaml | 64 +
.../display/connector/vga-connector.txt | 36 --
.../display/connector/vga-connector.yaml | 46
8 files changed, 232 insertions(+), 134 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
create mode 100644
Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
delete mode 100644
Documentation/devicetree/bindings/display/connector/dvi-connector.txt
create mode 100644
Documentation/devicetree/bindings/display/connector/dvi-connector.yaml
delete mode 100644
Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
create mode 100644
Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml
delete mode 100644
Documentation/devicetree/bindings/display/connector/vga-connector.txt
create mode 100644
Documentation/devicetree/bindings/display/connector/vga-connector.yaml
diff --git
a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
deleted file mode 100644
index 883bcb2604c7..
---
a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Analog TV Connector
-===
-
-Required properties:
-- compatible: "composite-video-connector" or "svideo-connector"
-
-Optional properties:
-- label: a symbolic name for the connector
-- sdtv-standards: limit the supported TV standards on a connector to the given
- ones. If not specified all TV standards are allowed.
- Possible TV standards are defined in
- include/dt-bindings/display/sdtv-standards.h.
-
-Required nodes:
-- Video port for TV input
-
-Example
-#include
-
-tv: connector {
- compatible = "composite-video-connector";
- label = "tv";
- sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
-
- port {
- tv_connector_in: endpoint {
- remote-endpoint = <_out>;
- };
- };
-};
diff --git
a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
new file mode 100644
index ..eebe88fed999
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/connector/analog-tv-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog TV Connector
+
+maintainers:
+ - Laurent Pinchart
+
+properties:
+ compatible:
+enum:
+ - composite-video-connector
+ - svideo-connector
+
+ label: true
+
+ sdtv-standards:
+description:
+ Limit the supported TV standards on a connector to the given ones. If
+ not specified all TV standards are allowed. Possible TV standards are
+ defined in include/dt-bindings/display/sdtv-standards.h.
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ port:
+description: Connection to controller providing analog TV signals
+
+required:
+ - compatible
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+connector {
+compatible = "composite-video-connector";
+label = "tv";
+sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
+
+port {
+tv_connector_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+};
+
+...
diff --git
a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
deleted file mode 100644
index 207e42e9eba0..
--- a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-DVI Connector
-==
-
-Required properties:
-- compatible: "dvi-connector"
-
-Optional properties:
-- label: a symbolic name for the connector
-- ddc-i2c-bus: phandle to the i2c bus that is connected to DVI DDC
-- analog: the connector has DVI analog pins
-- digital: the connector has DVI digital pins
--
[PATCH v2] dt-bindings: backlight: Convert common backlight bindings to DT schema
Convert the common GPIO, LED, and PWM backlight bindings to DT schema
format.
Given there's only 2 common properties and the descriptions are slightly
different, I opted to not create a common backlight schema.
Cc: Lee Jones
Cc: Daniel Thompson
Cc: Jingoo Han
Cc: Sam Ravnborg
Signed-off-by: Rob Herring
---
v2:
- Reformat descriptions
- drop default-brightness-level dependency on brightness-levels for
led-backlight
---
.../leds/backlight/gpio-backlight.txt | 16 ---
.../leds/backlight/gpio-backlight.yaml| 41 +++
.../bindings/leds/backlight/led-backlight.txt | 28 -
.../leds/backlight/led-backlight.yaml | 57 ++
.../bindings/leds/backlight/pwm-backlight.txt | 61 --
.../leds/backlight/pwm-backlight.yaml | 104 ++
6 files changed, 202 insertions(+), 105 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
create mode 100644
Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
delete mode 100644
Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
create mode 100644
Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml
delete mode 100644
Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
create mode 100644
Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml
diff --git
a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
deleted file mode 100644
index 321be6640533..
--- a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-gpio-backlight bindings
-
-Required properties:
- - compatible: "gpio-backlight"
- - gpios: describes the gpio that is used for enabling/disabling the
backlight.
-refer to bindings/gpio/gpio.txt for more details.
-
-Optional properties:
- - default-on: enable the backlight at boot.
-
-Example:
- backlight {
- compatible = "gpio-backlight";
- gpios = < 4 GPIO_ACTIVE_HIGH>;
- default-on;
- };
diff --git
a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
new file mode 100644
index ..75cc569b9c55
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/backlight/gpio-backlight.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: gpio-backlight bindings
+
+maintainers:
+ - Lee Jones
+ - Daniel Thompson
+ - Jingoo Han
+
+properties:
+ compatible:
+const: gpio-backlight
+
+ gpios:
+description: The gpio that is used for enabling/disabling the backlight.
+maxItems: 1
+
+ default-on:
+description: enable the backlight at boot.
+type: boolean
+
+required:
+ - compatible
+ - gpios
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+backlight {
+compatible = "gpio-backlight";
+gpios = < 4 GPIO_ACTIVE_HIGH>;
+default-on;
+};
+
+...
diff --git a/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
b/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
deleted file mode 100644
index 4c7dfbe7f67a..
--- a/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-led-backlight bindings
-
-This binding is used to describe a basic backlight device made of LEDs.
-It can also be used to describe a backlight device controlled by the output of
-a LED driver.
-
-Required properties:
- - compatible: "led-backlight"
- - leds: a list of LEDs
-
-Optional properties:
- - brightness-levels: Array of distinct brightness levels. The levels must be
- in the range accepted by the underlying LED devices.
- This is used to translate a backlight brightness level
- into a LED brightness level. If it is not provided, the
- identity mapping is used.
-
- - default-brightness-level: The default brightness level.
-
-Example:
-
- backlight {
- compatible = "led-backlight";
-
- leds = <>, <>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- };
diff --git
a/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml
b/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml
new file mode 100644
index ..625082bf3892
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/backlight/led-backlight.yaml#
+$schema:
[PATCH v3] arm64: dts: qcom: sc7180: Add Display Port dt node
Add DP device node on sc7180.
Changes in v2:
- Add assigned-clocks and assigned-clock-parents
- Remove cell-index and pixel_rcg
- Change compatible to qcom,sc7180-dp
Changes in v3:
- Update commit text
- Make DP child node of MDSS
- Remove data-lanes property from SOC dts
- Disable DP node in SOC dts
- Assign DP to Port2 in MDP node
- Add MDSS AHB clock in DP device node
This patch depends-on:
https://patchwork.freedesktop.org/series/78953/
Signed-off-by: Tanmay Shah
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 49 ++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 31b9217bb5bf..271d55db62ab 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2371,6 +2371,13 @@ dpu_intf1_out: endpoint {
remote-endpoint =
<_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
};
};
@@ -2440,6 +2447,44 @@ dsi_phy: dsi-phy@ae94400 {
status = "disabled";
};
+
+ msm_dp: displayport-controller@ae9{
+ status = "disabled";
+ compatible = "qcom,sc7180-dp";
+
+ reg = <0 0xae9 0 0x1400>;
+ reg-names = "dp_controller";
+
+ interrupt-parent = <>;
+ interrupts = <12 0>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_DP_AUX_CLK>,
+< DISP_CC_MDSS_DP_LINK_CLK>,
+<
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+< DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux",
"ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <_dp 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint =
<_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+ };
};
dispcc: clock-controller@af0 {
@@ -2449,8 +2494,8 @@ dispcc: clock-controller@af0 {
< GCC_DISP_GPLL0_CLK_SRC>,
<_phy 0>,
<_phy 1>,
-<0>,
-<0>;
+<_dp 0>,
+<_dp 1>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"dsi0_phy_pll_out_byteclk",
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[drm:not-butter 7/12] drivers/gpu/drm/i915/display/intel_fbdev.c:350:30: error: format '%x' expects argument of type 'unsigned int', but argument 6 has type 'u64' {aka 'long long unsigned int'}
tree: git://people.freedesktop.org/~airlied/linux.git not-butter
head: f9de02ab2d4b7fc8d05e5fff0d5b4d8e474bbba5
commit: d6c6b836c1d7cca965338f63eda9db568eb9c78e [7/12] i915/ttm: fbcon works
config: i386-randconfig-m021-20200630 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
|^~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning:
'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning:
'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning:
'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
|^
In file included from :
drivers/gpu/drm/i915/ttm/i915_ttm.h:8:26: error: 'struct drm_i915_private'
declared inside parameter list will not be visible outside of this definition
or declaration [-Werror]
8 | int i915_ttm_init(struct drm_i915_private *i915);
| ^~~~
drivers/gpu/drm/i915/ttm/i915_ttm.h:9:27: error: 'struct drm_i915_private'
declared inside parameter list will not be visible outside of this definition
or declaration [-Werror]
9 | void i915_ttm_fini(struct drm_i915_private *i915);
| ^~~~
drivers/gpu/drm/i915/ttm/i915_ttm.h: In function 'i915_ttm_bo_reserve':
drivers/gpu/drm/i915/ttm/i915_ttm.h:30:34: error: implicit declaration of
function 'to_i915_ttm_dev' [-Werror=implicit-function-declaration]
30 | struct drm_i915_private *i915 = to_i915_ttm_dev(bo->tbo.bdev);
| ^~~
drivers/gpu/drm/i915/ttm/i915_ttm.h:30:34: error: initialization of 'struct
drm_i915_private *' from 'int' makes pointer from integer without a cast
[-Werror=int-conversion]
In file included from include/linux/device.h:15,
from include/drm/drm_print.h:32,
from include/drm/drm_mm.h:49,
from include/drm/drm_vma_manager.h:26,
from include/drm/drm_gem.h:40,
from include/drm/ttm/ttm_bo_api.h:34,
from drivers/gpu/drm/i915/ttm/i915_ttm_object_types.h:4,
from drivers/gpu/drm/i915/ttm/i915_ttm.h:4,
from :
drivers/gpu/drm/i915/ttm/i915_ttm.h:36:16: error: dereferencing pointer to
incomplete type 'struct drm_i915_private'
36 |dev_err(i915->drm.dev, "%p reserve failed\n", bo);
|^~
include/linux/dev_printk.h:104:11: note: in definition of macro 'dev_err'
104 | _dev_err(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~
In file included from :
drivers/gpu/drm/i915/ttm/i915_ttm.h: In function
'i915_ttm_mem_type_to_region':
drivers/gpu/drm/i915/ttm/i915_ttm.h:57:10: error: 'REGION_LMEM' undeclared
(first use in this function); did you mean 'REGION_MIXED'?
57 | return REGION_LMEM;
| ^~~
| REGION_MIXED
drivers/gpu/drm/i915/ttm/i915_ttm.h:57:10: note: each undeclared identifier
is reported only once for each function it appears in
drivers/gpu/drm/i915/ttm/i915_ttm.h:59:10: error: 'REGION_SMEM' undeclared
(first use in this function); did you mean 'REGION_MIXED'?
59 | return REGION_SMEM;
| ^~~
| REGION_MIXED
drivers/gpu/drm/i915/ttm/i915_ttm.h: At top level:
drivers/gpu/drm/i915/ttm/i915_ttm.h:68:40: error: 'struct drm_i915_private'
declared inside parameter list will not be visible outside of this definition
or declaration [-Werror]
68 | int i915_ttm_bo_create_reserved(struct drm_i915_private *i915,
|^~~~
drivers/gpu/drm/i915/ttm/i915_ttm.h:73:54: error: 'struct drm_i915_private'
declared inside parameter list will not be visible outside of this definition
or declaration [-Werror]
73 | uint32_t i915_ttm_bo_get_preferred_pin_region(struct
drm_i915_private *i915,
| ^~~~
drivers/gpu/drm/i915/ttm/i915_ttm.h:76:38: error: 'struct drm_i915_private'
declared inside parameter list will
RE: [RFC PATCH v2 2/3] RDMA/core: Expand the driver method 'reg_user_mr' to support dma-buf
Cc'd drm people.
> -Original Message-
> From: Xiong, Jianxin
> Sent: Monday, June 29, 2020 10:32 AM
> To: linux-r...@vger.kernel.org
> Cc: Xiong, Jianxin ; Doug Ledford
> ; Jason Gunthorpe ; Sumit Semwal
> ; Leon Romanovsky ; Vetter, Daniel
>
> Subject: [RFC PATCH v2 2/3] RDMA/core: Expand the driver method 'reg_user_mr'
> to support dma-buf
>
> Add a parameter 'fd' for the file descriptor associated with the dma-buf
> object to be imported. A negative value indicates that dma-buf is not
> used.
>
> Signed-off-by: Jianxin Xiong
> Reviewed-by: Sean Hefty
> Acked-by: Michael J. Ruhl
> ---
> drivers/infiniband/core/uverbs_cmd.c| 2 +-
> drivers/infiniband/core/verbs.c | 2 +-
> drivers/infiniband/hw/bnxt_re/ib_verbs.c| 7 +++-
> drivers/infiniband/hw/bnxt_re/ib_verbs.h| 2 +-
> drivers/infiniband/hw/cxgb4/iw_cxgb4.h | 3 +-
> drivers/infiniband/hw/cxgb4/mem.c | 8 -
> drivers/infiniband/hw/efa/efa.h | 2 +-
> drivers/infiniband/hw/efa/efa_verbs.c | 7 +++-
> drivers/infiniband/hw/hns/hns_roce_device.h | 2 +-
> drivers/infiniband/hw/hns/hns_roce_mr.c | 7 +++-
> drivers/infiniband/hw/i40iw/i40iw_verbs.c | 6
> drivers/infiniband/hw/mlx4/mlx4_ib.h| 2 +-
> drivers/infiniband/hw/mlx4/mr.c | 7 +++-
> drivers/infiniband/hw/mlx5/mlx5_ib.h| 2 +-
> drivers/infiniband/hw/mlx5/mr.c | 45
> ++---
> drivers/infiniband/hw/mthca/mthca_provider.c| 8 -
> drivers/infiniband/hw/ocrdma/ocrdma_verbs.c | 9 -
> drivers/infiniband/hw/ocrdma/ocrdma_verbs.h | 3 +-
> drivers/infiniband/hw/qedr/verbs.c | 8 -
> drivers/infiniband/hw/qedr/verbs.h | 3 +-
> drivers/infiniband/hw/usnic/usnic_ib_verbs.c| 8 -
> drivers/infiniband/hw/usnic/usnic_ib_verbs.h| 2 +-
> drivers/infiniband/hw/vmw_pvrdma/pvrdma_mr.c| 6 +++-
> drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h | 2 +-
> drivers/infiniband/sw/rdmavt/mr.c | 6 +++-
> drivers/infiniband/sw/rdmavt/mr.h | 2 +-
> drivers/infiniband/sw/rxe/rxe_verbs.c | 6
> drivers/infiniband/sw/siw/siw_verbs.c | 8 -
> drivers/infiniband/sw/siw/siw_verbs.h | 3 +-
> include/rdma/ib_verbs.h | 4 +--
> 30 files changed, 150 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/infiniband/core/uverbs_cmd.c
> b/drivers/infiniband/core/uverbs_cmd.c
> index 060b4eb..0199da2 100644
> --- a/drivers/infiniband/core/uverbs_cmd.c
> +++ b/drivers/infiniband/core/uverbs_cmd.c
> @@ -757,7 +757,7 @@ static int ib_uverbs_reg_mr(struct uverbs_attr_bundle
> *attrs)
> }
>
> mr = pd->device->ops.reg_user_mr(pd, cmd.start, cmd.length, cmd.hca_va,
> - cmd.access_flags,
> + -1, cmd.access_flags,
>>driver_udata);
> if (IS_ERR(mr)) {
> ret = PTR_ERR(mr);
> diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c
> index 56a7133..aa067b2 100644
> --- a/drivers/infiniband/core/verbs.c
> +++ b/drivers/infiniband/core/verbs.c
> @@ -2003,7 +2003,7 @@ struct ib_mr *ib_reg_user_mr(struct ib_pd *pd, u64
> start, u64 length,
> }
>
> mr = pd->device->ops.reg_user_mr(pd, start, length, virt_addr,
> - access_flags, NULL);
> + -1, access_flags, NULL);
>
> if (IS_ERR(mr))
> return mr;
> diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
> b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
> index 95f6d49..af40457 100644
> --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
> +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
> @@ -3695,7 +3695,7 @@ static int fill_umem_pbl_tbl(struct ib_umem *umem, u64
> *pbl_tbl_orig,
>
> /* uverbs */
> struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
> - u64 virt_addr, int mr_access_flags,
> + u64 virt_addr, int fd, int mr_access_flags,
> struct ib_udata *udata)
> {
> struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
> @@ -3728,6 +3728,11 @@ struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd,
> u64 start, u64 length,
> /* The fixed portion of the rkey is the same as the lkey */
> mr->ib_mr.rkey = mr->qplib_mr.rkey;
>
> + if (fd >= 0) {
> + rc = -EOPNOTSUPP;
> + goto free_mrw;
> + }
> +
> umem = ib_umem_get(>ibdev, start, length, mr_access_flags);
> if (IS_ERR(umem)) {
> ibdev_err(>ibdev, "Failed to get umem");
> diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.h
> b/drivers/infiniband/hw/bnxt_re/ib_verbs.h
>
RE: [RFC PATCH v2 3/3] RDMA/uverbs: Add uverbs command for dma-buf based MR registration
Cc'd drm people.
> -Original Message-
> From: Xiong, Jianxin
> Sent: Monday, June 29, 2020 10:32 AM
> To: linux-r...@vger.kernel.org
> Cc: Xiong, Jianxin ; Doug Ledford
> ; Jason Gunthorpe ; Sumit Semwal
> ; Leon Romanovsky ; Vetter, Daniel
>
> Subject: [RFC PATCH v2 3/3] RDMA/uverbs: Add uverbs command for dma-buf based
> MR registration
>
> Add uverbs command for registering user memory region associated with a
> dma-buf file descriptor.
>
> Signed-off-by: Jianxin Xiong
> Reviewed-by: Sean Hefty
> Acked-by: Michael J. Ruhl
> ---
> drivers/infiniband/core/uverbs_std_types_mr.c | 112
> ++
> include/uapi/rdma/ib_user_ioctl_cmds.h| 14
> 2 files changed, 126 insertions(+)
>
> diff --git a/drivers/infiniband/core/uverbs_std_types_mr.c
> b/drivers/infiniband/core/uverbs_std_types_mr.c
> index c1286a5..2c9ff7c 100644
> --- a/drivers/infiniband/core/uverbs_std_types_mr.c
> +++ b/drivers/infiniband/core/uverbs_std_types_mr.c
> @@ -1,5 +1,6 @@
> /*
> * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved.
> + * Copyright (c) 2020, Intel Corporation. All rights reserved.
> *
> * This software is available to you under a choice of one of two
> * licenses. You may choose to be licensed under the terms of the GNU @@
> -154,6 +155,85 @@ static int
> UVERBS_HANDLER(UVERBS_METHOD_DM_MR_REG)(
> return ret;
> }
>
> +static int UVERBS_HANDLER(UVERBS_METHOD_REG_DMABUF_MR)(
> + struct uverbs_attr_bundle *attrs)
> +{
> + struct ib_uobject *uobj =
> + uverbs_attr_get_uobject(attrs,
> UVERBS_ATTR_REG_DMABUF_MR_HANDLE);
> + struct ib_pd *pd =
> + uverbs_attr_get_obj(attrs, UVERBS_ATTR_REG_DMABUF_MR_PD_HANDLE);
> + struct ib_device *ib_dev = pd->device;
> +
> + u64 addr, length, hca_va;
> + u32 fd;
> + u32 access_flags;
> + struct ib_mr *mr;
> + int ret;
> +
> + if (!ib_dev->ops.reg_user_mr)
> + return -EOPNOTSUPP;
> +
> + ret = uverbs_copy_from(, attrs, UVERBS_ATTR_REG_DMABUF_MR_ADDR);
> + if (ret)
> + return ret;
> +
> + ret = uverbs_copy_from(, attrs,
> +UVERBS_ATTR_REG_DMABUF_MR_LENGTH);
> + if (ret)
> + return ret;
> +
> + ret = uverbs_copy_from(_va, attrs,
> +UVERBS_ATTR_REG_DMABUF_MR_HCA_VA);
> + if (ret)
> + return ret;
> +
> + ret = uverbs_copy_from(, attrs,
> +UVERBS_ATTR_REG_DMABUF_MR_FD);
> + if (ret)
> + return ret;
> +
> + ret = uverbs_get_flags32(_flags, attrs,
> + UVERBS_ATTR_REG_DMABUF_MR_ACCESS_FLAGS,
> + IB_ACCESS_SUPPORTED);
> + if (ret)
> + return ret;
> +
> + ret = ib_check_mr_access(access_flags);
> + if (ret)
> + return ret;
> +
> + mr = pd->device->ops.reg_user_mr(pd, addr, length, hca_va,
> +(int)(s32)fd, access_flags,
> +>driver_udata);
> + if (IS_ERR(mr))
> + return PTR_ERR(mr);
> +
> + mr->device = pd->device;
> + mr->pd = pd;
> + mr->type= IB_MR_TYPE_USER;
> + mr->uobject = uobj;
> + atomic_inc(>usecnt);
> +
> + uobj->object = mr;
> +
> + ret = uverbs_copy_to(attrs, UVERBS_ATTR_REG_DMABUF_MR_RESP_LKEY,
> + >lkey, sizeof(mr->lkey));
> + if (ret)
> + goto err_dereg;
> +
> + ret = uverbs_copy_to(attrs, UVERBS_ATTR_REG_DMABUF_MR_RESP_RKEY,
> + >rkey, sizeof(mr->rkey));
> + if (ret)
> + goto err_dereg;
> +
> + return 0;
> +
> +err_dereg:
> + ib_dereg_mr_user(mr, uverbs_get_cleared_udata(attrs));
> +
> + return ret;
> +}
> +
> DECLARE_UVERBS_NAMED_METHOD(
> UVERBS_METHOD_ADVISE_MR,
> UVERBS_ATTR_IDR(UVERBS_ATTR_ADVISE_MR_PD_HANDLE,
> @@ -200,6 +280,37 @@ static int UVERBS_HANDLER(UVERBS_METHOD_DM_MR_REG)(
> UVERBS_ATTR_TYPE(u32),
> UA_MANDATORY));
>
> +DECLARE_UVERBS_NAMED_METHOD(
> + UVERBS_METHOD_REG_DMABUF_MR,
> + UVERBS_ATTR_IDR(UVERBS_ATTR_REG_DMABUF_MR_HANDLE,
> + UVERBS_OBJECT_MR,
> + UVERBS_ACCESS_NEW,
> + UA_MANDATORY),
> + UVERBS_ATTR_IDR(UVERBS_ATTR_REG_DMABUF_MR_PD_HANDLE,
> + UVERBS_OBJECT_PD,
> + UVERBS_ACCESS_READ,
> + UA_MANDATORY),
> + UVERBS_ATTR_PTR_IN(UVERBS_ATTR_REG_DMABUF_MR_ADDR,
> +UVERBS_ATTR_TYPE(u64),
> +UA_MANDATORY),
> + UVERBS_ATTR_PTR_IN(UVERBS_ATTR_REG_DMABUF_MR_LENGTH,
> +UVERBS_ATTR_TYPE(u64),
> +UA_MANDATORY),
> + UVERBS_ATTR_PTR_IN(UVERBS_ATTR_REG_DMABUF_MR_HCA_VA,
> +
RE: [RFC PATCH v2 1/3] RDMA/umem: Support importing dma-buf as user memory region
Cc'd drm people.
> -Original Message-
> From: Xiong, Jianxin
> Sent: Monday, June 29, 2020 10:32 AM
> To: linux-r...@vger.kernel.org
> Cc: Xiong, Jianxin ; Doug Ledford
> ; Jason Gunthorpe ; Sumit Semwal
> ; Leon Romanovsky ; Vetter, Daniel
>
> Subject: [RFC PATCH v2 1/3] RDMA/umem: Support importing dma-buf as user
> memory region
>
> Dma-buf is a standard cross-driver buffer sharing mechanism that can be
> used to support peer-to-peer access from RDMA devices.
>
> Device memory exported via dma-buf can be associated with a file
> descriptor. This is passed to the user space as a property associated
> with the buffer allocation. When the buffer is registered as a memory
> region, the file descriptor is passed to the RDMA driver along with
> other parameters.
>
> Implement the common code for importing dma-buf object, and pinning and
> mapping dma-buf pages.
>
> Signed-off-by: Jianxin Xiong
> Reviewed-by: Sean Hefty
> Acked-by: Michael J. Ruhl
> ---
> drivers/infiniband/core/Makefile | 2 +-
> drivers/infiniband/core/umem.c| 4 ++
> drivers/infiniband/core/umem_dmabuf.c | 105
> ++
> drivers/infiniband/core/umem_dmabuf.h | 11
> include/rdma/ib_umem.h| 14 -
> 5 files changed, 134 insertions(+), 2 deletions(-)
> create mode 100644 drivers/infiniband/core/umem_dmabuf.c
> create mode 100644 drivers/infiniband/core/umem_dmabuf.h
>
> diff --git a/drivers/infiniband/core/Makefile
> b/drivers/infiniband/core/Makefile
> index d1b14887..0d4efa0 100644
> --- a/drivers/infiniband/core/Makefile
> +++ b/drivers/infiniband/core/Makefile
> @@ -37,5 +37,5 @@ ib_uverbs-y := uverbs_main.o
> uverbs_cmd.o uverbs_marshall.o \
> uverbs_std_types_mr.o
> uverbs_std_types_counters.o \
> uverbs_uapi.o uverbs_std_types_device.o \
> uverbs_std_types_async_fd.o
> -ib_uverbs-$(CONFIG_INFINIBAND_USER_MEM) += umem.o
> +ib_uverbs-$(CONFIG_INFINIBAND_USER_MEM) += umem.o umem_dmabuf.o
> ib_uverbs-$(CONFIG_INFINIBAND_ON_DEMAND_PAGING) += umem_odp.o
> diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c
> index 82455a1..bf1a6c1 100644
> --- a/drivers/infiniband/core/umem.c
> +++ b/drivers/infiniband/core/umem.c
> @@ -2,6 +2,7 @@
> * Copyright (c) 2005 Topspin Communications. All rights reserved.
> * Copyright (c) 2005 Cisco Systems. All rights reserved.
> * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
> + * Copyright (c) 2020 Intel Corporation. All rights reserved.
> *
> * This software is available to you under a choice of one of two
> * licenses. You may choose to be licensed under the terms of the GNU
> @@ -42,6 +43,7 @@
> #include
>
> #include "uverbs.h"
> +#include "umem_dmabuf.h"
>
> static void __ib_umem_release(struct ib_device *dev, struct ib_umem *umem,
> int dirty)
> {
> @@ -317,6 +319,8 @@ void ib_umem_release(struct ib_umem *umem)
> {
> if (!umem)
> return;
> + if (umem->is_dmabuf)
> + return ib_umem_dmabuf_release(umem);
> if (umem->is_odp)
> return ib_umem_odp_release(to_ib_umem_odp(umem));
>
> diff --git a/drivers/infiniband/core/umem_dmabuf.c
> b/drivers/infiniband/core/umem_dmabuf.c
> new file mode 100644
> index 000..406ca64
> --- /dev/null
> +++ b/drivers/infiniband/core/umem_dmabuf.c
> @@ -0,0 +1,105 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2020 Intel Corporation. All rights reserved.
> + */
> +
> +#include
> +#include
> +
> +#include "uverbs.h"
> +
> +struct ib_umem_dmabuf {
> + struct ib_umem umem;
> + struct dma_buf *dmabuf;
> + struct dma_buf_attachment *attach;
> + struct sg_table *sgt;
> +};
> +
> +static inline struct ib_umem_dmabuf *to_ib_umem_dmabuf(struct ib_umem *umem)
> +{
> + return container_of(umem, struct ib_umem_dmabuf, umem);
> +}
> +
> +struct ib_umem *ib_umem_dmabuf_get(struct ib_device *device,
> +unsigned long addr, size_t size,
> +int dmabuf_fd, int access)
> +{
> + struct ib_umem_dmabuf *umem_dmabuf;
> + struct sg_table *sgt;
> + enum dma_data_direction dir;
> + long ret;
> + unsigned long end;
> +
> + if (check_add_overflow(addr, size, ))
> + return ERR_PTR(-EINVAL);
> +
> + if (unlikely(PAGE_ALIGN(end) < PAGE_SIZE))
> + return ERR_PTR(-EINVAL);
> +
> + if (access & IB_ACCESS_ON_DEMAND)
> + return ERR_PTR(-EOPNOTSUPP);
> +
> + umem_dmabuf = kzalloc(sizeof(*umem_dmabuf), GFP_KERNEL);
> + if (!umem_dmabuf)
> + return ERR_PTR(-ENOMEM);
> +
> + umem_dmabuf->umem.ibdev = device;
> + umem_dmabuf->umem.length = size;
> + umem_dmabuf->umem.address = addr;
> + umem_dmabuf->umem.writable = ib_access_writable(access);
> +
RE: [RFC PATCH v2 0/3] RDMA: add dma-buf support
Added to cc-list: Christian Koenig dri-devel@lists.freedesktop.org > -Original Message- > From: Xiong, Jianxin > Sent: Monday, June 29, 2020 10:32 AM > To: linux-r...@vger.kernel.org > Cc: Xiong, Jianxin ; Doug Ledford > ; Jason Gunthorpe ; Sumit Semwal > ; Leon Romanovsky ; Vetter, Daniel > > Subject: [RFC PATCH v2 0/3] RDMA: add dma-buf support > > When enabled, an RDMA capable NIC can perform peer-to-peer transactions > over PCIe to access the local memory located on another device. This can > often lead to better performance than using a system memory buffer for > RDMA and copying data between the buffer and device memory. > > Current kernel RDMA stack uses get_user_pages() to pin the physical > pages backing the user buffer and uses dma_map_sg_attrs() to get the > dma addresses for memory access. This usually doesn't work for peer > device memory due to the lack of associated page structures. > > Several mechanisms exist today to facilitate device memory access. > > ZONE_DEVICE is a new zone for device memory in the memory management > subsystem. It allows pages from device memory being described with > specialized page structures. As the result, calls like get_user_pages() > can succeed, but what can be done with these page structures may be > different from system memory. It is further specialized into multiple > memory types, such as one type for PCI p2pmem/p2pdma and one type for > HMM. > > PCI p2pmem/p2pdma uses ZONE_DEVICE to represent device memory residing > in a PCI BAR and provides a set of calls to publish, discover, allocate, > and map such memory for peer-to-peer transactions. One feature of the > API is that the buffer is allocated by the side that does the DMA > transfer. This works well with the storage usage case, but is awkward > with GPU-NIC communication, where typically the buffer is allocated by > the GPU driver rather than the NIC driver. > > Heterogeneous Memory Management (HMM) utilizes mmu_interval_notifier > and ZONE_DEVICE to support shared virtual address space and page > migration between system memory and device memory. HMM doesn't support > pinning device memory because pages located on device must be able to > migrate to system memory when accessed by CPU. Peer-to-peer access > is possible if the peer can handle page fault. For RDMA, that means > the NIC must support on-demand paging. > > Dma-buf is a standard mechanism for sharing buffers among different > device drivers. The buffer to be shared is exported by the owning > driver and imported by the driver that wants to use it. The exporter > provides a set of ops that the importer can call to pin and map the > buffer. In addition, a file descriptor can be associated with a dma- > buf object as the handle that can be passed to user space. > > This patch series adds dma-buf importer role to the RDMA driver in > attempt to support RDMA using device memory such as GPU VRAM. Dma-buf is > chosen for a few reasons: first, the API is relatively simple and allows > a lot of flexibility in implementing the buffer manipulation ops. > Second, it doesn't require page structure. Third, dma-buf is already > supported in many GPU drivers. However, we are aware that existing GPU > drivers don't allow pinning device memory via the dma-buf interface. > Pinning and mapping a dma-buf would cause the backing storage to migrate > to system RAM. This is due to the lack of knowledge about whether the > importer can perform peer-to-peer access and the lack of resource limit > control measure for GPU. For the first part, the latest dma-buf driver > has a peer-to-peer flag for the importer, but the flag is currently tied > to dynamic mapping support, which requires on-demand paging support from > the NIC to work. There are a few possible ways to address these issues, > such as decoupling peer-to-peer flag from dynamic mapping, allowing more > leeway for individual drivers to make the pinning decision and adding > GPU resource limit control via cgroup. We would like to get comments on > this patch series with the assumption that device memory pinning via > dma-buf is supported by some GPU drivers, and at the same time welcome > open discussions on how to address the aforementioned issues as well as > GPU-NIC peer-to-peer access solutions in general. > > This is the second version of the patch series. Here are the changes > from the previous version: > * The Kconfig option is removed. There is no dependence issue since > dma-buf driver is always enabled. > * The declaration of new data structure and functions is reorganized to > minimize the visibility of the changes. > * The new uverbs command now goes through ioctl() instead of write(). > * The rereg functionality is removed. > * Instead of adding new device method for dma-buf specific registration, > existing method is extended to accept an extra parameter. > * The correct function is now used for address range checking. > > This series is organized as follows. The
[PATCH v8 0/6] Add support for DisplayPort driver on SnapDragon
These patches add Display-Port driver on SnapDragon/msm hardware. This series also contains device-tree bindings for msm DP driver. It also contains Makefile and Kconfig changes to compile msm DP driver. The block diagram of DP driver is shown below: +-+ |DRM FRAMEWORK| +--+--+ | +v+ | DP DRM | +++ | +v+ ++| DP+--++--+ ++---+| DISPLAY |+---+ | | |++-+-+-+| | | || | | | | | || | | | | | || | | | | | vv v v v v v +--+ +--+ +---+ ++ ++ +---+ +-+ | DP | | DP | |DP | | DP | | DP | |DP | | DP | |PARSER| | HPD | |AUX| |LINK| |CTRL| |PHY| |POWER| +--+---+ +---+--+ +---+ ++ +--+-+ +-+-+ +-+ | | | +--v---+ +v-v+ |DEVICE| | DP | | TREE | |CATALOG| +--+ +---+---+ | +---v+ |CTRL/PHY| | HW | ++ Changes in v7: - Modify cover letter description and fix title. - Introduce dp-controller.yaml for common bindings across SOC - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml for SC7180 bindings - Rename compatible string to qcom,sc7180-dp - Add assigned-clocks and assigned-clock-parents properties in bindings - Remove redundant code from driver - Extend series to include HPD detection logic Changes in v8: - Add MDSS AHB clock in bindings - Replace mode->vrefresh use with drm_mode_vrefresh API - Remove redundant aux config code from parser and aux module - Assign default max lanes if data-lanes property is not available - Fix use-after-free during DP driver remove - Unregister hardware clocks during driver cleanup This series depends-on: https://patchwork.freedesktop.org/patch/366159/ https://patchwork.freedesktop.org/patch/369859/ Chandan Uddaraju (4): dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon drm: add constant N value in helper file drm/msm/dp: add displayPort driver support drm/msm/dp: add support for DP PLL driver Jeykumar Sankaran (1): drm/msm/dpu: add display port support in DPU Tanmay Shah (1): drm/msm/dp: Add Display Port HPD feature .../display/msm/dp-controller-sc7180.yaml | 144 ++ .../bindings/display/msm/dp-controller.yaml | 61 + .../bindings/display/msm/dpu-sc7180.yaml | 11 + drivers/gpu/drm/i915/display/intel_display.c |2 +- drivers/gpu/drm/msm/Kconfig | 16 + drivers/gpu/drm/msm/Makefile | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c |8 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 83 +- drivers/gpu/drm/msm/dp/dp_aux.c | 510 + drivers/gpu/drm/msm/dp/dp_aux.h | 29 + drivers/gpu/drm/msm/dp/dp_catalog.c | 1060 ++ drivers/gpu/drm/msm/dp/dp_catalog.h | 104 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 1707 + drivers/gpu/drm/msm/dp/dp_ctrl.h | 35 + drivers/gpu/drm/msm/dp/dp_display.c | 1017 ++ drivers/gpu/drm/msm/dp/dp_display.h | 31 + drivers/gpu/drm/msm/dp/dp_drm.c | 168 ++ drivers/gpu/drm/msm/dp/dp_drm.h | 18 + drivers/gpu/drm/msm/dp/dp_hpd.c | 69 + drivers/gpu/drm/msm/dp/dp_hpd.h | 79 + drivers/gpu/drm/msm/dp/dp_link.c | 1216 drivers/gpu/drm/msm/dp/dp_link.h | 132 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 490 + drivers/gpu/drm/msm/dp/dp_panel.h | 95 + drivers/gpu/drm/msm/dp/dp_parser.c| 267 +++ drivers/gpu/drm/msm/dp/dp_parser.h| 138 ++ drivers/gpu/drm/msm/dp/dp_pll.c | 99 + drivers/gpu/drm/msm/dp/dp_pll.h | 61 + drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 917 + drivers/gpu/drm/msm/dp/dp_pll_private.h | 111 ++ drivers/gpu/drm/msm/dp/dp_power.c | 392 drivers/gpu/drm/msm/dp/dp_power.h | 103 + drivers/gpu/drm/msm/dp/dp_reg.h | 517 + drivers/gpu/drm/msm/msm_drv.c |2 + drivers/gpu/drm/msm/msm_drv.h | 59 +- include/drm/drm_dp_helper.h |1 + 37 files changed, 9776 insertions(+), 19 deletions(-) create mode 100644
[PATCH v8 5/6] drm/msm/dpu: add display port support in DPU
From: Jeykumar Sankaran
Add display port support in DPU by creating hooks
for DP encoder enumeration and encoder mode
initialization.
changes in v2:
- rebase on [2] (Sean Paul)
- remove unwanted error checks and
switch cases (Jordan Crouse)
[1] https://lwn.net/Articles/768265/
[2] https://lkml.org/lkml/2018/11/17/87
changes in V3:
-- Moved this change as part of the DP driver changes.
-- Addressed compilation issues on the latest code base.
Changes in v6:
-- Fix checkpatch.pl warning
Changes in v7: Remove depends-on tag from commit message.
Changes in v8: None
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Chandan Uddaraju
Signed-off-by: Vara Reddy
Signed-off-by: Tanmay Shah
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 65 +
2 files changed, 58 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 753cc2fcf916..b439e482fc80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1994,7 +1994,7 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
{
int ret = 0;
int i = 0;
- enum dpu_intf_type intf_type;
+ enum dpu_intf_type intf_type = INTF_NONE;
struct dpu_enc_phys_init_params phys_params;
if (!dpu_enc) {
@@ -2016,9 +2016,9 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
case DRM_MODE_ENCODER_DSI:
intf_type = INTF_DSI;
break;
- default:
- DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
- return -EINVAL;
+ case DRM_MODE_ENCODER_TMDS:
+ intf_type = INTF_DP;
+ break;
}
WARN_ON(disp_info->num_of_h_tiles < 1);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index b8615d4fe8a3..f6c219f875db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -492,6 +492,33 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
return rc;
}
+static int _dpu_kms_initialize_displayport(struct drm_device *dev,
+ struct msm_drm_private *priv,
+ struct dpu_kms *dpu_kms)
+{
+ struct drm_encoder *encoder = NULL;
+ int rc = 0;
+
+ if (!priv->dp)
+ return rc;
+
+ encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
+ if (IS_ERR(encoder)) {
+ DPU_ERROR("encoder init failed for dsi display\n");
+ return PTR_ERR(encoder);
+ }
+
+ rc = msm_dp_modeset_init(priv->dp, dev, encoder);
+ if (rc) {
+ DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
+ drm_encoder_cleanup(encoder);
+ return rc;
+ }
+
+ priv->encoders[priv->num_encoders++] = encoder;
+ return rc;
+}
+
/**
* _dpu_kms_setup_displays - create encoders, bridges and connectors
* for underlying displays
@@ -504,12 +531,21 @@ static int _dpu_kms_setup_displays(struct drm_device *dev,
struct msm_drm_private *priv,
struct dpu_kms *dpu_kms)
{
- /**
-* Extend this function to initialize other
-* types of displays
-*/
+ int rc = 0;
+
+ rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
+ if (rc) {
+ DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
+ return rc;
+ }
- return _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
+ rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
+ if (rc) {
+ DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
+ return rc;
+ }
+
+ return rc;
}
static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms)
@@ -694,13 +730,20 @@ static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE :
MSM_DISPLAY_CAP_VID_MODE;
- /* TODO: No support for DSI swap */
- for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
- if (priv->dsi[i]) {
- info.h_tile_instance[info.num_of_h_tiles] = i;
- info.num_of_h_tiles++;
+ switch (info.intf_type) {
+ case DRM_MODE_ENCODER_DSI:
+ /* TODO: No support for DSI swap */
+ for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+ if (priv->dsi[i]) {
+ info.h_tile_instance[info.num_of_h_tiles] = i;
+ info.num_of_h_tiles++;
+ }
}
- }
+ break;
+
[PATCH v8 4/6] drm/msm/dp: add support for DP PLL driver
From: Chandan Uddaraju
Add the needed DP PLL specific files to support
display port interface on msm targets.
The DP driver calls the DP PLL driver registration.
The DP driver sets the link and pixel clock sources.
Changes in v2:
-- Update copyright markings on all relevant files.
-- Use DRM_DEBUG_DP for debug msgs.
Changes in v4:
-- Update the DP link clock provider names
Changes in V5:
-- Addressed comments from Stephen Boyd, Rob clark.
Changes in V6:
-- Remove PLL as separate driver and include PLL as DP module
-- Remove redundant clock parsing from PLL module and make DP as
clock provider
-- Map USB3 DPCOM and PHY IO using hardcoded register address and
move mapping form parser to PLL module
-- Access DP PHY modules from same base address using offsets instead of
deriving base address of individual module from device tree.
-- Remove dp_pll_10nm_util.c and include its functionality in
dp_pll_10nm.c
-- Introduce new data structures private to PLL module
Changes in v7:
-- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig
-- Remove set_parent from determin_rate API
-- Remove phy_pll_vco_div_clk from parent list
-- Remove flag CLK_DIVIDER_ONE_BASED
-- Remove redundant cell-index property parsing
Changes in v8:
-- Unregister hardware clocks during driver cleanup
Signed-off-by: Chandan Uddaraju
Signed-off-by: Vara Reddy
Signed-off-by: Tanmay Shah
---
drivers/gpu/drm/msm/Kconfig | 8 +
drivers/gpu/drm/msm/Makefile| 4 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 31 +-
drivers/gpu/drm/msm/dp/dp_display.c | 18 +-
drivers/gpu/drm/msm/dp/dp_display.h | 3 +
drivers/gpu/drm/msm/dp/dp_parser.c | 30 +-
drivers/gpu/drm/msm/dp/dp_parser.h | 7 +-
drivers/gpu/drm/msm/dp/dp_pll.c | 99 +++
drivers/gpu/drm/msm/dp/dp_pll.h | 61 ++
drivers/gpu/drm/msm/dp/dp_pll_10nm.c| 917
drivers/gpu/drm/msm/dp/dp_pll_private.h | 111 +++
drivers/gpu/drm/msm/dp/dp_power.c | 10 +
drivers/gpu/drm/msm/dp/dp_power.h | 40 +-
drivers/gpu/drm/msm/dp/dp_reg.h | 16 +
14 files changed, 1310 insertions(+), 45 deletions(-)
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index ea3c4d094d09..6f575e8da455 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -60,11 +60,19 @@ config DRM_MSM_HDMI_HDCP
config DRM_MSM_DP
bool "Enable DP support in MSM DRM driver"
depends on DRM_MSM
+ default y
help
Compile in support for DP driver in msm drm driver. DP external
display support is enabled through this config option. It can
be primary or secondary display on device.
+config DRM_MSM_DP_10NM_PLL
+ bool "Enable DP 10nm PLL driver in MSM DRM (used by sc7180)"
+ depends on DRM_MSM_DP
+ default y
+ help
+ Choose this option if DP PLL on SC7180 is used on the platform.
+
config DRM_MSM_DSI
bool "Enable DSI support in MSM DRM driver"
depends on DRM_MSM
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index af868e791210..6d31188cc776 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -109,7 +109,9 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_link.o \
dp/dp_panel.o \
dp/dp_parser.o \
- dp/dp_power.o
+ dp/dp_power.o \
+ dp/dp_pll.o \
+ dp/dp_pll_10nm.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index c54312341e3c..b5898ad03e4f 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -5,6 +5,7 @@
#define pr_fmt(fmt)"[drm-dp] %s: " fmt, __func__
+#include
#include
#include
#include
@@ -160,51 +161,58 @@ static inline void dp_write_ahb(struct dp_catalog_private
*catalog,
static inline void dp_write_phy(struct dp_catalog_private *catalog,
u32 offset, u32 data)
{
+ offset += DP_PHY_REG_OFFSET;
/*
* To make sure phy reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, catalog->io->phy_io.base + offset);
+ writel(data, catalog->io->phy_reg.base + offset);
}
static inline u32 dp_read_phy(struct dp_catalog_private *catalog,
u32 offset)
{
+ offset += DP_PHY_REG_OFFSET;
/*
* To make sure phy reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
-
[PATCH v8 6/6] drm/msm/dp: Add Display Port HPD feature
Configure HPD registers in DP controller and
enable HPD interrupt.
Add interrupt to handle HPD connect and disconnect events.
Changes in v8: None
Signed-off-by: Tanmay Shah
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18
drivers/gpu/drm/msm/dp/dp_catalog.c | 67 +--
drivers/gpu/drm/msm/dp/dp_catalog.h | 5 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c| 1 -
drivers/gpu/drm/msm/dp/dp_display.c | 108 ++--
drivers/gpu/drm/msm/dp/dp_reg.h | 12 +++
drivers/gpu/drm/msm/msm_drv.h | 6 ++
7 files changed, 182 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index f6c219f875db..8169238724b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -765,6 +765,23 @@ static void dpu_irq_preinstall(struct msm_kms *kms)
dpu_core_irq_preinstall(dpu_kms);
}
+static int dpu_irq_postinstall(struct msm_kms *kms)
+{
+ struct msm_drm_private *priv;
+ struct dpu_kms *dpu_kms = to_dpu_kms(kms);
+
+ if (!dpu_kms || !dpu_kms->dev)
+ return -EINVAL;
+
+ priv = dpu_kms->dev->dev_private;
+ if (!priv)
+ return -EINVAL;
+
+ msm_dp_irq_postinstall(priv->dp);
+
+ return 0;
+}
+
static void dpu_irq_uninstall(struct msm_kms *kms)
{
struct dpu_kms *dpu_kms = to_dpu_kms(kms);
@@ -775,6 +792,7 @@ static void dpu_irq_uninstall(struct msm_kms *kms)
static const struct msm_kms_funcs kms_funcs = {
.hw_init = dpu_kms_hw_init,
.irq_preinstall = dpu_irq_preinstall,
+ .irq_postinstall = dpu_irq_postinstall,
.irq_uninstall = dpu_irq_uninstall,
.irq = dpu_irq,
.enable_commit = dpu_kms_enable_commit,
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index b5898ad03e4f..ab69ae3e2dbd 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -17,7 +17,6 @@
#define POLLING_SLEEP_US 1000
#define POLLING_TIMEOUT_US 1
-#define REFTIMER_DEFAULT_VALUE 0x2
#define SCRAMBLER_RESET_COUNT_VALUE0xFC
#define DP_INTERRUPT_STATUS_ACK_SHIFT 1
@@ -761,35 +760,51 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog
*dp_catalog,
}
}
-void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool en)
+void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
+ u32 intr_mask, bool en)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- if (en) {
- u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
-
- dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK,
- DP_DP_HPD_PLUG_INT_ACK |
- DP_DP_IRQ_HPD_INT_ACK |
- DP_DP_HPD_REPLUG_INT_ACK |
- DP_DP_HPD_UNPLUG_INT_ACK);
- dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK,
- DP_DP_HPD_PLUG_INT_MASK |
- DP_DP_IRQ_HPD_INT_MASK |
- DP_DP_HPD_REPLUG_INT_MASK |
- DP_DP_HPD_UNPLUG_INT_MASK);
-
- /* Configure REFTIMER */
- reftimer |= REFTIMER_DEFAULT_VALUE;
- dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer);
- /* Enable HPD */
- dp_write_aux(catalog, REG_DP_DP_HPD_CTRL,
- DP_DP_HPD_CTRL_HPD_EN);
- } else {
- /* Disable HPD */
- dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0x0);
- }
+ u32 config = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK);
+
+ config = (en ? config | intr_mask : config & ~intr_mask);
+
+ dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK,
+ config & DP_DP_HPD_INT_MASK);
+}
+
+void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
+
+ /* enable HPD interrupts */
+ dp_catalog_hpd_config_intr(dp_catalog,
+ DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK
+ | DP_DP_HPD_UNPLUG_INT_MASK, true);
+
+ /* Configure REFTIMER and enable it */
+ reftimer |= DP_DP_HPD_REFTIMER_ENABLE;
+ dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer);
+
+ /* Enable HPD */
+ dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
+}
+
+u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
+{
+ struct
[PATCH v8 2/6] drm: add constant N value in helper file
From: Chandan Uddaraju The constant N value (0x8000) is used by i915 DP driver. Define this value in dp helper header file to use in multiple Display Port drivers. Change i915 driver accordingly. Change in v6: Change commit message Signed-off-by: Chandan Uddaraju Signed-off-by: Vara Reddy Signed-off-by: Tanmay Shah Reviewed-by: Stephen Boyd Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- include/drm/drm_dp_helper.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c1836095ea38..81c461aeb3ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8085,7 +8085,7 @@ static void compute_m_n(unsigned int m, unsigned int n, * which the devices expect also in synchronous clock mode. */ if (constant_n) - *ret_n = 0x8000; + *ret_n = DP_LINK_CONSTANT_N_VALUE; else *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1165ec105638..73dae5bd6048 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1134,6 +1134,7 @@ #define DP_MST_PHYSICAL_PORT_0 0 #define DP_MST_LOGICAL_PORT_0 8 +#define DP_LINK_CONSTANT_N_VALUE 0x8000 #define DP_LINK_STATUS_SIZE 6 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [RFC PATCH v2 0/3] RDMA: add dma-buf support
> -Original Message- > From: Jason Gunthorpe > Sent: Tuesday, June 30, 2020 10:35 AM > To: Xiong, Jianxin > Cc: linux-r...@vger.kernel.org; Doug Ledford ; Sumit > Semwal ; Leon Romanovsky > ; Vetter, Daniel ; Christian Koenig > > Subject: Re: [RFC PATCH v2 0/3] RDMA: add dma-buf support > > On Tue, Jun 30, 2020 at 05:21:33PM +, Xiong, Jianxin wrote: > > > > Heterogeneous Memory Management (HMM) utilizes > > > > mmu_interval_notifier and ZONE_DEVICE to support shared virtual > > > > address space and page migration between system memory and device > > > > memory. HMM doesn't support pinning device memory because pages > > > > located on device must be able to migrate to system memory when > > > > accessed by CPU. Peer-to-peer access is possible if the peer can > > > > handle page fault. For RDMA, that means the NIC must support on-demand > > > > paging. > > > > > > peer-peer access is currently not possible with hmm_range_fault(). > > > > Currently hmm_range_fault() always sets the cpu access flag and device > > private pages are migrated to the system RAM in the fault handler. > > However, it's possible to have a modified code flow to keep the device > > private page info for use with peer to peer access. > > Sort of, but only within the same device, RDMA or anything else generic can't > reach inside a DEVICE_PRIVATE and extract anything useful. But pfn is supposed to be all that is needed. > > > > So.. this patch doesn't really do anything new? We could just make a MR > > > against the DMA buf mmap and get to the same place? > > > > That's right, the patch alone is just half of the story. The > > functionality depends on availability of dma-buf exporter that can pin > > the device memory. > > Well, what do you want to happen here? The RDMA parts are reasonable, but I > don't want to add new functionality without a purpose - the > other parts need to be settled out first. At the RDMA side, we mainly want to check if the changes are acceptable. For example, the part about adding 'fd' to the device ops and the ioctl interface. All the previous comments are very helpful for us to refine the patch so that we can be ready when GPU side support becomes available. > > The need for the dynamic mapping support for even the current DMA Buf hacky > P2P users is really too bad. Can you get any GPU driver to > support non-dynamic mapping? We are working on direct direction. > > > > > migrate to system RAM. This is due to the lack of knowledge about > > > > whether the importer can perform peer-to-peer access and the lack > > > > of resource limit control measure for GPU. For the first part, the > > > > latest dma-buf driver has a peer-to-peer flag for the importer, > > > > but the flag is currently tied to dynamic mapping support, which > > > > requires on-demand paging support from the NIC to work. > > > > > > ODP for DMA buf? > > > > Right. > > Hum. This is not actually so hard to do. The whole dma buf proposal would > make a lot more sense if the 'dma buf MR' had to be the > dynamic kind and the driver had to provide the faulting. It would not be so > hard to change mlx5 to be able to work like this, perhaps. (the > locking might be a bit tricky though) The main issue is that not all NICs support ODP. > > > > > There are a few possible ways to address these issues, such as > > > > decoupling peer-to-peer flag from dynamic mapping, allowing more > > > > leeway for individual drivers to make the pinning decision and > > > > adding GPU resource limit control via cgroup. We would like to get > > > > comments on this patch series with the assumption that device > > > > memory pinning via dma-buf is supported by some GPU drivers, and > > > > at the same time welcome open discussions on how to address the > > > > aforementioned issues as well as GPU-NIC peer-to-peer access solutions > > > > in general. > > > > > > These seem like DMA buf problems, not RDMA problems, why are you > > > asking these questions with a RDMA patch set? The usual DMA buf people > > > are not even Cc'd here. > > > > The intention is to have people from both RDMA and DMA buffer side to > > comment. Sumit Semwal is the DMA buffer maintainer according to the > > MAINTAINERS file. I agree more people could be invited to the discussion. > > Just added Christian Koenig to the cc-list. > > Would be good to have added the drm lists too Thanks, cc'd dri-devel here, and will also do the same for the previous part of the thread. > > > If the umem_description you mentioned is for information used to > > create the umem (e.g. a structure for all the parameters), then this would > > work better. > > It would make some more sense, and avoid all these weird EOPNOTSUPPS. Good, thanks for the suggestion. > > Jason ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v8 1/6] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon
From: Chandan Uddaraju
Add bindings for Snapdragon DisplayPort controller driver.
Changes in V2:
Provide details about sel-gpio
Changes in V4:
Provide details about max dp lanes
Change the commit text
Changes in V5:
moved dp.txt to yaml file
Changes in v6:
- Squash all AUX LUT properties into one pattern Property
- Make aux-cfg[0-9]-settings properties optional
- Remove PLL/PHY bindings from DP controller dts
- Add DP clocks description
- Remove _clk suffix from clock names
- Rename pixel clock to stream_pixel
- Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
- Fix indentation
- Add Display Port as interface of DPU in DPU bindings
and add port mapping accordingly.
Chages in v7:
- Add dp-controller.yaml file common between multiple SOC
- Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
- change compatible string and add SOC name to it.
- Remove Root clock generator for pixel clock
- Add assigned-clocks and assigned-clock-parents bindings
- Remove redundant properties, descriptions and blank lines
- Add DP port in DPU bindings
- Update depends-on tag in commit message and rebase change accordingly
Changes in v8:
- Add MDSS AHB clock in bindings
This change depends-on:
- https://patchwork.freedesktop.org/patch/366159/
Signed-off-by: Chandan Uddaraju
Signed-off-by: Vara Reddy
Signed-off-by: Tanmay Shah
---
.../display/msm/dp-controller-sc7180.yaml | 144 ++
.../bindings/display/msm/dp-controller.yaml | 61
.../bindings/display/msm/dpu-sc7180.yaml | 11 ++
3 files changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml
b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml
new file mode 100644
index ..ce89ea73e778
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-controller-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MSM SC7180 Display Port Controller.
+
+maintainers:
+ - Chandan Uddaraju
+ - Vara Reddy
+ - Tanmay Shah
+
+description: |
+ Device tree bindings for DP host controller for MSM SC7180 target
+ that are compatible with VESA Display Port interface specification.
+
+allOf:
+ - $ref: dp-controller.yaml#
+
+properties:
+ compatible:
+items:
+ - enum:
+ - qcom,sc7180-dp
+
+ reg:
+maxItems: 1
+ reg-names:
+const: dp_controller
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 5
+
+ clock-names:
+items:
+ - const: core_iface
+ - const: core_aux
+ - const: ctrl_link
+ - const: ctrl_link_iface
+ - const: stream_pixel
+
+ "#clock-cells":
+const: 1
+
+ assigned-clocks:
+maxItems: 1
+ assigned-clock-parents:
+maxItems: 1
+
+ data-lanes:
+$ref: "/schemas/types.yaml#/definitions/uint32-array"
+minItems: 1
+maxItems: 4
+
+ vdda-1p2-supply:
+description: phandle to vdda 1.2V regulator node.
+
+ vdda-0p9-supply:
+description: phandle to vdda 0.9V regulator node.
+
+ ports:
+type: object
+properties:
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ port@0:
+type: object
+ port@1:
+type: object
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - vdda-1p2-supply
+ - vdda-0p9-supply
+ - data-lanes
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+msm_dp: displayport-controller@ae9{
+compatible = "qcom,sc7180-dp";
+reg = <0 0xae9 0 0x1400>;
+reg-names = "dp_controller";
+
+interrupt-parent = <>;
+interrupts = <12 0>;
+
+clocks = < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_DP_AUX_CLK>,
+ < DISP_CC_MDSS_DP_LINK_CLK>,
+ < DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ < DISP_CC_MDSS_DP_PIXEL_CLK>;
+clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+#clock-cells = <1>;
+
+assigned-clocks = < DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+assigned-clock-parents = <_phy 1>;
+
+vdda-1p2-supply = <_l3c_1p2>;
+vdda-0p9-supply = <_l4a_0p8>;
+
+data-lanes = <0 1>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dp_in: endpoint {
+remote-endpoint = <_intf0_out>;
+
Re: [PATCH 1/2] dt-bindings: serial: add generic DT binding for announcing RTS/CTS lines
On Sat, Jun 27, 2020 at 8:18 AM Greg Kroah-Hartman wrote: > > On Wed, May 20, 2020 at 03:39:31PM +0200, Erwan Le Ray wrote: > > Add support of generic DT binding for annoucing RTS/CTS lines. The initial > > binding 'st,hw-flow-control' is not needed anymore since generic binding > > is available, but is kept for backward compatibility. > > > > Signed-off-by: Erwan Le Ray > > > > diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml > > b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml > > index 75b8521eb7cb..06d5f251ec88 100644 > > --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml > > +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml > > @@ -35,9 +35,11 @@ properties: > > description: label associated with this uart > > > >st,hw-flow-ctrl: > > -description: enable hardware flow control > > +description: enable hardware flow control (deprecated) > > $ref: /schemas/types.yaml#/definitions/flag > > > > + uart-has-rtscts: true > > + > >dmas: > > minItems: 1 > > maxItems: 2 > > -- > > 2.17.1 > > > > Did this get ignored by the DT maintainers? :( When it doesn't go to the DT list, you are playing roulette whether I happen to see it. :( Anyways, Reviewed-by: Rob Herring ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] omapfb: dss: Fix max fclk divider for omap36xx
The drm/omap driver was fixed to correct an issue where using a
divider of 32 breaks the DSS despite the TRM stating 32 is a valid
number. Through experimentation, it appears that 31 works, and
it is consistent with the value used by the drm/omap driver.
This patch fixes the divider for fbdev driver instead of the drm.
Fixes: f76ee892a99e ("omapfb: copy omapdss & displays for omapfb")
Cc: #4.9+
Signed-off-by: Adam Ford
---
Linux 4.4 will need a similar patch, but it doesn't apply cleanly.
The DRM version of this same fix is:
e2c4ed148cf3 ("drm/omap: fix max fclk divider for omap36xx")
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dss.c
b/drivers/video/fbdev/omap2/omapfb/dss/dss.c
index 7252d22dd117..bfc5c4c5a26a 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/dss.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/dss.c
@@ -833,7 +833,7 @@ static const struct dss_features omap34xx_dss_feats = {
};
static const struct dss_features omap3630_dss_feats = {
- .fck_div_max= 32,
+ .fck_div_max= 31,
.dss_fck_multiplier = 1,
.parent_clk_name= "dpll4_ck",
.dpi_select_source = _dpi_select_source_omap2_omap3,
--
2.25.1
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[drm:not-butter 6/12] drivers/gpu/drm/i915/ttm/i915_ttm.c:280:5: error: no previous prototype for 'i915_ttm_bo_create'
tree: git://people.freedesktop.org/~airlied/linux.git not-butter
head: f9de02ab2d4b7fc8d05e5fff0d5b4d8e474bbba5
commit: 5212462bfe5c8cb3f783accd4afd40413c45ac57 [6/12] i915: hacks the planet
config: i386-randconfig-m021-20200630 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
from
drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from
drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:65,
from drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:30:
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning:
'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
|^~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning:
'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=]
75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
|^~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning:
'dc_fixpt_e' defined but not used [-Wunused-const-variable=]
74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
|^~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning:
'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning:
'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning:
'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
|^
In file included from
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:24:
drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:190:18: warning:
'sched_policy' defined but not used [-Wunused-const-variable=]
190 | static const int sched_policy = KFD_SCHED_POLICY_HWS;
| ^~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33,
from
drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from
drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:65,
from
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:24:
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning:
'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
|^~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning:
'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=]
75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
|^~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning:
'dc_fixpt_e' defined but not used [-Wunused-const-variable=]
74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
|^~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning:
'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning:
'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
|^~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning:
'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
|^
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c: In function
'vega20_is_dpm_running':
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:2852:6: warning:
variable 'ret' set but not used [-W
[PATCH v1 4/7] drm/panel: novatek-nt39016: drop use of legacy drm_bus_flags
Drop use of the legacy drm_bus_flags member and use the more descriptive
_SAMPLE_ variant.
No functional change.
Note:
DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = DRM_BUS_FLAG_PIXDATA_NEGEDGE
Signed-off-by: Sam Ravnborg
Cc: Laurent Pinchart
Cc: Thierry Reding
Cc: Sam Ravnborg
---
drivers/gpu/drm/panel/panel-novatek-nt39016.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt39016.c
b/drivers/gpu/drm/panel/panel-novatek-nt39016.c
index 79be3dc4e817..91df050ba3f6 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt39016.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt39016.c
@@ -357,7 +357,7 @@ static const struct nt39016_panel_info kd035g6_info = {
.width_mm = 71,
.height_mm = 53,
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
};
static const struct of_device_id nt39016_of_match[] = {
--
2.25.1
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[PATCH v1 6/7] drm/drm_connector: drop legacy drm_bus_flags values
Drop the now unused legacy drm_bus_flags values.
Signed-off-by: Sam Ravnborg
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
include/drm/drm_connector.h | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 6a451b86c454..7dc804488ccd 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -323,8 +323,6 @@ struct drm_monitor_range_info {
*
* @DRM_BUS_FLAG_DE_LOW: The Data Enable signal is active low
* @DRM_BUS_FLAG_DE_HIGH: The Data Enable signal is active high
- * @DRM_BUS_FLAG_PIXDATA_POSEDGE: Legacy value, do not use
- * @DRM_BUS_FLAG_PIXDATA_NEGEDGE: Legacy value, do not use
* @DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE:Data is driven on the rising
edge of
* the pixel clock
* @DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE:Data is driven on the falling
edge of
@@ -335,8 +333,6 @@ struct drm_monitor_range_info {
* the pixel clock
* @DRM_BUS_FLAG_DATA_MSB_TO_LSB: Data is transmitted MSB to LSB on the
bus
* @DRM_BUS_FLAG_DATA_LSB_TO_MSB: Data is transmitted LSB to MSB on the
bus
- * @DRM_BUS_FLAG_SYNC_POSEDGE: Legacy value, do not use
- * @DRM_BUS_FLAG_SYNC_NEGEDGE: Legacy value, do not use
* @DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE: Sync signals are driven on the rising
* edge of the pixel clock
* @DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE: Sync signals are driven on the falling
@@ -351,20 +347,16 @@ struct drm_monitor_range_info {
enum drm_bus_flags {
DRM_BUS_FLAG_DE_LOW = BIT(0),
DRM_BUS_FLAG_DE_HIGH = BIT(1),
- DRM_BUS_FLAG_PIXDATA_POSEDGE = BIT(2),
- DRM_BUS_FLAG_PIXDATA_NEGEDGE = BIT(3),
- DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = DRM_BUS_FLAG_PIXDATA_POSEDGE,
- DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
- DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
- DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE = DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = BIT(2),
+ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = BIT(3),
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE =
DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE =
DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
DRM_BUS_FLAG_DATA_MSB_TO_LSB = BIT(4),
DRM_BUS_FLAG_DATA_LSB_TO_MSB = BIT(5),
- DRM_BUS_FLAG_SYNC_POSEDGE = BIT(6),
- DRM_BUS_FLAG_SYNC_NEGEDGE = BIT(7),
- DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = DRM_BUS_FLAG_SYNC_POSEDGE,
- DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = DRM_BUS_FLAG_SYNC_NEGEDGE,
- DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_NEGEDGE,
- DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_POSEDGE,
+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = BIT(6),
+ DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = BIT(7),
+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
DRM_BUS_FLAG_SHARP_SIGNALS = BIT(8),
};
--
2.25.1
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[PATCH v1 7/7] drm/drm_connector: use inline comments for drm_bus_flags
Use inline comments for the drm_bus_flags enum.
This makes it easier to add more description comments in the future
should the need arise.
Signed-off-by: Sam Ravnborg
Cc: Laurent Pinchart
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
include/drm/drm_connector.h | 100 +++-
1 file changed, 77 insertions(+), 23 deletions(-)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 7dc804488ccd..af145608b5ed 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -320,43 +320,97 @@ struct drm_monitor_range_info {
* opposite edge of the driving edge. Transmitters and receivers may however
* need to take other signal timings into account to convert between driving
* and sample edges.
- *
- * @DRM_BUS_FLAG_DE_LOW: The Data Enable signal is active low
- * @DRM_BUS_FLAG_DE_HIGH: The Data Enable signal is active high
- * @DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE:Data is driven on the rising
edge of
- * the pixel clock
- * @DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE:Data is driven on the falling
edge of
- * the pixel clock
- * @DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE: Data is sampled on the rising edge of
- * the pixel clock
- * @DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE: Data is sampled on the falling edge of
- * the pixel clock
- * @DRM_BUS_FLAG_DATA_MSB_TO_LSB: Data is transmitted MSB to LSB on the
bus
- * @DRM_BUS_FLAG_DATA_LSB_TO_MSB: Data is transmitted LSB to MSB on the
bus
- * @DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE: Sync signals are driven on the rising
- * edge of the pixel clock
- * @DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE: Sync signals are driven on the falling
- * edge of the pixel clock
- * @DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE: Sync signals are sampled on the rising
- * edge of the pixel clock
- * @DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE: Sync signals are sampled on the falling
- * edge of the pixel clock
- * @DRM_BUS_FLAG_SHARP_SIGNALS:Set if the Sharp-specific
signals
- * (SPL, CLS, PS, REV) must be used
*/
enum drm_bus_flags {
+ /**
+* @DRM_BUS_FLAG_DE_LOW:
+*
+* The Data Enable signal is active low
+*/
DRM_BUS_FLAG_DE_LOW = BIT(0),
+
+ /**
+* @DRM_BUS_FLAG_DE_HIGH:
+*
+* The Data Enable signal is active high
+*/
DRM_BUS_FLAG_DE_HIGH = BIT(1),
+
+ /**
+* @DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE:
+*
+* Data is driven on the rising edge of the pixel clock
+*/
DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = BIT(2),
+
+ /**
+* @DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE:
+*
+* Data is driven on the falling edge of the pixel clock
+*/
DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = BIT(3),
+
+ /**
+* @DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE:
+*
+* Data is sampled on the rising edge of the pixel clock
+*/
DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE =
DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+
+ /**
+* @DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE:
+*
+* Data is sampled on the falling edge of the pixel clock
+*/
DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE =
DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
+
+ /**
+* @DRM_BUS_FLAG_DATA_MSB_TO_LSB:
+*
+* Data is transmitted MSB to LSB on the bus
+*/
DRM_BUS_FLAG_DATA_MSB_TO_LSB = BIT(4),
+
+ /**
+* @DRM_BUS_FLAG_DATA_LSB_TO_MSB:
+*
+* Data is transmitted LSB to MSB on the bus
+*/
DRM_BUS_FLAG_DATA_LSB_TO_MSB = BIT(5),
+
+ /**
+* @DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE:
+*
+* Sync signals are driven on the rising edge of the pixel clock
+*/
DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = BIT(6),
+
+ /**
+* @DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE:
+*
+* Sync signals are driven on the falling edge of the pixel clock
+*/
DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = BIT(7),
+
+ /**
+* @DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE:
+*
+* Sync signals are sampled on the rising edge of the pixel clock
+*/
DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
+
+ /**
+* @DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE:
+*
+* Sync signals are sampled on the falling edge of the pixel clock
+*/
DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
+
+ /**
+* @DRM_BUS_FLAG_SHARP_SIGNALS:
+*
+* Set if the Sharp-specific
[PATCH v1 5/7] drm/panel: panel-simple: drop use of legacy drm_bus_flags
Replace all uses of the legacy drm_bus_flags with their relevant
_SAMPLE_ variant.
This is a 1:1 replacement, no effort was made to validate the actual
bus flags for the panels.
Note:
DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = DRM_BUS_FLAG_PIXDATA_NEGEDGE
DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE = DRM_BUS_FLAG_PIXDATA_POSEDGE
Signed-off-by: Sam Ravnborg
Cc: Laurent Pinchart
Cc: Thierry Reding
Cc: Sam Ravnborg
---
drivers/gpu/drm/panel/panel-simple.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 3a35f74d6cb7..4f0ec5e5b0aa 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -681,7 +681,7 @@ static const struct panel_desc armadeus_st0700_adapt = {
.height = 86,
},
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
};
static const struct drm_display_mode auo_b101aw03_mode = {
@@ -1339,7 +1339,7 @@ static const struct panel_desc cdtech_s070pws19hp_fc21 = {
.height = 86,
},
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
.connector_type = DRM_MODE_CONNECTOR_DPI,
};
@@ -1366,7 +1366,7 @@ static const struct panel_desc cdtech_s070swv29hg_dc44 = {
.height = 86,
},
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
.connector_type = DRM_MODE_CONNECTOR_DPI,
};
@@ -1577,7 +1577,7 @@ static const struct panel_desc edt_et035012dm6 = {
.height = 52,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
};
static const struct drm_display_mode edt_etm043080dh6gp_mode = {
@@ -1720,7 +1720,7 @@ static const struct panel_desc evervision_vgg804821 = {
.height = 64,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
};
static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
@@ -1768,7 +1768,7 @@ static const struct panel_desc frida_frd350h54004 = {
.height = 64,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
.connector_type = DRM_MODE_CONNECTOR_DPI,
};
@@ -1839,7 +1839,7 @@ static const struct panel_desc giantplus_gpm940b0 = {
.height = 45,
},
.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
};
static const struct display_timing hannstar_hsd070pww1_timing = {
@@ -2885,7 +2885,7 @@ static const struct panel_desc ortustech_com37h3m = {
.height = 75, /* 74.88mm */
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE
|
DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
};
@@ -3184,7 +3184,7 @@ static const struct panel_desc sharp_lq070y3dg3b = {
.height = 91, /* 91.4mm */
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE
|
DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
};
@@ -3287,7 +3287,7 @@ static const struct panel_desc sharp_ls020b1dd01d = {
},
.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
.bus_flags = DRM_BUS_FLAG_DE_HIGH
- | DRM_BUS_FLAG_PIXDATA_NEGEDGE
+ | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
| DRM_BUS_FLAG_SHARP_SIGNALS,
};
@@ -3386,7 +3386,7 @@ static const struct panel_desc tfc_s9700rtwv43tr_01b = {
.height = 90,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
};
static const struct display_timing tianma_tm070jdhg30_timing = {
@@
[PATCH v1 1/7] drm/tidss: drop use of legacy drm_bus_flags
Use the more descriptive _DRIVE_ variants thus avoiding the legacy drm_bus_flags values. Signed-off-by: Sam Ravnborg Cc: Laurent Pinchart Cc: Jyri Sarha Cc: Tomi Valkeinen --- drivers/gpu/drm/tidss/tidss_dispc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 629dd06393f6..772a497e8c57 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -997,12 +997,12 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); - ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE); + ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); /* always use the 'rf' setting */ onoff = true; - rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_POSEDGE); + rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); /* always use aligned syncs */ align = true; -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v1 0/7] drm_connector: drop legacy drm_bus_flags
Drop all uses of legacy drm_bus_flags, and then drop the flags. Follow-up with a patch to inline the documentation of the flags. The conversion was triggered by Laurent's clean-up of the bus_flags use in panel-simple. https://lore.kernel.org/dri-devel/20200630135802.ga581...@ravnborg.org/T/#t Build tested only. Patches on top of latest drm-misc-next. Sam (Procrastination, was supposed to review patches, not producing them). Sam Ravnborg (7): drm/tidss: drop use of legacy drm_bus_flags drm/ingenic-drm: drop use of legacy drm_bus_flags drm/panel: raydium-rm67191: drop use of legacy drm_bus_flags drm/panel: novatek-nt39016: drop use of legacy drm_bus_flags drm/panel: panel-simple: drop use of legacy drm_bus_flags drm/drm_connector: drop legacy drm_bus_flags values drm/drm_connector: use inline comments for drm_bus_flags drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +- drivers/gpu/drm/panel/panel-novatek-nt39016.c | 2 +- drivers/gpu/drm/panel/panel-raydium-rm67191.c | 2 +- drivers/gpu/drm/panel/panel-simple.c | 28 +++--- drivers/gpu/drm/tidss/tidss_dispc.c | 4 +- include/drm/drm_connector.h | 124 ++ 6 files changed, 104 insertions(+), 58 deletions(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v1 2/7] drm/ingenic-drm: drop use of legacy drm_bus_flags
Replace the legacy member with the more descriptive _DRIVE_ variant.
No functional change.
Signed-off-by: Sam Ravnborg
Cc: Laurent Pinchart
Cc: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 16f0740df507..deb37b4a8e91 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -419,7 +419,7 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
drm_encoder *encoder,
cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
- if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
+ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
if (!priv->panel_is_sharp) {
--
2.25.1
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